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# EE375 Electronics 1: lab 1

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• 3. CTU: EE 375 – Electronics 1: Lab 1: Regulated DC Power Supply 3 VI. CIRCUIT SCHEMATICS The circuit schematics below were built in PSpice and allowed our team to analyze the circuit digitally before performing the physical build. Figure 4: PSpice Schematic of Design 1 (Part 1). See attachments section for full size image.Figure 2: Hand Calculations for Part 2 (Design using Part 1 Design with addition of filter capacitor). See attachments section for full size image. Figure 5: PSpice Schematic of Design 2 (Part 2), RL=1k. See attachments section for full size image. Figure 6: PSpice Schematic of Design 2 (Part 2) RL=10k. See attachments section for full size image.Figure 3: Hand Calculations for Part 3 (Design using Part2 Design with addition of Zener Diode). See attachments section for full size image. Figure 7: PSpice Schematic of Design 2 (Part 2) RL=100. See attachments section for full size image.
• 4. CTU: EE 375 – Electronics 1: Lab 1: Regulated DC Power Supply 4 capacitance.  A oscilloscope for viewing the input and output waveforms of the circuit.  A power supply/transformer capable of converting a 110(rms)V @ 60Hz to 12.6(rms)V.  A 423.75Ω(220+220) resistor for Ri, and 200Ω (200.2), and 1kΩ (1.05k), 10kΩ (9.98k), 150kΩ(149.5k) resistors for testing RL.  A 83.33µF (100)  Bread board with wires. Figure 8: PSpice Schematic of Design 3 (Part 3) RL=1k.  NOTE: Resistors can normally provide around +/- See attachments section for full size image. 5%-25% difference between actual and designed values while Capacitors generally provide around 20%-50% difference between actual and designed values. You can add resisters in series as (R1+R2) to closer approximate required resistance values and you can add Capacitors in parallel as (C1+C2) to closely approximate required capacitance. VIII. PSPICE SIMULATION RESULTS Figure 9: PSpice Schematic of Design 3 (Part 3) RL=10k. See attachments section for full size image. Figure 12: PSpice Simulation Results of Design 1 (Part 1) Figure 10: PSpice Schematic of Design 3 (Part 3) RL=1k and 10k. See attachments section for full size RL=150k. See attachments section for full size image. image.Figure 11: PSpice Schematic of Design 3 (Part 3) RL=200. See attachments section for full size image. VII. COMPONENT LIST The following is a list of components that were used inbuilding the final DC power supply. (The actual values our Figure 13: PSpice Simulation Results ofgroup used in the build are in parenthesis). Design 2 (Part 2) RL=1k. See attachments  A digital multimeter for measuring circuit section for full size image. voltages, resistor resistances, and capacitor
• 5. CTU: EE 375 – Electronics 1: Lab 1: Regulated DC Power Supply 5 Figure 14: PSpice Simulation Results of Figure 17: PSpice Simulation Results of Design 2 (Part 2) RL=10k. See attachments Design 3 (Part 3) RL=10k. See attachments section for full size image. section for full size image. Figure 15: PSpice Simulation Results of Design 2 (Part 2) RL=100. See attachments Figure 18: PSpice Simulation Results of section for full size image. Design 3 (Part 3) RL=150k. See attachments section for full size image. Figure 16: PSpice Simulation Results of Design 3 (Part 3) RL=1k. See attachments section for full size image. Figure 19: PSpice Simulation Results of Design 3 (Part 3) RL=200. See attachments section for full size image.
• 6. CTU: EE 375 – Electronics 1: Lab 1: Regulated DC Power Supply 6 IX. EXPERIMENTAL DATA produced a greater “ripple” than was allowed by the initial design constraints. However we also observed that the higher The following table illustrates the measurements the value of RL the less “ripple” observed.taken at each stage of the lab. Stage 3: After adding the Zener diode the ripple in our filter rectifier remained constant regardless of whether we used a STAGE 1: Bridge (10k, or 1k resistor). This is most likely due to the voltage Rectifier limiting characteristics of the Zener diode. The V ripple was RL (Actual) VL (Actual) exactly the same “ripple” we achieved from the previous design. 10k (9.98k) 0V to 16.419V After adding the Zener diode, RL produced a 1k (1.05k) 0V to 16.419V constant voltage of approximately 10V. This was true for the 1k, 10k, and 150k resistors. However the 200 ohm resistor 100 (99.2) 0V to 16.419V pushed the Zener diode outside of its Power limitation of .5WTable 1: Stage 1: circuit measurements (Rectifier without producing unstable results at 4.97V. Again all measurements Filter Capacitor) observed were within 10% of Hand and PSpice calculated results. STAGE 2: Includes XI. CONCLUSIONS Filter Capaciter This lab was effective in demonstrating the AC to DC RL (Actual) VL (Actual) rectification capabilities produced by using a bridge rectifier 10k (9.98k) .2V and the power of diodes in restricting current in one direction. Through adding the filter capacitor in phase 2 our team 1k (1.05k) 2.2V observed the how the “ripple” could be smoothed and reduced Table 2: Stage 2: circuit measurements (Rectifier with to exact specifications. Finally in phase 3 after designing the Filter Capacitor) Zener Diode we observed the voltage shunting capabilities of such a diode and observed the importance of choosing a value STAGE 2: Includes of Ri that would allow for lower load impedances in your Filter Capaciter design. This lab was incredibly effective in providing a visual look at diodes and their usefulness in power supplies and RL (Actual) VL (Actual) circuit design. 10k (9.98k) 9.99V XII. ATTACHMENTS 1k (1.05k) 9.983V All figures above follow. 150k (149.5) 10.004V 200 (200.2) 4.97 REFERENCES Table 3: Stage 3: circuit measurements (with Stage 2 and [1] D. A. Neamen, “Microelectronics: circuit analysis and design - 3rd ed.” added Zener diode.) McGraw-Hill, New York, NY, 2007. pp. 1-107. X. ANALYSIS Stage 1: In design 1 the bridge rectifier efficiently producedan expected DC voltage, however the was a tremendous“ripple” that would not have been good for using the Powersupply as a stable power supply. Stage 2: After adding the filter capacitor the output rippleclosely approximated hand and PSpice calculations within10%. The output ripple was also smoothed and greatlyreduced by the capacitor producing a more stable DC output.Our physical calculations, hand and PSpice calculations againwere within 10% proving the validity of our design. Since our filter capacitor was designed using a worstcase scenario of a 1k resister at RL, changing RL below 1k