Ee325 cmos design lab 5 report - loren k schwappach
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics Colorado Technical UniversityPSpice, L-Edit Designed CMOS Inverter Analysis Lab 5 Report Submitted to Professor R. Hoffmeister In Partial Fulfillment of the Requirements for EE 325-CMOS Design By Loren Karl Robinson Schwappach Student Number: 06B7050651 Colorado Springs, Colorado Due: 2 June 2010 Completed: 5 June 2010 1
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics Table of ContentsLab Objectives ..................................................................................................................................................................................................................................... 3Requirements and Design Approaches/Trade-Offs .................................................................................................................................................................. 3L-Edit CMOS Inverter ........................................................................................................................................................................................................................ 4 CMOS Inverter Cross Section ...................................................................................................................................................................................... 4 CMOS Inverter Design Rule Check ............................................................................................................................................................................. 5 CMOS Inverter L-Edit Extracted CMOS.SPC File..................................................................................................................................................... 5 CMOS Inverter Modified SCNA.SPC File ................................................................................................................................................................... 6Voltage Transfer Function of the CMOS Inverter ..................................................................................................................................................................... 7 Circuit Layout .................................................................................................................................................................................................................. 8 PSpice Simulation Results............................................................................................................................................................................................ 9 Truth Table ...................................................................................................................................................................................................................... 9Power Consumption of the CMOS Inverter ..............................................................................................................................................................................10 PSpice Simulation Results..........................................................................................................................................................................................10Small Signal Characteristics of the CMOS Inverter .................................................................................................................................................................11 Circuit Layout ................................................................................................................................................................................................................11 PSpice Simulation Results..........................................................................................................................................................................................11Frequency Response of the CMOS Inverter ..............................................................................................................................................................................12 Circuit Layout ................................................................................................................................................................................................................12 PSpice Simulation Results..........................................................................................................................................................................................13Propagation Delay and Rise/Fall Times of the CMOS Inverter ...........................................................................................................................................14 Circuit Layout ................................................................................................................................................................................................................14 PSpice Simulation Results..........................................................................................................................................................................................15Digital Frequency Response of the CMOS Inverter ................................................................................................................................................................16 PSpice Simulation Results..........................................................................................................................................................................................16Maximum Frequency of the circuit using the CMOS Inverter ............................................................................................................................................17 PSpice Simulation Results..........................................................................................................................................................................................17Output Current Response of the CMOS Inverter .....................................................................................................................................................................18 PSpice Simulation Results..........................................................................................................................................................................................18Pulse response of the CMOS Inverter at various load capacitances. ..................................................................................................................................19 PSpice Simulation Results................................................................................................................................................................................... 19-20Summary of Results .........................................................................................................................................................................................................................21Conclusion and Recommendations .............................................................................................................................................................................................22 2
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics Lab ObjectivesThis objective of this lab is to gain additional experience in the use and features of one of themost popular analog and digital simulation software packages; PSpice (specifically OrCADCapture CIS Demo Version 15.7). As an added objective, the user should complete this labassignment with a greater understanding of the common characteristics of a complimentarymetal-oxide-semiconductor (CMOS) device built using L-Edit Student Edition Version 7.2. Theuser should further be able to compare the characteristics of the L-Edit designed CMOS invertercircuit against the N-channel MOSFET (NMOS) inverter circuit analyzed during EE325 Lab 4,and the IRF-150 Power MOSFET circuit analyzed during EE325 Lab 3. This lab willevaluate/compare the L-Edit CMOS inverter characteristics against the NMOS and IRF-150characteristics from Labs 4 and 3 by generating voltage transfer functions, frequency responsediagrams (bode plots), and the time domain analysis results of specific frequencies needed tocompute the characteristic rise/fall times, propagation delays, and maximum frequencies. Nocharacteristic curve analysis will be completed for this lab report. In addition to evaluationsmentioned previously, this lab will analyze a graph of the CMOS circuits output current I(C L),analyze propagation at adjusted load capacitances, and calculate the effective “on” resistances ofthe n and p-channel MOSFETS of the CMOS circuit. Requirements and Design Approaches / Trade-offsThere are no specific design requirements for this project since it is not a design project, but aPSpice learning / inverter characteristic comparison lab. The primary objective of this lab is tolearn the procedures and methods in using the PSpice simulation software and to identify andanalyze key characteristics of the N complimentary metal-oxide-semiconductor (CMOS) circuitwhile comparing the results against the N-channel MOSFET (NMOS) circuit and the IRF-150Power MOSFET inverter circuit analyzed in labs 4 and 3. To successfully accomplish thePSpice analysis of the CMOS inverter, the user must have successfully created a CMOS inverterin compliance with the MORBN20 design rules and default 2-micron, N-well, double metal, 11-mask CMOS SCNA technology using L-Edit (a basic CMOS inverter layout can be found onfigure 5.9 on Page 5-8 of the book titled “Physical Design of CMOS Integrated Circuits Using L-EDIT” by John P. Uyemura). The CMOS inverter’s P-Channel MOSFET should have a width of52 µm and length of 2 µm, the CMOS inverter’s N-Channel MOSFET should have a width of 22µm and length of 2 µm. After designing the CMOS device the user must extract the CMOSmodel to a location available for PSpice, as well as the L-Edit SCNA.SPC file edited during lab2 (as mentioned in Lab 4), the Cross-Section results, DRC results, and finally the L-Edit CMOSTanner Database File. These files should be compared against the figures / data presented on thefollowing pages. 3
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics L-Edit CMOS Inverter Layout Figure 1: L-Edit CMOS Inverter (rotated right). P-Channel MOSFET (left) W = 52 µm and L = 2 µm. N- Channel MOSFET (right) W = 22 µm and L = 2 µm. The layers used in the L-Edit design of this CMOS inverter are identified below... light purple = P-Select layer, teal = N-Select layer, red = Poly layer (length = 2µm),green = two Active layers {inside (P / N)-Select layers} P-Channel width = 52 µm, N-Channel width = 22 µm, blue = Metal layers with assigned ports (Vin, Vout, Vdd, and Vss), black = Contact layers (54 Active {inside Metal/Active layers}, and 1 Poly {Metal/Poly layer}. Well “ties” were included as shown on the bottom half of the image. L-Edit CMOS Inverter Cross SectionsObtaining the CMOS Inverters cross section was accomplished by clicking Tools/Cross-Section and clicking on the CMOS inverter PMOS and NMOS sections by using the “Pick”button. Figure 2: EE325 L-Edit CMOS Inverter PMOS Cross Section. Figure 3: EE325 L-Edit CMOS Inverter NMOS Cross Section. 4
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics L-Edit CMOS Inverter Design Rule Check Results -------------------- CMOS_DRC.DRC --------------------- DRC Errors in cell Cell0 of file C:Documents and SettingsLorenDesktopLAB 5Lab5. 0 errors. DRC Merge/Gen Layers Elapsed Time: 0.000000 seconds. DRC Test Elapsed Time: 0.000000 seconds. DRC Elapsed Time: 0 seconds. ------------------------------------------------------- L-Edit CMOS Inverter Extracted FileSome important things to not about this file, are the “Node Name Aliases”, these are the netaliases names that must be used in PSpice. Also mentioned are PMOS and NMOS length andwidths. Note that the PMOS Width must be about 2.8 times the NMOS Width. -------------------- CMOS.SPC --------------------- * Circuit Extracted by Tanner Researchs L-Edit V7.12 / Extract V4.00 ; * TDB File: C:Documents and SettingsLorenDesktopLAB 5Lab5, Cell: Cell0 * Extract Definition File: C:LEditmosismorbn20.ext * Extract Date and Time: 06/06/2010 - 21:42 * WARNING: Layers with Unassigned AREA Capacitance. * <Poly Resistor> * <Poly2 Resistor> * <N Diff Resistor> * <P Diff Resistor> * <N Well Resistor> * <P Base Resistor> * WARNING: Layers with Unassigned FRINGE Capacitance. * <Poly Resistor> * <Poly2 Resistor> * <N Diff Resistor> * <P Diff Resistor> * <N Well Resistor> * <P Base Resistor> * <Poly1-Poly2 Capacitor> * <Pad Comment> * WARNING: Layers with Zero Resistance. * <Poly1-Poly2 Capacitor> * <NMOS Capacitor> * <PMOS Capacitor> * <Pad Comment> * NODE NAME ALIASES * 1 = Vdd (-25.5,20) * 2 = Vin (38.5,7.5) * 3 = Vss (72.5,20) * 4 = Vout (38.5,49) M1 Vdd Vin Vout Vdd PMOS L=2u W=52u AD=312p PD=116u AS=312p PS=116u * M1 DRAIN GATE SOURCE BULK (-19 31 33 33) M2 Vss Vin Vout Vss NMOS L=2u W=26u AD=156p PD=64u AS=156p PS=64u * M2 DRAIN GATE SOURCE BULK (43 31 69 33) * Total Nodes: 4 * Total Elements: 2 * Extract Elapsed Time: 0 seconds .END ------------------------------------------------------- 5
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics Edited SCNA.CSE File Required for L-Edit CMOS Inverter in PSpiceLines 2 and 11 of this file were edited to change CMOSN to NMOS and CMOSP to PMOS. -------------------- SCNA.SPC --------------------- * THESE ARE TYPICAL SCNA SPICE LEVEL 2 PARAMETERS .MODEL NMOS NMOS LEVEL=2 LD=0.250000U TOX=417.000008E-10 + NSUB=6.108619E+14 VTO=0.825008 KP=4.919000E-05 GAMMA=0.172 + PHI=0.6 UO=594 UEXP=6.682275E-02 UCRIT=5000 + DELTA=5.08308 VMAX=65547.3 XJ=0.250000U LAMBDA=6.636197E-03 + NFS=1.98E+11 NEFF=1 NSS=1.000000E+10 TPG=1.000000 + RSH=32.740000 CGDO=3.105345E-10 CGSO=3.105345E-10 CGBO=3.848530E-10 + CJ=9.494900E-05 MJ=0.847099 CJSW=4.410100E-10 MJSW=0.334060 PB=0.800000 * Weff = Wdrawn - Delta_W * The suggested Delta_W is -0.25 um .MODEL PMOS PMOS LEVEL=2 LD=0.227236U TOX=417.000008E-10 + NSUB=1.056124E+16 VTO=-0.937048 KP=1.731000E-05 GAMMA=0.715 + PHI=0.6 UO=209 UEXP=0.233831 UCRIT=47509.9 + DELTA=1.07179 VMAX=100000 XJ=0.250000U LAMBDA=4.391428E-02 + NFS=3.27E+11 NEFF=1.001 NSS=1.000000E+10 TPG=-1.000000 + RSH=72.960000 CGDO=2.822585E-10 CGSO=2.822585E-10 CGBO=5.292375E-10 + CJ=3.224200E-04 MJ=0.584956 CJSW=2.979100E-10 MJSW=0.310807 PB=0.800000 * Weff = Wdrawn - Delta_W * The suggested Delta_W is -1.14 um -------------------------------------------------------- 6
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics Voltage Transfer Function for the CMOS Inverter CircuitIn order to begin analyzing the L-Edit CMOS inverter, you must have OrCAD 15.7 Demoinstalled (or a later, working variant). Next open OrCAD Capture CIS and create a newproject using Analog / Mixed (A/D). The main PSpice parts/components we will use in thislab are (Rectangle {acts as a virtual holder for the L-Edit CMOS inverter}, VDC, VAC,VPULSE, 0Ground, C/ANALOG, R/ANALOG, and Net Alias). A rectangle was drawn to act asa virtual placeholder for the L-Edit CMOS inverter device.To generate the voltage transfer function (Vout vs. Vin) of the L-Edit CMOS inverter acircuit design similar to the design used by labs 3 and 4 was used (see figure 4). Youshould notice the absence of the 50 kΩ resister used in Lab 4’s analysis. In addition a“PARAM” (parameter) part was added to allow simulating the load capacitor CL at differentload capacitances. Once you have everything pieced together you are ready to run a PSpicesimulation. First, create a new simulation profile. You must include the L-Edit CMOSinverter “CMOS.SPC” (extracted) and modified “SCNA.SPC” (L-Edit directory) files bylocating them and clicking “Add to Design” under the “Configuration Files” tab as wasrequired mentioned in Lab 4.Simulation settings should be set for a DC Sweep with a Primary Sweep of “Vgate” from 0 Vto 5 V in small 1mV increments. The simulation results are shown by the bottom half offigure 5. You may need to add a trace of “V(Vout)” if you didn’t attach a voltage probe toVout.Next, a line with a slope of 1 was drawn originating from (0 V, 0 V) to (4 V, 4 V). Theintersection of this line with the voltage transfer function graph of V(Vout) was noted asthe L-Edit CMOS inverters logic threshold or switching point. This threshold voltage is thepoint where Vin = Vout, and was determined to be approximately 2.2926 V (-8% of Ideal).The Ideal inverters Logic Threshold is V DD/2 – 0 = 2.5 V. The IRF-150 Power MOSFET’slogic threshold was approx 2.86 V (+15% of Ideal), and the NMOS circuit’s logic thresholdwas approx 1.8299 V (-27% of Ideal).Next a new plot was added to graph the slope (derivative) of “Vout” (Top half of figure 5).Creating a new plot is as simple as clicking plot/new plot and giving the new plot a trace(In this case d(V(Vout))). The points where the new slope = -1 are used to define the noisemargins of this inverter. An easy way to find these locations is by using the searchcommand and typing “search forward level(-1)”. Using this technique twice to find bothlocations where the slope = -1 the following could be defined. Once found you can identifythe specific x-value with the “search forward xvalue(###)” command, where ### is the x-value you are searching for. After adding these coordinates the following data wasobtained (table 1). 7
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics VDrain PARAMETERS: 5Vdc CL_VAL = 1pF 0 Vdd CMOS (Extracted) Device Vin P-CH(W/L) = 52/2 Vout VGate N-CH(W/L) = 22/2 V CL {CL_Val} 5Vdc Vss RS 1 0 0 0 Circuit used for generating the L-Edit CMOS inverter voltage transfer function (Vout vs. Vin)Figure 4: PSpice circuit for generating the L-Edit CMOS inverter voltage transfer function (Vout vs. Vin). Noise Margin Comparison Ideal IRF-150 NMOS CMOS Winner Parameter Inverter Inverter Inverter Inverter % error (vs. Ideal) Logic Threshold or Switching Point 2.5 V 2.8682 V 1.8299 V 2.2926 V CMOS VIH = minimum HIGH input voltage 2.5 V 2.8965 V 2.1214 V 2.6319 V CMOS VIL = maximum LOW input voltage 2.5 V 2.8311 V 941.732 mV 1.8339 V IRF-150VOH = minimum HIGH output voltage 5V 4.9886 V 4.9105 V 4.5787 V IRF-150VOL = maximum LOW output voltage 0V 32.908 mV 711.519 mV 495.124 mV IRF-150Noise Margin Low = NML = VIL – VOL 2.5 V 2.798 V 230 mV 1.3388 V IRF-150Noise Margin High = NMH = VOH – VIH 2.5 V 2.092 V 2.7891 V 1.9468 V NMOS Table 1: L-Edit NMOS Noise Margin Comparison Table, all percentages are rounded. 8
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics -0 S Graph of V(Vout)s Slope l o Interesting points are where Slope = -1 p (1.8339,-1.0000) These points determine Vin(low) and Vin(high) -10 Slope of V(Vout) = -1 Used for finding NML and NMH e (2.6319,-1.0000) Slope of V(Vout) = -1 -20 SEL>> -30 D(V(Vout)) 5.0V V CMOS Voltage Transfer Function o Logic Threshold or Switching Point {Vout vs. Vin (V_VGate)} u (2.2926,2.2926) (1.8339,4.5787) t Vin (low), Vout (high) CMOS NML = Vin(low) - Vout(low) = 1.3388 V CMOS NMH = Vout(high) - Vin(high) = 1.9468 V 2.5V Other Inverter Noise Margins Vin (high), Vout (low) Ideal: NML = 2.5 V, NMH = 2.5 V (2.6319,495.124m) IRF-150: NML = 2.798 V, NMH = 2.092 V NMOS: NML = 230 mV, NMH = 2.7891 V This is a simple strait line (slope = 1) 0V 0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V V(VOUT) V_VGateFigure 5: PSpice simulation results displaying voltage transfer characteristics of the L-Edit CMOS invertercircuit. The top plot is a graph of the slope of V(Vout) the points where slope = -1 and identifies the pointsneeded to calculate the noise thresholds of the device. You can see from the graph of Vout vs. Vin that the L-Edit CMOS NML is -46% of the Ideal NML (the IRF-150 was +12%, and the NMOS was -91%), while the L-Edit CMOS NMH is -22% of the Ideal NMH (the IRF-150 was -16%, and the NMOS was +12%). So the L-Edit CMOS inverters NML is farther from the ideal than the IRF-150’s NML but closer than the NMOS’sNML. However, the CMOS NMH is farther from the ideal than both the IRF-150’s and NMOS’s NMH. Thismeans the L-Edit CMOS inverter will work well for Logic (low) inputs < 1.8339 V and Logic (high) inputs >2.6319 V. The IRF-150 Power MOSFET inverter worked well with Logic (low) inputs < 2.8311 V and Logic(high) inputs > 2.8965 V, and the NMOS inverter worked well with Logic (low) inputs < 941 mV and Logic(high) inputs > 2.121 V. Thus, the IRF-150 circuit had the best NML while the NMOS circuit had the bestNMH. Vin Vout 0 1 1 0 Table 2: Truth table for the L-Edit NMOS inverter.After analyzing figure 5 the truth table above (table 2) can be developed. It is obviousfrom this truth table that this circuit is acting as an inverter; although with a worse NMLthan the IRF-150 Power MOSFET’s NML, and a worse NMH than the IRF-150 PowerMOSFET’s and NMOS circuits NM H. A Vin < 1.8339 V (Low) results in a Vout > 4.5787 V(High), while a Vin > 2.6319 V (High) results in a Vout of 495 mV (Low). 9
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics Power Consumption of the CMOS Inverter CircuitModifications to the circuit used in generating the voltage transfer function (figure 4) arenot required (other than switching the V-probe at “Vout” for a W-probe at “Vdrain”) forfinding the power consumed, nor are modifications to the simulation settings. By running asimulation using a W-probe at “Vdrain” the following results were obtained as shown byfigure 6. 4.0mW P L-Edit CMOS Inverter o Previously Determined w Power Consumed as a function of Vin Logic Threshold, Switching Point e (2.2926,3.4195m) r C 3.0mW Previously Determined o Minimum (High) Input voltage = 2.6319 V n (2.6319,2.6714m) s u m Previously Determined (2.3400,3.5341m) e Maximum (Low) Input voltage = 1.8339 V Max Power = 3.5341 mW 2.0mW d Max (1.8339,1.8475m) 1.0mW Min Power at 0 V = 25 pW Power at 5 V = 25 pW CMOS: Max = 3.5 mW, Min = 25 pW (5.0000,25.177p) (0.000,25.051p) NMOS: Max = 481 uW, Min = 24 pW IRF-150: Max = 25 mW, Min = 56 uW 0W 0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V -W(VDrain) V_VGateFigure 6: PSpice simulation results showing power consumed by the L-Edit CMOS inverter circuit.As observed from figure 6, small power (approx 25 pW) is consumed when the transistoris inverting a low input (Vin) logic Low (0) < approx 1V into an output (Vout) logic High(1), or a high input (Vin) logic High (1) > approx 4V into an output (Vout) logic Low (0).However, maximum power (481 µW) is consumed when the transistor is inverting an input(Vin) logic High (1) or input logic Low (0) at an input voltage near the voltage threshold(switching point). This ensures the CMOS inverter acts as a much more efficient powerconsuming inverter than either the IRF-150 or NMOS inverters.A complex logic circuit composed of 2000 such CMOS inverters, where half have a logic 0 atapprox 0V, and the other half have a logic 1 at approx 5V could consume 50 nW of power(1000 * 25 pW + 1000 * 25 pW = 50 nW). This is immensely smaller (approx. 500 milliontimes smaller) than the power required using only IRF-150 inverters (requires approx.25W), and much smaller (approx. 9.62 million times smaller) than the power requiredusing only NMOS inverters (requires approx. 481 mW). However, if half of the 2000 (1000)CMOS inverters were switching, those inverters would be consume 1000*max power. 10
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics Small Signal Characteristics of the CMOS Inverter CircuitIn order to find the small signal characteristics of the L-Edit CMOS inverter, the VDC powersource “Vgate” voltage was changed (see figure 7) to the threshold voltage determined byfigure 5. VDrain PARAMETERS: 5Vdc CL_VAL = 1pF 0 Vdd CMOS (Extracted) Device Vin P-CH(W/L) = 52/2 Vout VGate N-CH(W/L) = 22/2 CL {CL_Val} 2.2926Vdc Vss RS 1 0 0 0 Circuit used for generating the L-Edit CMOS inverter small signal characteristics. VGate is now at threshold voltage. Figure 7: PSpice circuit used to find the small signal characteristics of the CMOS inverter.Next circuit simulation settings were adjusted for Bias Point analysis, and the check box forcalculating small-signal DC gain was checked. “Vgate” was used as the simulation inputsource and “V(Vout)” was provided as an Output variable name.Small data capture from the bottom of PSpice simulation output file…--------------------------------------------------------------------------------------------------------------------- **** SMALL-SIGNAL CHARACTERISTICS V(Vout)/V_VGate = -2.919E+01 INPUT RESISTANCE AT V_VGate = 1.000E+20 OUTPUT RESISTANCE AT V(Vout) = 2.021E+04---------------------------------------------------------------------------------------------------------------------So the gain is approximately 29.19 (NMOS gain was 5.73, and the IRF-150 gain was 113.7),input resistance is approximately 100 EΩ (exa-ohms) or higher, due to PSpice limits (Sameas NMOS and IRF-150 results), and output resistance (Ro) is approximately 20.21 kΩ(NMOS Ro was 47.92 kΩ (had a 50 kΩ resister in the circuit design)), IRF-150 Ro was 997.8Ω). At this point it seems that this circuit has a better small signal gain than the NMOS, butworse than the IRF-150, an extremely high input impedance and lower output impedancethan the NMOS circuit (had a 50 kΩ resister in the circuit design) but higher outputimpedance than the IRF-150. 11
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics Frequency Response of the CMOS Inverter CircuitTo find the frequency response of the circuit using the L-Edit CMOS Inverter a VAC source(with 1 VAC, and the threshold voltage VDC) was swapped for the VDC source “Vgate” asshown in figure 8. Simulation settings were then adjusted for an “AC Sweep/Noise”analysis to provide a good bode plot diagram showing frequencies from 1Hz to 10GHz(plotted logarithmically) at 10 points per decade. The results shown by figure 9 indicatedthe circuit was behaving like a low pass filter with a corner (f * 3 dB) frequency of 7.0816MHz. You may need to add a trace of “DB(V(Vout))” This indicates that frequencies lessthan the corner frequency will respond better (larger gains realized) than frequenciesgreater than the corner frequency (less gain realized, until eventually the CMOS inverter isunable to keep up with the large frequencies and becomes non-functional. VDrain PARAMETERS: 5Vdc CL_VAL = 1pF 0 Vdd CMOS (Extracted) Device Vin P-CH(W/L) = 52/2 Vout VGate N-CH(W/L) = 22/2 CL {CL_Val} 1Vac Vss 2.2926Vdc RS 1 0 0 0 Circuit used for generating the L-Edit CMOS inverter frequency response. VGate is now a VAC source (1VAC) at threshold DC voltage. Figure 8: PSpice circuit used for finding the CMOS circuit frequency response. 12
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics 30 G a Bode plot for L-Edit CMOS inverter i frequency response n 20 (7.0816M,26.306) ( Corner Frequency (Max -3 dB) d This is the frequency at which B the power out is reduced to 1/2 of max ) .1 * f( 3 dB ) = 708.16 kHz and the voltage gain is reduced .707 of max f( 3 dB ) = 7.0816 MHz Frequency = 7.0816MHz 10 * f( 3 dB ) = 70.816 MHz 0 -20 LAB 4: NMOS Corner Freq. was 2.4262MHz LAB 3: IRF-150 Corner Freq. was 56.410 kHz Note: The CMOS inverter acts like a LP Filter (Approx -17dB / decade) -35 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz 1.0GHz 10GHz 100GHz DB(V(Vout)) FrequencyFigure 9: PSpice simulation results (bode-plot) of CMOS circuit frequency response. Corner freq = 7.0816MHz (Higher than the IRF-150 and NMOS inverters). You should observe that frequencies below 1.5 MHzreceive great gain and allow the CMOS inverter’s switching speeds to approximate that of an ideal inverter.You can see from the results displayed in figure 9 the L-Edit CMOS inverter has a larger cutofffrequency than both the IRF-150 Power MOSFET inverter (7.08 MHz vs. 56 kHz), and theNMOS inverter (7.08 MHz vs. 2.43 MHz). This allows the CMOS inverter to work in a muchlarger, although still limited (frequencies in the GHz range, are widely used today) realm ofengineering circuits. This fact tied together with the power consumption requirements of theCMOS circuit vs. the NMOS and IRF-150 circuits make the CMOS design a sure win especiallyin the power consumption category. 13
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics Propagation Delays of the CMOS Inverter CircuitUsing a frequency slightly lower than f3dB, the circuit was again modified by replacing theVAC source “Vgate” with a Vpulse source as shown by figure 10. At a frequency of 7 MHz(slightly lower than f3dB) use PER = 142.86 ns, PW = 71.429 ns, TR = 1 ps, TF = 1 ps, TD =0, V1 = 0 V, and V2 = 5 V. The simulation Time Domain Analysis was performed to allowthe user to see 3 to 5 periods (run to time = 3 to 5 * PER), and step size < 1/1000 (I used1ps for simplicity). Simulation results are shown on figure 11. VDrain PARAMETERS: 5Vdc CL_VAL = 1pF 0 Vdd CMOS (Extracted) Device Vin P-CH(W/L) = 52/2 Vout V1 = 0 V2 = 5 VGate V N-CH(W/L) = 22/2 CL V {CL_Val} TD = 0 Vss TR = 1ps TF = 1ps PW = 71.429ns RS PER = 142.86ns 1 0 0 0 Circuit used for generating the L-Edit CMOS inverter digitalfrequency response and propogation delays. VGate is now a Vpulse source. Figure 10: PSpice circuit for finding the L-Edit CMOS inverter circuits propagation delays and digital frequency response at f( 3 dB ). 14
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics 5.5VVo Rise / Fall Times and Propogation Delays, frequency = 7 MHz (slightly lower than f(3dB))lt (73.862n,4.5000) (142.929n,5.0000)ag (119.230n,5.0000)e 4.0V (143.087n,4.5000) t(LH) rise .1 Vdd to .9 Vdd t(LH) rise = 2.204 ns t(HL) fall = 1.459 ns Calculated Max Switching Freq = 273 MHz (72.412n,2.5000) (143.713n,2.5000) prop. delay (LH) = 626 ps 2.0V prop. delay (HL) = 784 ps t(HL) fall tP (Prop Delay Time) = 705 ps .9 Vdd to .1 Vdd (71.658n,500.000m) (144.546n,500.000m) 0V (71.486n,0.000) tp(LH) = time to rise from 0 to 2.5 V (146.197n,10.440m) tp(HL) = time to fall from 5 to 2.5 V 70ns 80ns 90ns 100ns 110ns 120ns 130ns 140ns 150ns V(VOUT) TimeFigure 11: PSpice simulation results showing rise time, fall time and propagation delays of CMOS circuit at input freq. = 7 MHz, approximately f(3dB). From the results obtained by figure 11 above we can calculate the following (table 4)..Note a small %error in tPHL and tPLH may be the parasitic capacitance and resistance of the CMOS inverter. CMOS Inverter Rise/Fall Times and Propagation Delay Comparison Parameter Ideal IRF-150 NMOS CMOS WinnertHL = the time it takes output voltage to drop from 4.5 V to .5 V 0s 21 ns 7.3 ns 1.459 ns CMOStLH = the time it takes output voltage to rise from .5 V to 4.5 V 0s 4.453 µs 111.9 ns 2.204 ns CMOStPLH = the time it takes output voltage to rise from 0 to 2.5 V 0s 1.774 µs 35ns 626 ps CMOStPHL = the time it takes output voltage to fall from 5 V to 2.5 V 0s 13 ns 2.7 ns 784 ps CMOStP = Propagation delay time = .5 * ( tPLH + tPHL ) 0s 831 ns 18.9 ns 705 ps CMOSMax Switching Frequency (calculated) = 1/( tLH + tHL ) ∞ 223.5 kHz 8.389 MHz 273 MHz CMOS*Note: Calculated result is usually far off from actual result. Not yet Not yetMax Switching Frequency (observed/actual) ∞ 100 kHz 4.3 MHz Known at this Known at this point. point. Table 4: CMOS Inverter Rise/Fall times and Propagation Delay Comparisons. 15
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter CharacteristicsFrom figure 11 and table 4’s results, the CMOS circuit’s propagation delays and rise/falltimes are much smaller than both the IRF-150 and NMOS circuit’s propagation delays andrise/fall times. This further stakes the claim, that the CMOS inverter circuit is the betterinverter to utilize, for high frequency, low power (digital) applications. Digital Frequency Response of the CMOS Inverter CircuitNow the CMOS inverter circuit’s digital response is analyzed using the circuit from theprevious section (figure 11). The digital response is checked at the corner frequency ofapproximately 7 MHz (as done previously). The results follow… 5.5V V Frequency = 7 MHz slightly lower than f(3dB) o l t a Input g (83.611n,5.0066) e 4.0V Great Inverter response 2.0V Output 0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns 450ns 500ns 550ns V(VOUT) V(VIN) TimeFigure 12: PSpice simulation results showing digital response of output at frequency of 7 MHz (Slightly lowerthan f(3dB {7.0816MHz}). Note the red is the input square pulse (Vin), and the green is the output invertedresponse (Vout). This is acting as a great inverter since the output reaches over 90% of the operating rangewithin a pulse width (at 7 MHz it actually reaches 5 V). This response should improve at lower inputfrequencies, and degrade at greater frequencies. 16
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics Maximum Frequency of the CMOS InverterThe maximum frequency is the frequency at which the output just reaches 90% of theoperating range within a pulse width. Finding the maximum frequency is done through alittle trial and error. Using the corner frequency as a starting position the frequency wasincrementally increased until the output reached 90% of VDD = 4.5 V. This was found to beapproximately 210 MHz, as shown in figure 13 below. The components that limit thefrequency response of the CMOS inverter circuit are the circuit and CMOS deviceresistances, and the circuit 1pF load and CMOS parasitic capacitances. 5.5V V Approximation of Max Frequency Response o l Output reaches approx. 90% of operating range By slowly increasing frequencies the Max freq. was found Approx 4.5 V -> 90% of 5 V t a Frequency = 2.1 MHz (4.7718n,4.4974) g Max Frequency e 4.0V 2.0V 0V 2.5ns 3.0ns 3.5ns 4.0ns 4.5ns 5.0ns 5.5ns 6.0ns 6.5ns 7.0ns V(VOUT) TimeFigure 13: PSpice simulation results of testing freq. = 210 MHz as maximum frequency. Notice outputreaches approx 4.5 V (90% of 5 V).From the result obtained above (figure 13), the CMOS inverter has a much maximumfrequency (210 MHz) than the NMOS (4.3 MHz) and IRF-150 (100 kHz) inverter circuitsanalyzed. The IRF-150 Power MOSFET was the most limiting transistor in this areabecause it is intended for high power, low frequency applications and thus has a muchslower switching speed. Although 210 MHz is a good maximum frequency for a lot oftoday’s electronic devices, many of today’s devices are already exceeding the GHz range. 17
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics Output Current Analysis of the CMOS InverterTo create a plot of the output current the circuit’s Vpulse source “VGate” frequency wasadjusted to 1MHz (PER=1 us, PW = 500 ns, TR/TF = 1 ps), and a current probe was placedat CL. Next a Time Domain Analysis simulation was ran for 1 us with a step size of 10 ps.After scaling the graph the current analysis results were obtained (figure 14). The resultsare explained in the figure.Figure 14: PSpice simulation results of output current I(CL). The n-FET is associated with the right(negative) pulse (where I(CL) goes from approx -3mA to 0) as explained in the figure, while the p-FET isassociated with the left (positive) pulse (where I(CL) goes from -3mA to 0) as explained in the figure.When a logic 1 is applied to the gate (V(Vin) = 5 V, the nFET switch is CLOSED, while thepFET switch is OPEN. Thus the ground (Vss) is connected to the output V(Vout) = Vss = 0V, Discharging the load Capacitor CL (Current travels through the nFET). When a logic 0 isapplied to the gate (V(Vin) = 0 V, the nFET switch is OPEN, while the pFET switch isCLOSED. Thus the logic 1 (power supply) is connected to the output V(Vout) = Vdd = 5 V,Charging the load Capacitor CL (Current travels through the pFET). Current is onlydrawn/pushed by the load capacitor when the CMOS device is switching. 18
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics Pulse Response at Freq of 2 MHz when CL = (1 pF, 10 pF, and 100 pF) To get the pulse responses (rise/fall times and propagation delays) of the CMOS circuit at a frequency of 2 MHz the circuit Vpulse source “VGate”’s frequency was adjusted to 2MHz (PER=500 ns, PW = 250 ns, TR/TF = 1 ps), and a voltage probe was placed at CL. Next a Time Domain Analysis simulation was ran for 750 ns (Start saving after 240 ns) with a step size of 100 ps. Next the “Parametric Sweep” box was checked to allow use of the “global parameter” named “CL_Val” with values: 1 pF, 10 pF, and 100 pF to be created as mentioned at the beginning of this report using the PARAM part. After scaling the graph the various pulse response results were obtained (figure 15). The results are explained in the figure. 5.5VV (264.135n,5.0000) (368.636n,5.0000) 10pF 1pFo 1pF 10pF (500.069n,5.0000) (500.000n,5.0000)l 100pFt (252.433n,4.5000) 1pF (500.227n,4.5000) (499.966n,4.7410) 100pFa 1pFg (271.021n,4.5000) (506.574n,4.5000)e 10pF 100pF 4.0V (501.458n,4.5000) (455.995n,4.5000) 10pF Prop delays & Rise/Fall Times (258.420n,2.5000) See table for calc. results. 10pF Green = 1pF, Red = 10pF, Blue = 100pF 1pF (500.853n,2.5000) (250.985n,2.5000) 1pF (507.060n,2.5000) 100pF 100pF 10pF (331.886n,2.5000) (561.941n,2.5000) 2.0V (250.229n,500.000m) 1pF 100pF 1pF (635.818n,500.000m) (251.626n,500.000m) 10pF (501.689n,500.000m) (514.534n,500.000m) 100pF 10pF 100pF (264.685n,500.000m) 1pF (528.985n,11.231m) (750.000n,24.271m) 1pF, 10pF, and 100pF (503.327n,10.310m) 10pF 0V (249.950n,0.000) 250ns 300ns 350ns 400ns 450ns 500ns 550ns 600ns 650ns 700ns 750ns V(CL:2) Time Figure 15: PSpice simulation results of propagation delays and rise/fall times at various load capacitances. Table below displays the final calculated results. 19
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics CMOS Inverter Rise/Fall Times and Propagation Delay Comparison at various load capacitances. CMOS CMOS CMOS Parameter Ideal IRF-150 NMOS CL = 1pF CL = 10pF CL = 100pFtHL = the time it takes output voltage to drop from 4.5 V to .5 V 0s 21 ns 7.3 ns 1.462 ns 13.076 ns 129.244 nstLH = the time it takes output voltage to rise from .5 V to 4.5 V 0s 4.453 µs 111.9 ns 2.204 ns 19.395 ns 191.31 nstPLH = the time it takes output voltage to rise from 0 to 2.5 V 0s 1.774 µs 35ns 1.035 ns 8.47 ns 81.936 nstPHL = the time it takes output voltage to fall from 5 V to 2.5 V 0s 13 ns 2.7 ns 853 ps 6.991 ns 61.975 nstP = Propagation delay time = .5 * ( tPLH + tPHL ) 0s 831 ns 18.9 ns 944 ps 7.7305 ns 71.9555 nsRp-ch = Resistance of p-channel MOSFET = Rp-ch = (tLH/(2.2*CL)) 1.002 k 881.6 869.6Rn-ch = Resistance of n-channel MOSFET = Rn-ch = (tHL/(2.2*CL)) 664.5 594.4 587.5 Table 5: PSpice simulation calculations for rise/fall times, propagation delays and (p/n)-channel resistances. As noted in the table above, by using the load capacitance and rise/fall times the effective “on” resistances for the pFET and nFET devices were calculated. As the load capacitance increases so does the delay. This increased delay is caused by the increased time needed for the larger capacitor to charge/discharge. 20
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics LAB 5: Summary of Results Evaluation Ideal IRF-150 NMOS CMOS Winner Procedure Parameter Inverter Inverter Inverter Inverter Circuit Circuit Circuit Transfer Char. VThreshold 2.5 V 2.8682 V 1.8299 V 2.2926 V CMOS Noise NMH 2.5 V 2.092 V 2.7891 V 1.9458 V NMOS Margins NML 2.5 V 2.798 V 230 mV 1.3388 V IRF-150 P@0V 0W 56 µW 24 pW 25 pW NMOS/CMOS Power P@5V 0W 25 mW 481 uW 25 pW CMOS 3.5341 PMax 0W 25 mW 481 uW NMOS mW Rise Time tLH 0s 4.453 µs 111.9 ns 2.204 ns CMOS Fall Time tHL 0s 21 ns 7.3 ns 1.459 ns CMOS tPHL 0s 13 ns 2.7 ns 784 ps CMOS Propagation tPLH 0s 1.774 µs 35 ns 626 ps CMOS Delays tP 0s 831 ns 18.9 ns 705 ps CMOSSmall Signal Gain Av ∞ 113.7 5.73 29.19 IRF-150 Rin ∞ ∞ ∞ ∞ 3 Way Tie Impedances Rout 0 997.8 Ω 47.92 kΩ 20.21 kΩ IRF-150 3dB Corner 56.23 2.4262 7.0816 f3dB N/A CMOS kHz MHz MHz Frequency Maximum fMax ∞ 100 kHz 4.3 MHz 210 MHz CMOS Frequency Table 5: Summary of results for Lab 5. 21
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EE325, CMOS Design, Lab 5: L-Edit CMOS Inverter Characteristics Conclusion and RecommendationsThe L-Edit CMOS NML was -46% of the Ideal NML (the IRF-150 was +12%, and the NMOSwas -91%), while the L-Edit CMOS NMH was -22% of the Ideal NM H (the IRF-150 was -16%,and the NMOS was +12%). So the L-Edit CMOS inverters NML was farther from the idealthan the IRF-150’s NML but closer than the NMOS’s NML. However, the CMOS NM H wasfarther from the ideal than both the IRF-150’s and NMOS’s NM H. Thus, the IRF-150 circuithad the best NML while the NMOS circuit had the best NM H, even though the CMOS invertercircuit’s voltage threshold was closer to an ideal than either the NMOS or IRF-150 designs.In addition, the IRF-150 circuit design had the smallest signal output impedance of 997.8 Ω(due to the small 1 kΩ output resister), and largest small signal gain. However, by the endof the lab the additional analysis and comparison of the CMOS inverter against the NMOSand IRF-150 circuits revealed a completely different story (on numerous levels). First, andof great importance, the IRF-150 is a Power MOSFET and demands much larger amounts ofpower than the NMOS inverter circuit. The IRF-150 consumed a minimum of 56 µW (2.3Mtimes more power than the NMOS) to invert a low input into a high output, and consumed25 mW (52 times more power than the NMOS) to invert a high input into a low output.This is a tremendous loss for the IRF-150, since power is of the utmost importance intoday’s digital world. However the CMOS circuit bested both IRF-150 and NMOS circuits byonly using maximum power when switching. Last but not least, the NMOS and IRF-150circuit’s rise/fall times, and propagation delay times were much slower than the CMOScircuit. This allowed the CMOS circuit to operate at frequencies far beyond the range of theIRF-150 or NMOS designs. In summary, both the IRF-150 and NMOS designs failed to beatthe CMOS design as a high frequency, low power, large scale, digital inverter. This labfurther verified when the n-FET and p-FET devices within the CMOS inverter conductedcurrent by analysis of Figure 14, and also demonstrated a way for determining theeffective on resistances of the n-FET and p-FET devices. Overall this was a great lab atdemonstrating why CMOS has become an industry standard. 22
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