Ee 352 lab 1 (tutorial) - schwappach - 15 oct 09

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Ee 352 lab 1 (tutorial) - schwappach - 15 oct 09

  1. 1. EE 352 Digital Design II Individual Lab 1 - Tutorial EE 352 Digital Design II Individual Lab 1 - Tutorial Created by: Loren K. Schwappach Student Number: 06B7050651 Date Due: October 15, 2009 Date Completed: October 15, 2009Loren Karl Schwappach Page 1 of 18 Colorado Technical University
  2. 2. EE 352 Digital Design II Individual Lab 1 - Tutorial Table of ContentsAbstract PageCreating a new Workspace and a new Design (Questions 1-4) PageCreating Project Resources (Questions 5) PageVerilog Source Code Wizard (Questions 6-13) Page10-bit Counter (Questions 14-18) PageTop Level Diagram (Questions 19-25) PageTop Level Schematic (Questions 26-29) PageState Diagram (Questions 30-35) PageSimulation (Questions 36-39) PageDebugging (Questions 40-43) PageGeneral (Questions 44-45) PageToolbar Buttons (Table) PageLoren Karl Schwappach Page 2 of 18 Colorado Technical University
  3. 3. EE 352 Digital Design II Individual Lab 1 - TutorialABSTRACT:This individual Lab was developed for completion to the Aldec, Inc. Active HDL 7.2 VerilogEntry and Simulation Tutorial and questions provided in class by Professor Pamela Hoffman.The Tutorial and questions were distributed in class on 13 October 2009. An electronic versionof the tutorial can be found in the Aldec Active-HDL software, in both the professional andstudent versions, in the following location:Help --> Online Documentation --> Tutorials --> Verilog Entry and Simulation TutorialLoren Karl Schwappach Page 3 of 18 Colorado Technical University
  4. 4. EE 352 Digital Design II Individual Lab 1 - TutorialCREATING A NEW WORKSPACE AND A NEW DESIGN{Starts @ Tutorial Page 1} 1. What is the name of the Workspace that was created for this tutorial? Workspace name: “tutorials”. 2. What is the location of the Workspace that was created for this tutorial? What folders and files were created and stored in this location? Workspace location: “c:my_designs”. The files “library.cfg” and “tutorials.aws” were initially created. Once the New Design Wizard was finished another folder named “tutorial_verilog” was created with the following folders inside… “compile” folder (with “contents.lib~tutorial_verilog” file inside), “log” folder (with “console.log” file inside), “src” folder (empty). The following files were also created within the “tutorial_verilog” folder… “bde.set”, “compilation.order”, “compile.cfg”, “Edfmap.ini”, “projlib.cfg”, “tutorial_verilog.adf”, “tutorial_verilog.lib”, and “tutorial_verilog.wsp”. 3. There are several options available in the New Design Wizard. When each option is selected, a description of that option‟s function is displayed. Explain the function of each of the following options in the new design wizard. a. Create an Empty Design: This option creates an empty design with no synthesis or implementation tool set and disables Design Flow Manager. It also allows you to select a vender, technology and specify the default HDL language of your new design entry sources. b. Create an Empty Design with Design Flow: This option creates an empty design and enables Design Flow Manager. You can select a vender of your synthesis or implementation tool, technology, libraries, and specify the default HDL language of your new design entry sources. c. Add Existing Resource Files: This option creates an empty design, allows specifying sources to be added prior to creating the design, and enables Design Flow Manager. You can select a vendor of your synthesis or implementation tool, technology, libraries, and specify the default HDL language of your new design entry sources. d. Import a Design from Active-CAD: This option creates an empty design, imports an Active-CAD project, and enables Design Flow Manager. You can select a vendor of your synthesis or implementation tool, technology, libraries, and specify the default HDL language of your new design entry sources. 4. In the “Design Browser” window in the upper-left corner of the design environment, there are three tabs, “File”, “Structure”, and “Resources”.Loren Karl Schwappach Page 4 of 18 Colorado Technical University
  5. 5. EE 352 Digital Design II Individual Lab 1 - Tutorial a. What is available in the window associated with the “File” tab at this stage in creating a new design? Workspace „tutorials‟: 1 design(s) Tutorial_verilog  Add New File  Add New Library  Tutorial_verilog library b. What are the folders in the window associated with the “Resources” tab?  Event Lists  Logs o log  console.log  Waveforms  Makefiles  Memory  Dll Libraries  PDF  HTML c. Right-click on each folder in the Resources tab and select “Properties”. For each folder, provide its location and file extension(s) of files to be included in that folder.  Folder name: Event Lists o Directory: c:My_Designstutorialstutorial_verilogsrc o File extensions: lst  Folder name: Logs o Directory: c:My_Designstutorialstutorial_verilog o File extensions: log;htm;xml;txt  Folder name: Waveforms o Directory: c:My_Designstutorialstutorial_verilogsrc o File extensions: awf;asc;asdb;awc  Folder name: Makefiles o Directory: c:My_Designstutorialstutorial_verilog o File extensions: mak  Folder name: Memory o Directory: c:My_Designstutorialstutorial_verilogsrc o File extensions: mem;mif;hex  Folder name: Dll Libraries o Directory: c:My_Designstutorialstutorial_verilog o File extensions: dll  Folder name: PDF o Directory: c:My_Designstutorialstutorial_verilog o File extensions: pdf  Folder name: HTMLLoren Karl Schwappach Page 5 of 18 Colorado Technical University
  6. 6. EE 352 Digital Design II Individual Lab 1 - Tutorial o Directory: c:My_Designstutorialstutorial_verilog o File extensions: none provided d. What is the Library Name for this design? “tutorial_verilog”CREATING PROJECT RESOURCES{Tutorial Page 3} 5. When clicking the “Add New File” Icon located in the “Design Browser” window, the “Add New File” dialog box is displayed. What are the names of the two tabs in this dialog box and what options are available in each? Empty Files  Options: VHDL Source Code, Block Diagram, State Diagram, SystemC Source Code, SystemVerilog Source Code, Verilog Source Code. Wizards  Options: VHDL Source Code, Block Diagram, State Diagram, SystemC Source Code, Verilog Source Code.VERILOG SOURCE CODE WIZARD:{Starts @ Tutorial Page 3} 6. In the dialog screen that is concerned with naming the new source file: a. What information is requested? The name of the source file to be created and the name of the module (optional) are requested. b. Which pieces of information, if any, are optional? The name of the module is optional. c. What is / are the consequences of filling in the optional information? It allows the user to name the module. d. What is / are the consequences of leaving the optional information blank? If the name of the module is not provided the module name is created using the default source file name.Loren Karl Schwappach Page 6 of 18 Colorado Technical University
  7. 7. EE 352 Digital Design II Individual Lab 1 - Tutorial 7. In the tutorial a New Source File was created. a. What was the default type for each input? Wire. b. What was the default type for each output? Wire. 8. What was added to the Design Browser window in the Files tab? Cnt_10b.v 9. What file was generated in the HDL Editor window? What is the file type (extension) of this file? Discuss the generated content of this file including declarations and frameworks. The file below was created… The file name is “cnt_10b.v”, the extension is “.v” indicating a Verilog source file. All Active-HDL components are embedded into an integrated graphical environment referred to as the framework. The framework provides workspace and communication channels for all the components. I have inserted the source file that was created below (highlighted purple) and added commenting to discuss the generated content (highlighted blue). //----------------------------------------------------------------------------- // Title : cnt_10b // Design : tutorial_verilog // Author : Loren K. Schwappach // Company : CTU Student //----------------------------------------------------------------------------- // File : cnt_10b.v // Generated : Thu Oct 15 18:30:24 2009 // From : interface description file // By : Itf2Vhdl ver. 1.21 //----------------------------------------------------------------------------- // Description : //----------------------------------------------------------------------------- `timescale 1 ns / 1 ps //declares a timescale of 1 nanosecond per 1 pulse. //{{ Section below this comment is automatically maintained // and may be overwritten //{module {cnt_10b}}Loren Karl Schwappach Page 7 of 18 Colorado Technical University
  8. 8. EE 352 Digital Design II Individual Lab 1 - Tutorial module cnt_10b ( CLK ,ENABLE ,RESET ,FULL ,COUNT ); //declares a module with //input/output ports CLK ,ENABLE ,RESET ,FULL ,and COUNT. output FULL ; //declares FULL as an output port wire FULL ; //declares FULL as type wire output [9:0] COUNT ; //declares COUNT as a 10-bit output port, [9:0] indicates an array //with array index at [9:0]. wire [9:0] COUNT ; //declares COUNT as type wire input CLK ; //declares CLK as an input port wire CLK ; //declares CLK as type wire input ENABLE ; //declares ENABLE as an input port wire ENABLE ; //declares ENABLE as type wire input RESET ; //declares RESET as an input port wire RESET ; //declares RESET as type wire //}} End of automatically maintained section // -- Enter your statements here -- // //the following lines of code were manually created… reg [9:0] COUNT_I; //declares a array of registers „reg‟ for storing the elements of the //10 bit output port COUNT named COUNT_I reg FULL_I; //declares a register for storing binary output of port FULL named FULL_I //adds behavioral description of code always @ (posedge CLK or posedge RESET) //Do the following at positive edge of CLK //or positive edge of RESET port signals. Always allows for continual execution during //program run. A posedge is any transition from 0, x, and z to 1, and from 0 to z or x. begin //begin architecture, block statement(s), function, process or procedure if (RESET) // asynchronous reset // if RESET input goes high do this begin //begin architectureLoren Karl Schwappach Page 8 of 18 Colorado Technical University
  9. 9. EE 352 Digital Design II Individual Lab 1 - Tutorial COUNT_I = 10b0000000000; //make all COUNT_I bits //low. FULL_I = 1b0; //make FULL_I bit low. end //end architecture else // active clock edge //If RESET is low do the following at each //posedge CLK or posedge RESET begin //begin architecture if (ENABLE) //If ENABLE goes high do this begin //begin architecture if (COUNT_I == 10b1111111111) //if all COUNT_I array bits are high do this FULL_I = 1b1; //make FULL_I high else //otherwise do this COUNT_I = COUNT_I +1; //increment COUNT_I array by 1 end //end architecture end //end architecture end //end architecture assign COUNT = COUNT_I; //assign value from output port COUNT to COUNT_I assign FULL = FULL_I; //assign value from output port COUNT to COUNT_I //this ends the manually created code. endmodule //ends module 10. Where (window and tab) in the design environment is code entered manually? In the HDL Editor window (to the right of the Design Browser, and above the console window), under the commented section // -- Enter your statements here -- //, but above endmodule. 11. What in the Design Browser window, Files tab, indicates that compilation was successful? Once successfully compiled the question mark next to the source file name in the Design Browser/Files tab is replaced by a green check mark next to the compiled source file name indicating compilation was successful.Loren Karl Schwappach Page 9 of 18 Colorado Technical University
  10. 10. EE 352 Digital Design II Individual Lab 1 - Tutorial 12. Where else in the design environment is successful compilation documented? An architecture body is used to describe the behavior, data flow, or structure of a design entity. 13. Is the Architecture associated with the 10-Bit Counter primarily behavioral or structural in nature? A structural body is based on component instantiation and generate statements. It allows hierarchical projects, from simple gates to very complex components, describing entire subsystems. The connections among components are realized through ports. This architecture is primarily behavioral in nature and describes only the expected functionality (behavior) of the circuit, without any direct indication as to the hardware implementation. Such description consists only of one or more processes, each of which contains sequential statements.10-BIT COUNTER{Tutorial Page 5} 14. In the Verilog Source Code File, what is the line of code that initializes the counter? COUNT_I = 10b0000000000; 15. In the Verilog Source Code File, what is the line of code that increments the counter? COUNT_I = COUNT_I +1; 16. Is the 10-Bit Counter positive-edge or negative-edge triggered? How do you know? Positive-edge, always @ (posedge CLK or posedge RESET) 17. Is the Reset synchronous with respect to the clock or asynchronous? How do you know? Asynchronous, if (RESET) // asynchronous reset. Codes executes whenever RESET port input is high regardless of CLK (clock) port input. 18. Based on the code that was generated and the code that was inserted manually, how high will the 10-bit Counter count? Until COUNT_I == 10b1111111111 or 1023 (base 10)TOP LEVEL DIAGRAM{Starts @ Tutorial Page 13 and again @ Tutorial Page 28} 19. When creating and compiling a Block Diagram: a. What file was generated in the HDL Editor window?Loren Karl Schwappach Page 10 of 18 Colorado Technical University
  11. 11. EE 352 Digital Design II Individual Lab 1 - Tutorial freq_m b. What is the file type (extension) of this file? .bde c. Discuss the generated content of this file including declarations and frameworks. I pasted the initial contents of the compiled block diagram Verilog source file (freq_m.v), since the contents of the Block Diagram file is used for port positioning, colors, and alignment. The initial freq_m.v file is pasted below with added comments… //----------------------------------------------------------------------------- // Title : freq_m // Design : tutorial_verilog // Author : Loren K. Schwappach // Company : USAF //----------------------------------------------------------------------------- // File : c:My_Designstutorialstutorial_verilogcompilefreq_m.v // Generated : Thu Oct 15 22:23:20 2009 // From : c:My_Designstutorialstutorial_verilogsrcfreq_m.bde // By : Bde2Verilog ver. 2.01 //----------------------------------------------------------------------------- // Description : //----------------------------------------------------------------------------- `ifdef _VCP `else `define library `endif // ---------- Design Unit Header ---------- // `timescale 1ps / 1ps //declares a timescale of 1 nanosecond per 1 pulse. module freq_m (F_CONV,F_INPUT,PATTERN,RESET,START,FULL,LED_A,LED_B,LED_C ,LED_D) ; //declares a module with input/output ports CLK ,ENABLE ,RESET ,FULL ,and //COUNT. // ------------ Port declarations --------- // input F_CONV; //declares F_CONV as an input port wire F_CONV; //declares F_CONV as type wire input F_INPUT; //declares F_INPUT as an input port wire F_INPUT; //declares F_INPUT as type wireLoren Karl Schwappach Page 11 of 18 Colorado Technical University
  12. 12. EE 352 Digital Design II Individual Lab 1 - Tutorial input PATTERN; //declares PATTERN as an input port wire PATTERN; //declares PATTERN as type wire input RESET; //declares RESET as an input port wire RESET; //declares RESET as type wire input START; //declares START as an input port wire START; //declares START as type wire output FULL; //declares FULL as an output port wire FULL; //declares FULL as type wire output [6:0] LED_A; //declares LED_A as a 7-bit output port, [6:0] indicates an //array with index at [6:0]. wire [6:0] LED_A; //declares LED_A as type wire output [6:0] LED_B; //declares LED_B as a 7-bit output port, [6:0] indicates an //array with index at [6:0]. wire [6:0] LED_B; //declares LED_B as type wire output [6:0] LED_C; //declares LED_C as a 7-bit output port, [6:0] indicates an //array with index at [6:0]. wire [6:0] LED_C; //declares LED_C as type wire output [6:0] LED_D; //declares LED_D as a 7-bit output port, [6:0] indicates an //array with index at [6:0]. wire [6:0] LED_D; //declares LED_D as type wire endmodule d. How many files will the toolbar button, , compile and how does it determine which files to operate on? One, it compiles the active tab shown in the HDL editor window. 20. What window (tab) is generated upon clicking Finish in the design wizard? Describe the initial contents of this window (tab). The freq_m.bde block diagram schematic was created in the HDL editor window now called the Block diagram editor window with input ports (F_INPUT, PATTERN, RESET, START, F_CONV) on the left and output ports (LED_D, LED_C, LED_B, LED_A, FULL) on the right. A table with the ALDEC address, logo, creation date, title, and page are on the bottom of the diagram. 21. What file type(s) is(are) created when using the wizard to create a Block Diagram schematic? A block diagram file (.bde) is created as well as a corresponding Verilog source file (.v) when compiled. 22. What happened in the System Toolbox window when the first instance of cnt_10b was dragged / dropped into the schematic?Loren Karl Schwappach Page 12 of 18 Colorado Technical University
  13. 13. EE 352 Digital Design II Individual Lab 1 - Tutorial It was removed from the Units without symbols section of the Symbols tool box and placed directly under the tutorial_verilog section. 23. After the schematic was compiled in the tutorial, how would one view the VERILOG Source Code associated with that schematic. In which window would the Source Code be displayed? The Verilog source code of the schematic can be viewed by clicking on the corresponding “.v” Verilog source file. The resultant source code appears in the HDL Editor Window (Main Window). 24. What file type(s) was(were) created upon compilation of the schematic. Upon completion the following file types were created and available in the browsers Design Browser files tab… Verilog source files (cnt_10b.v, hex2led.v, bin2bcd.v, fre_m.v, control.v), Block Diagram (freq_m.bde), State Diagram (control.asf), a file named (Sreg()), and the library files (Multiple-Unit, All-Verilog, $root, control, BIN2BCD, cnt_10b, freq_m, and hex2led). There were also two files in the Resources section of the Design Browser under Logs/log (console.log, and freq_m.htm). 25. Is the Architecture associated with the Block Diagram primarily behavioral or structural in nature? Explain your answer. The Architecture is primarily structural. A structural body is based on component instantiation and generate statements. It allows hierarchical projects, from simple gates to very complex components, describing entire subsystems. The connections among components are realized through ports.TOP-LEVEL SCHEMATIC{Starts @ Tutorial Page 16} 26. Explain what is meant by a Top-Down Design Methodology. The Block Diagram Editor lets you create symbols and place them on a diagram to enable later source specification using Verilog or a State Diagram file. This methodology is called top-down designing and is used to build the controlling automata. 27. What is a FUB and how is it used? A fub is a graphical representation of a logic block that is created and edited directly on a diagram sheet. A logic contained within such a block interfaces with the outer environment via ports. Once the fub symbol and its interface have been defined, you can double-click it or use the Push command to create the source file describing the contents of the fub - its implementation.Loren Karl Schwappach Page 13 of 18 Colorado Technical University
  14. 14. EE 352 Digital Design II Individual Lab 1 - Tutorial 28. How does one get to the Fub Properties window and what tabs are available in the Fub Properties window? Right click on the FUB and choose properties. The available tabs are: General, Pin List, Port Mapping, Parameters, Synthesis Attributes, View Texts, and Comment. 29. When a FUB is initially drawn what is the default number of pins? 0.STATE DIAGRAM{Starts @ Tutorial Page 17} 30. Following the “Push” operation, what file type is created? What did the “Push” operation accomplish? Pushing into an empty symbol or empty fub (without contents) creates a new implementation. After choosing State Diagram the state file named control.asf was created. 31. How would the mode of an input port be changed so that it could serve as a clocking signal? What distinguishes the modified port as a clocking signal? To change the mode of a port right click on the port and choose properties, click the clock box and accept changes with OK. The modified port will now have two pulses indicating it is a clocking port. 32. How is a transition from a State to itself, created? Click the state once and then move slightly within the state and click once again. This will create a smooth loop transition. 33. What is the function of the reset signal in a State Diagram and why is it necessary? The reset signal in a State Diagram is used to set the initial/reset state and corresponding outputs. It is necessary to define the initial state as well as state during reset. 34. How was the State Machine (State Diagram) for “control” linked to the associated FUB? By comparing the FUB with its associated state contents diagram and updating the symbol inside Block diagram. 35. What does “Compare Symbol with Contents…” accomplish? It compares the associated symbol or FUB with the contents of its state diagram, updates the symbol/FUB and creates terminals according to the state diagram machine ports.Loren Karl Schwappach Page 14 of 18 Colorado Technical University
  15. 15. EE 352 Digital Design II Individual Lab 1 - TutorialSIMULATION{Starts @ Tutorial Page 34} 36. What is meant by the Active-HDL “Top-Level” architecture and why is it important with respect to Simulation? How is the “Top-Level” distinguished in the design environment? “Top-Level” architecture runs from the top level down. By specifying the freq_m module as the Top Level you allow the simulation the capability of identifying each of the lower level modules required for the simulation. To declare a module as “Top-Level” you right click on the module file beneath the (.v file) and choose Set as Top-Level. It is distinguished from other modules by bolding out the module. According to the Verilog LRM, any Verilog module that is not instantiated anywhere in the design becomes a top- level module. 37. What tab is automatically brought to the front in the Design Browser during Simulation Initialization? The Structure tab. 38. When is it appropriate to use “Compile All” as opposed to “Compile”. Provide an example from the tutorial where “Compile All” was used as opposed to “Compile” and explain the difference in the two situations. When you make changes to multiple files from editing one file (Such as when the control.asf state file was manipulated) “Compile All” is useful to test for errors and compile the entire Workspace. Also, whenever you use the save all command you will need to “Compile-All” to recompile each file. “Compile” is useful when checking a standalone file (active tab). 39. Explain how to save simulation results as a waveform. What file type is created in doing this? The simulation can be saved as waveforms in a native .awf file by clicking the save button on the main toolbar or using the file menu. The results are saved in the src folder and can be used by the test bench.SIMULATION WITH TESTBENCH{Tutorial Page 39 – 44}If you are using the Student Version, you can Skip this section. But you are encouraged toexplore this section using the professional version in the lab.Did this section on Campus, however results did not seem any different than from running thesimulation.Loren Karl Schwappach Page 15 of 18 Colorado Technical University
  16. 16. EE 352 Digital Design II Individual Lab 1 - TutorialDEBUGGING{Tutorial Page 45} 40. What is a Breakpoint and how is it used with respect to Debugging? The breakpoint stops the program from running past a specific point and can be used to isolate specific sections of a program and control program debugging. 41. Describe how the signal and code breakpoints enable step-by-step code debugging. The signal and code breakpoints run until they hit specific sections / signals and stopping at the indicated points to allow the debugger to analyze program throughout runtime. 42. Describe how signal changes may be observed in a Block Diagram (Schematic Editor). Signal changes can be observed as values change within the block diagram as the program runs. 43. Describe how signal changes may be observed in a State Diagram. The state diagram alternates colors to indicate state changes and signal changes within the state diagram.GENERAL 44. Explain the differences between Behavioral and Structural architectures. References examples in the tutorial. Behavioral modeling describes the funtionality of a design by specifying what the designed circuit will do. A structural body is based on component instantiation and generate statements. It allows hierarchical projects, from simple gates to very complex components, describing entire subsystems. The connections among components are realized through ports. This architecture is primarily behavioral in nature and describes only the expected functionality (behavior) of the circuit, without any direct indication as to the hardware implementation. Such description consists only of one or more processes, each of which contains sequential statements. An example of behavioral architecture is seen in the cnt_10b verilog file while structural modeling is seen in the freq_m.bde block diagram. 45. State and explain an instance in the tutorial where smaller design Modules were connected to create a larger more complex Architecture. For example: The cnt_10b module was designed seperatly to simplify the program and troubleshooting and was connected to the freq_m.bde to create the larger architecture.TOOLBAR BUTTONSLoren Karl Schwappach Page 16 of 18 Colorado Technical University
  17. 17. EE 352 Digital Design II Individual Lab 1 - TutorialComplete the following table {Add and / or Expand Rows and/or Columns as needed} Button Function Application / Usage or Select Mode Selects and edits Compile Compiles selected file Compile All Compiles all files Symbols Toolbox Shows Symbols Toolbox Wire Draws a new wire Bus Draws a new bus Places a global wire which binds all unconnected pins of Wire the same name Fub Adds a new fub to the diagram or Input port Adds an input port to the diagram Output port Adds an output port to the diagram State Adds a state to the machine Transition Adds a transition to the machine Adds a reset(synchronous machine)/initial Reset state(asynchronous machine) to the state Condition Adds a condition to the transition State Adds a state action to the state Waveform Creates a new Waveform window List Creates a new List window Step Interval Shows simulation step for run command Run For Advances Simulation by the specified time Run Runs Simulation Run Until Advances simulation to the specified time Restart Restarts Simulation SimulationLoren Karl Schwappach Page 17 of 18 Colorado Technical University
  18. 18. EE 352 Digital Design II Individual Lab 1 - Tutorial Button Function Application / Usage End Simulation Ends running simulation Trace Into Traces into the next statement Trace Over Traces over the next statement Trace Out Traces out of the current procedure Zoom Mode Enlarges the selected part of the diagramLoren Karl Schwappach Page 18 of 18 Colorado Technical University

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