Ex No :1aDESIGN & SIMULATION OF COMBINATIONAL LOGIC CIRCUITS(Structural modeling)Date :AIM:To Design the following Combina...
A & B- InputsS-SumC-CarryVerilog ModuleOutput Waveform2TRUTH TABLEInput OutputA B S C0 0 0 00 1 1 01 0 1 01 1 0 1
b) Full AdderCircuit Diagram& Truth TableA & B- InputsCi-Input CarryS-SumCo-Output CarryVerilog Modulei) Without Instantia...
ii) With Instantiation4
Output Waveformc) Parallel AdderCircuit Diagram5
A3 A2 A1 A0 &B3 B2 B1 B0 areoperands.C0- input carryC4 -output carryS3 S2 S1 S0-SumVerilog ModuleOutput Datad) Multiplexer...
S0S1-Select LinesD0 D1 D2 D3- Input variableX- OutputVerilog ModuleOutput waveform7TRUTH TABLEInputs OutputS0 S1 X0 0 D00 ...
e) De-multiplexerCircuit Diagram & Truth TableS0S1-Select LinesInp- inputO0 O1 O2 O3- OutputVerilog Module8
Output Waveformf) Two- bit Magnitude ComparatorCircuit DiagramVerilog Module9
Output Wave formPROCEDURE:i) Open the application software Xilinx window.ii) Open a new projecta). Give the project name, ...
VIVA QUESTIONS:1. What are Min val & Max val Specifications in Gate Level Modeling?2. What is Wire3. Give the Verilog Data...
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Vlsilab13

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Vlsilab13

  1. 1. Ex No :1aDESIGN & SIMULATION OF COMBINATIONAL LOGIC CIRCUITS(Structural modeling)Date :AIM:To Design the following Combinational Circuits using verilog HDL and Simulate using Xilinxfoundation Series ISE version9.1a) Half Addersb) Full adderc) Parallel adderd) Multiplexere) Demultiplexerf) 2-bit Magnitude ComparatorTOOLS REQUIRED:Simulation Tool: Xilinx ISE 9.1 SimulatorDESIGN:a) Half adderCircuit Diagram& Truth Table1
  2. 2. A & B- InputsS-SumC-CarryVerilog ModuleOutput Waveform2TRUTH TABLEInput OutputA B S C0 0 0 00 1 1 01 0 1 01 1 0 1
  3. 3. b) Full AdderCircuit Diagram& Truth TableA & B- InputsCi-Input CarryS-SumCo-Output CarryVerilog Modulei) Without Instantiation3TRUTH TABLEInput OutputA B Cin Sum Carry0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
  4. 4. ii) With Instantiation4
  5. 5. Output Waveformc) Parallel AdderCircuit Diagram5
  6. 6. A3 A2 A1 A0 &B3 B2 B1 B0 areoperands.C0- input carryC4 -output carryS3 S2 S1 S0-SumVerilog ModuleOutput Datad) MultiplexerCircuit Diagram & Truth Table6
  7. 7. S0S1-Select LinesD0 D1 D2 D3- Input variableX- OutputVerilog ModuleOutput waveform7TRUTH TABLEInputs OutputS0 S1 X0 0 D00 1 D11 0 D21 1 D3
  8. 8. e) De-multiplexerCircuit Diagram & Truth TableS0S1-Select LinesInp- inputO0 O1 O2 O3- OutputVerilog Module8
  9. 9. Output Waveformf) Two- bit Magnitude ComparatorCircuit DiagramVerilog Module9
  10. 10. Output Wave formPROCEDURE:i) Open the application software Xilinx window.ii) Open a new projecta). Give the project name, check for configuration ‘Spartan 3E’ in next window.b). Open new source verilog module, give the file name.c). Give the name for input and output variables of the program.d). Click Finish.iii) Type the program to be synthesized.iv) Save the program.v) Run the synthesis tool.vi) After completion of successful synthesis, click and view the RTL schematic.vii) RTL schematic view window is open and synthesized circuit is seen on the screen.10
  11. 11. VIVA QUESTIONS:1. What are Min val & Max val Specifications in Gate Level Modeling?2. What is Wire3. Give the Verilog Data types?4. What is Hardware Description Language5. Give the Different types of modeling. Arrange them in descending order from highestlevel of abstraction to lowestRESULT:11Preparation /40Output & Result /30Viva /30Total /100

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