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    • ORIGINAL ARTICLE Study on LD-VHDL conversion for FPGA-based PLC implementation Daoshan Du & Yadong Liu & Xingui Guo & Kazuo Yamazaki & Makoto Fujishima Received: 28 September 2007 /Accepted: 31 January 2008 /Published online: 28 February 2008 # Springer-Verlag London Limited 2008 Abstract Programmable logic controllers (PLCs) have been widely used in manufacturing systems for many years. PLC performance is highly constrained by speed of the microprocessor and real-time firmware of the PLC. To enhance conventional PLC performance and flexibility, this paper proposes a new PLC design based on field programmable gate array (FPGA) with parallel execution mechanism and reconfigurable hardware structure. Since ladder diagrams (LD) are the most popular programming language of PLCs, the essential approach of this research is to convert LD programs to equivalent and very high speed integrated circuit hardware description language programs (VHDL), which are the major programming language for FPGA design. This conversion process requires two steps. The first step is to convert the LD program to a VHDL program, in which the LD sequence is controlled by a state machine process. The second step is to optimize the state machine process with concurrent sensitive signals to assure that independent operations in the LD program can be executed in parallel in FPGA. Considering the diversity of LD instructions from different PLC providers, a universal converter with an extended Boolean equation as a bridge is introduced to implement the conversion of LD programs to VHDL. In the second step, the condensed simultaneity graph theory (CSG) is applied to optimize the converted VHDL program with concurrent sensitive signals, which is explained by a practical example. Keywords PLC . Ladder diagram . VHDL . FPGA . CSG 1 Introduction Programmable logic controllers (PLCs) have established a firm place as control elements for logic control of manufacturing systems [1]. To describe the logic sequence, a ladder diagram (LD) is widely used to program PLC applications. It is well known that PLC has a typical software-based implementation structure in which the microprocessor decodes and executes the LD program in a sequential and cyclic way. As a result, PLC performance is limited by the cyclic scan period which depends on the program length and the microprocessor’s processing speed. In order to overcome these drawbacks, a new PLC design, a field programmable gate array (FPGA) based PLC is proposed. It can achieve reconfigurable hardware structure and parallel execution advantage. A number of researchers have focused on this field. Miyazawa [2] and Ikeshita et al. [3] developed a very rough manner in 1999 to convert the graphic ladder diagram into a program description of a very high speed integrated circuit hardware description language (VHDL). Chen and Patyra [4] designed a VHDL model of the whole system directly from the original system requirements to build a controller. Abdel-Hamid et al. [5] and Kuusilinna et al. [6] developed an algorithm to convert FSM into VHDL. Adamski et al. [7–10] conducted effective work in choosing the Petri net model as a substitute of the ladder diagram in manufactur- ing control. These studies show that reconfigurable hard- ware has advantages of simplicity of programming, size, Int J Adv Manuf Technol (2009) 40:1181–1190 DOI 10.1007/s00170-008-1426-4 D. Du (*) :Y. Liu :X. Guo :K. Yamazaki Department of Mechanical & Aeronautic Engineering, IMS-Mechatronics Laboratory, University of California, Davis, CA 95616, USA e-mail: ddu@ucdavis.edu M. Fujishima Mori Seiki Co. Ltd., 2-35-16 Meieki, Nakamura-ku, Nagoya City, Japan
    • and cost, while parallel execution of FPGA can improve the PLC performance dramatically. Generally, the current research stays at a very rough stage by only introducing case-based conversion from PLC descrip- tion language to VHDL. Also, most methods aim at obtaining the hardware description languages (HDL) or the register transfer level (RTL) architecture of FPGA from the original system requirement. As the majority of PLC programs in the manufacturing system are written by LD, it is essential to consider making use of the existing LD programs of the current PLC system to conduct new PLC design. The remainder of this article is organized as follows. Section 2 briefly introduces the FPGA-based PLC design, the research feasibility, and overall approach. Section 3 explains the implementation of conversion from LD to VHDL. The performance optimization of a converted VHDL program considering independent operations with concurrent sensitive signals is discussed in Sect. 4. Section 5 concludes the paper with a brief description of the ongoing work and future research. 2 FPGA-based PLC design As many researchers have explained, FPGA technology has great advantages to conduct new PLC design compared to the traditional software-based PLC solution. The new scheme can improve performance, reduce manufacturing cost, and enforce flexibility of the logic control of the manufacturing system. In order to approach these goals, the essential point is to convert the PLC program into gate- level digital circuit expressions, so that the same control logic of the PLC represented in its program can be exactly reflected in the FPGA-based solution. Since the internal structure of FPGA is reconfigurable, the required circuit can be built as long as a LD program is converted into RTL architecture and downloaded to the FPGA chip. Such an implementation will perform the same functions as the original PLC with LD, but not in the traditional manner with sequential cyclic scan. The new solution can respond to the input signals with parallel execution at electric speed, which dramatically improves the PLC speed. Moreover, it can be reconfigured many times as a new program is converted and downloaded. As for the RTL architecture of FPGA implementation, it is a low level description of the internal logic circuit of FPGA. Several commercial software tools are available. The typical one is Xilinx ISE, which can establish RTL architecture by synthesizing a high level program, VHDL. Therefore, how to convert an LD program into VHDL during implementation of the FPGA-based PLC from the original LD program is the key of this research. Fig. 1 The architecture of converter of LD to VHDL 1182 Int J Adv Manuf Technol (2009) 40:1181–1190
    • 3 Implementation of LD-VHDL conversion A literature survey shows that some research has been proposed in terms of this topic. But most of that work [4– 13] starts from the original requirement specification to establish models such as a state flow model or a Petri-net model and not to make use of the existing resources of the LD program, which ignores the fact that most PLC applications are using LD. The LD is one of the most popular PLC programming languages in industrial control and manufacturing systems. In order to implement FPGA- based PLC, the most valuable approach is to convert the LD program into VHDL, Verilog HDL, or ABEL, the typical FPGA programming languages. In this research, VHDL is selected, which has precise syntax definition and powerful ability to describe complicated systems [14]. One of the most important features of the LD program is the sequential cyclic scan mechanism. When PLC is working, the LD program is executed rung by rung from top to the bottom. However, the FPGA is executed in parallel after a VHDL program is synthesized and down- loaded. Thus, there is a very big difference between the LD program and the VHDL program. For some components in LD, such as normal open and normal close, there are corresponding components in VHDL such as NOT, AND, and OR gates to match. For other components such as self- hold and interlock, there are no corresponding components. Therefore, a bridge is needed to eliminate this gap between these two programs. Several researchers used the modeling method like finite state machine (FSM) or Petri-net as the bridge [5–10, 15]. However, for a complicated LD program, thousands of states could appear, which may easily cause the FSM or Petri-net model to be extremely complex and hard to handle. In this research, the Boolean equations are chosen as the bridge to connect LD to VHDL. Boolean algebra is a system of mathematics often used to manipulate logic and it is very appropriate to describe the logic circuit. Taking the Boolean expression as the bridge, designers only concen- trate on the algorithm to convert LD to a Boolean expression then to VHDL. As a logic descriptor, Boolean expression is often used for the design of logic circuits, so it is much easier to convert LD to Boolean expressions than to other models. Considering different LD instruction sets provided by different PLC producers, a universal converter from LD to VHDL is proposed in this article. Figure 1 shows the architecture of this converter. 3.1 Architecture of the converter As shown in Fig. 1, the converter consists of four parts: the main program frame, PLC instruction dictionaries, dynamic link libraries (DLL) of the Boolean expression generator, and DLL of Boolean expression to VHDL. The main program frame has two components: a LD to Boolean equation converter and a Boolean equation to VHDL converter. When executing the conversions, it calls the others parts to complete the operations. PLC instruction dictionaries are created separately for different PLC types. Each instruction dictionary contains different instruction patterns following the corresponding PLC provider’s specification. When a LD program is processed, the main program frame calls the corresponding decoding function in DLL of the Boolean expression generator to process the instructions and convert them to Boolean expression. The DLLs of the Boolean expression generator are created separately for different PLC producers. The LD includes three types of instructions—common logic, timer/counter, and command—which are processed in different ways. The first is converted into regular Boolean equation. As for the other two, they are repre- sented as extended Boolean expression, the Boolean functions. Then, by referring to the DLL of the Boolean to VHDL converter, the main program frame is going to convert these Boolean equations and functions into VHDL. This is a universal architecture. For different types of PLC LD programs, what needs to be done is to provide the specific PLC instruction dictionaries and two DLL files: one DLL of the Boolean expression generator and the other of the Boolean to VHDL converter, while the main program frame remains the same. Table 1 Boolean expression operator ! & # $ NOT AND OR XOR LD Boolean equation Y1 := (X1 # X2) & (!X3 # X4) Table 2 Example of LD- Boolean equation for common logic Int J Adv Manuf Technol (2009) 40:1181–1190 1183
    • 3.2 Conversion from LD to Boolean equation This component realizes the conversion from LD program to Boolean equations rung by rung. One rung in the LD program is converted into one Boolean equation. Tradi- tional Boolean algebra only includes a logic process. The LD program components are classified as three types of patterns: common combinational logic, timer and counter, and command. The data processing, timer and counter components are different from the common combinational logic. Traditional Boolean algebra can only deal with the first type logic. In order to process all three types with a uniform format, extension to Boolean expression is needed. In this paper, they are handled as follows: 1. Common combinational logic. The essential parts of Boolean algebra are Boolean operators, which are shown in Table 1. These operators correspond to the AND, OR, NOT, and XOR logic. The following symbols for Boolean operation are used. Common combinational logic is the simplest case. For the pure combinational logic, it is easy to write out corresponding Boolean equations according to Boolean algebra. The following example in Table 2 shows how to use operators to convert LD to Boolean equations for common combinational logic. It is an acceptable form for VHDL. In the next step, it is also easy to convert this Boolean equation to a VHDL process statement. 2. Timer and counter. The timer and counter are very important components in the LD program. It can be a coil with a preset parameter, or a contact. In order to describe the LD program with a uniform Boolean equation, an extension is needed. Two cases are taken into account: coil and contact. As for contact, the timer or counter is the same as a common logic device; therefore, it can be processed as the first type. As a coil, a constant parameter is assigned to timer or counter. For example, the T1 (K50), claims it as a timer with 50 ms delay. Then, if a T1 with a parameter is detected, the converter will take it as a timer with preset value K50 and create a 50 ms delay timer in VHDL, just like the example shown in Table 3. 3. Commands. Besides common combinational logic, timer and counter, the LD also has lots of commands, such as program control commands (CALL, CJ) and data processing commands (MOV, >, = <, and +, −, *, /). These commands cannot be described in Boolean equations either, so an extension is also needed. Just like the timer and counter, they are extended by a command with one or more parameters, which lets the converter know a command with corresponding parameter. If the command is in the coil position, the VHDL program will interpret it as an operation, such as move, jump, or mathematics calculation. If the command is in the contact position, the VHDL program will interpret it as a logic device. An example is shown in Table 4. 3.3 Conversion from Boolean equation to VHDL This component realizes the conversion from Boolean equations to VHDL process statements one by one. A complete VHDL program body includes at least four portions: the declaration of the entity, the declaration of the architecture, process statements converted from Boolean equations, and process to control sensitive signals for sequentially activating those processes converted from Boolean equations. In the entity, input ports and output ports of the system are declared. LD Boolean equation T1(K50) :=X1 Y1 := T1 Table 3 Example of LD- Boolean equation for timer or counter LD Boolean equation MOV(D01, D02) :=X1 Y1 :=X2 & LG(D02,D03) Table 4 Example of LD-Bool- ean equation for commands 1184 Int J Adv Manuf Technol (2009) 40:1181–1190
    • Local signals and variables are declared in the architecture. Two kinds of process statements are included in the potential VHDL program. The first one is a series of process statements converted from Boolean equations, here named by regular Boolean processes. The second is to control the sensitive signal to sequentially activate regular process statements, named by state machine processes. In the VHDL program, process statements are running in a concurrent way. For FPGA-based PLC implementation, regular Boolean processes expect to be activated in a sequential way, the same as the original PLC LD does. This can be done with sensitive signals produced by the state machine process. The state machine process is a process activated by clock signal, which will generate the sensitive signals to activate regular Boolean processes in a sequential way. Basically, within one clock period, the state machine process determines which regular Boolean process will be activated in the next clock. By activating those regular Boolean processes in the same order of original LD, the same logic control of PLC can be performed in FPGA. Figure 2 shows an example of the state machine process and regular Boolean processes. FSM_process: process(clock, reset) begin if (reset='1') then current_process <= "000"; elsif (clock'event and clock='1') then if (current_process ="111")then current_process <= "000"; else end if; end if; end process; No_1: process current_process( ) begin if current_state = "001" then Y1 <= (X1 or X2) and ( not X3 or X4); end if; end process No_1; …… (Regular Boolean Process#1) (State Machine Process) Assigning sensitive signal number Sensitive Signal current_process <= current_process + "001"; Fig. 2 The example of the state machine process and regular processes Fig. 3 The LD program and Boolean equations of a simple example Int J Adv Manuf Technol (2009) 40:1181–1190 1185
    • 4 Optimization for the VHDL program 4.1 Optimization for the implementation of the VHDL program in FPGA If all the converted regular Boolean processes were sequen- tially executed in FPGA in the same way as the original LD program, the PLCs performance would not be improved much. The advantage of FPGA-based PLC should be the capability of performing several combinational logic oper- ations concurrently. Therefore, those regular Boolean pro- cesses should be organized not only sequentially but also with parallel structure as much as possible. As mentioned before, the converted VHDL program consists of several portions. The entity declares input ports and output ports of the whole PLC system. The architecture declares local signals and variables used in the LD program. The state machine process describes in which order to perform the regular Boolean processes converted from all rungs of the LD program. The regular Boolean processes handle each of the Boolean logic specified in each rung of the LD program. In the VHDL program, the process statement is the concurrent statement, which is activated by sensitive signals. The state machine process is used to produce the sensitive signals to trigger these regular Boolean processes. Thus, how to organize the regular Boolean processes is equal to how to produce sensitive signals to trigger these processes concurrently or sequentially. In the most basic form, a PLC is a microprocessor-based controller that samples binary input signals at discrete time instants and updates the values of the binary output signals after a delay during which the program is executed. One cycle or scan consists of sampling the input signals once, executing the control program to update the PLCs internal registers, and then writing the new output signals. An LD program consists of many rungs which are all scanned in order on each execution of the LD code. Here one output of one rung exactly is taken as one state variable. Input variables are mapped into one output of a rung according to the Boolean equation of the rung expression. In a given LD program, a rung output may depend upon the output of a previous rung or rungs. The output of the rung is said to be dependent on the state variables explicitly included in the Boolean equation of the rung expression. The scan order of interdependent rungs is critical. To create an equivalent VHDL program to the given LD program, these rungs must be scanned exactly in the same order in the VHDL as in the original LD. Assigning interdependent rungs to sequential sensitive signals guarantees that the original scan order is maintained in the VHDL program. The dependency graph, described later, contains information as to which state variables depend on each other [15, 16]. On the other hand, state variables that are independent from the outputs of other rung or rungs and can be on concurrently in the LD program are assigned to the same sensitive signal in the VHDL program. These VHDL process statements can be activated at the same time. The simultaneity graph, described later, contains information as to which state variables can be on simultaneously [15, 16]. In the following section, a simple example is given to explain how to produce sensitive signals to activate parallel and sequential process in FPGA. 4.2 Explanation of optimization processing with example Here is a chemical neutralization control system used for a neutralization process (Fig. 3). Because this research work orientates a general LD program, the meaning of the neutralization process was irrelevant and only the LD program code was considered. The system has eight state variables: v1, m, h, tl, v4, v2, al, and v3 and six inputs: start, ls1, ls2, ls3, ts, and as. 4.2.1 The simultaneity graph (SG) The first graph of interest is the simultaneity graph (Fig. 4). This undirected graph contains information on which state variables can be on concurrently. This graph has a node for each rung output and an edge connecting the nodes m h v2v4 v3 al tl v1Fig. 4 Simultaneity graph (SG) m h v2v4 v3 al tl v1Fig. 5 Dependency graph (DG) m h v4,v2,v3 al tl v1Fig. 6 Condensed simultaneity graph (CSG) 1186 Int J Adv Manuf Technol (2009) 40:1181–1190
    • corresponding to rung outputs that can be true simulta- neously at the completion of one LD scan. The SG contains the sequential information of the processes in the VHDL program. 4.2.2 The dependency graph (DG) The second graph of interest is the dependency graph (Fig. 5). This directed graph contains information of which rung depends on the outputs of previous rungs during one scan of the LD program. The DG has a node for each state variable in the LD program. Because the DG is a directed graph, each edge is represented by a directed pair <u; v>; u is the tail and v the head of the edge and the edge <u; v> implies that rung v depends on the output of rung u. The DG contains the concurrency information of the processes in the VHDL model. The dependency of the rungs is vital in constructing a VHDL that emulates an LD program because the rungs that depend on previous rungs in the LD must be scanned in the same order. To assure the order of the scan, the rungs connected in the DG and activated by the sequential sensitive signals should be combined. 4.2.3 The condensed simultaneity graph (CSG) In order to maintain the correct operation order of rungs in the LD program, the processes converted from the rungs that depend on the previous rung outputs keep the original order by triggering the assigned sensitive signals in the VHDL program. This process is represented by introducing a third graph (Fig. 6), the condensed simultaneity graph. This is an undirected graph created by condensing the nodes of the simultaneity graph that are connected in the dependency graph into one node. The node interconnections are the same as in the original simultaneity graph. In this graph, more than one rung output can be associated with a node and it contains information on the sequence in the SG and the concurrency in the DG. 4.2.4 Decomposition of CSG Once the CSG is obtained, the decomposition of the CSG is an essential part for producing the set of sensitive signals. The CSG is decomposed into sub-graphs via two decom- positions: the connected component decomposition (CCD) and the full connectivity decomposition (FCD). Connected component decomposition (CCD) Any con- densed simultaneity graph G can be partitioned into its connected components. Given a graph G = (N, E), where N and E are sets of nodes and edges, the CCD of graph G produces a collection of sub-graphs {G1; G2; ......}, such that each Gi =(Ni, Ei), and no node in Gi is connected to a sensitive signals state variable related to activated processes ‘001’ m {(v4,v2,v3},vl,h,tl,al}* m hv4,v2,v3 al tl v1 m hv4,v2,v3 al tl v1 FCD Signal ‘001’ Fig. 7 FCD for ‘m’ node and the assigned sensitive signal ‘001’. * The component includes more state variables than one, but which state variable should be activated first is undetermined sensitive signals state variable related to activated processes ‘001’ m v1 ‘010’ {(v4,v2,v3), h, tl, al}* m hv4,v2,v3 al tl v1 CCD hv4,v2,v3 al tl m v1 Signal ‘001’Signal ‘010’Signal ‘001’ Fig. 8 CCD for ‘v1’ node and the assigned sensitive signal ‘001’. * The component includes more state variables than one, but which state variable should be activated first is undetermined Int J Adv Manuf Technol (2009) 40:1181–1190 1187
    • node in Gj if i 6¼ j. Performing the CCD on the CSG produces one or more sub-graphs to which new sensitive signals are assigned. These newly created sensitive signals are produced in a sequential order. Since no two sensitive signals can be active concurrently, they are sequenced according to the order of state variables appearing in the LD program. Full connectivity decomposition (FCD) A connected graph can be partitioned into a collection of sub-graphs via FCD. The FCD of G is denoted by FCD(G) and FCD(G)={ G1; G2;G3;......}, If i 6¼ j, then every node in Gi is connected to every node in each Gj. After accomplishing FCD, the interconnecting edges are then removed. Since all the components in the sub-graphs are connected to each other according to the physical meaning of SG, activating one component also means the activation of another component. Accordingly, these two components are activated by the same sensitive signal in the VHDL program. 4.3 Optimization processing with CSG step by step According to the original LD program, CSG has been created from SG and DG. It is possible to optimize the organization of the processes in the VHDL program with the theory of CSG decomposition. This still uses the LD program shown in the beginning of this section as the case study to discuss the optimization process (assuming the first sensitive signal appeared in the VHDL program is ‘001’). Step 1 Create the CSG using the definition in Sects. 4.2.1– 4.2.3. Step 2 Apply FCD to node ‘m’. The two sub-graphs {m} and {(v4, v2, v3), vl, h, tl, al} are divided into two concurrent components as shown in Fig. 7. Accordingly, the sensitive signal number, ‘001’, is assigned to these two components, which are activated at the same time. Step 3 Apply CCD to node ‘v1’. According to Sect. 4.2.4, part (2) the {v1} can be separated from the original graph of {(v4, v2, v3), v1, al, tl, h} as shown in Fig. 8. Two sequential subcomponents are divided from the upper level component. They are activated by the sequen- tial sensitive signal. Referring to the order appearing in the LD program, the sensitive signal number is assigned to these two components. Step 4 Repeat step 2 and apply FCD to node ‘al’ and ‘v4, v2, v3’. The sub-graph {{v4, v2, v3}, al, tl, h} can be partitioned into three sub-graphs: {al}, {(v4, v2, v3)} and {tl, h}. The result of FCD to node ‘al’ and ‘v4, v2, v3’ is shown in Fig. 9. sensitive signals state variable related to activated processes ‘001’ m v1 ‘010’ al (v4.v2 v3)* {tl, h}* FCD hv4,v2,v3 al tl m v1 m v1 al v4,v2,v3 h tl Signal ‘010’ Signal ‘001’Signal ‘001’Signal ‘010’ Fig. 9 FCD for ‘al’ ‘tl,h’ and ‘v4,v2,v3’ nodes and the assigned sensitive signal ‘010’. * The component includes more state variables than one, but which state variable should be activated first is undetermined sensitive signals state variable related to activated processes ‘001’ m v1 ‘010’ al (v4.v2 v3)* h ‘011’ tl CCD m v1 al v4,v2,v3 h tl Signal ‘010’ Signal ‘001’ m v1 al v4,v2,v3 htl Signal ‘010’ Signal ‘001’ Signal ‘011’ Fig. 10 CCD for ‘tl,h’ nodes and the assigned sensitive signal ‘010’ and ‘011’. * The component includes more state variables than one, but which state variable should be activated first is undetermined 1188 Int J Adv Manuf Technol (2009) 40:1181–1190
    • These three sub-graphs are in parallel levels and can be activated at the same time, so they are assigned to one sensitive signal number. Step 5 Repeat step 3 and apply CCD to node ‘tl’ and ‘h’. Sub-graph {tl, h} is partitioned into two sub- graphs, {tl} and {h}. Just like step 3, sequential sensitive signals are assigned to these two con- verted processes in the VHDL program and they are activated by sequential sensitive signals in the same order as that in the LD program. The result is shown in Fig. 10. Step 6 Since there are no nodes in CSG that can be decomposed, the connected nodes in DG are finally considered. It has been mentioned that DG shows information of rungs depending on the outputs of previous rungs during one scan of the LD program. In this step, what needs to be done is just assign sequential sensitive signal numbers to the processes converted from these rungs with dependent state variables. Here, sensitive signals ‘010’, ‘011’, and ‘100’ are assigned to v4, v2 and v3, respectively. The result is shown in Fig. 11. After the last step, a complete VHDL program with parallel and sequential portions has been obtained. To the original LD program in this case study, there are eight rungs. If this program is executed in a sequential way as executed in the microprocessor, eight clock cycles are needed. Otherwise, it only needs four clock cycles with both the sequential operation and the parallel operation. The performance becomes more efficient. At the same time, it keeps the function as the original LD program. The new VHDL program keeps not only the sequential operations existing in the LD program for dependent logic control of PLC but also makes full use of the advantage of FPGA to implement the parallel operation for independent logic control. It is very helpful for FPGA-based PLC to get higher performance and thus to upgrade the current PLC design. 5 Conclusion In order to overcome the performance limitation of the traditional microprocessor-based PLC, in this paper a FPGA-based hardware implementation scheme is intro- duced. Two essential issues have been discussed in detail: 1. With a Boolean equation as a bridge, this research proposed a universal architecture to convert different producers’ PLC LD program into a VHDL program. The converted VHDL program can then be synthe- sized into an FPGA chip to form a new PLC implementation. Based on the execution mechanism of clock-driven and sensitive signal-driven processes inside FPGA, the synthesized architecture in FPGA can perform the same functions as the LD program does in traditional PLC. Two steps of conversion have been explained. The first step is to convert the LD program to Boolean equations rung by rung. The second step is to convert Boolean equations to VHDL processes. 2. In order to take the great advantage of FPGA as a reconfigurable hardware circuit, the CSG optimization method is applied to group and reorder the processes in the converted VHDL program. This implements both the sequential and parallel operations to improve the FPGA-based PLC performance. From a practical viewpoint, this research is still in a nascent stage of development. There are several mathemat- ical issues that must be examined. With the rapidly increasing extension of instruction of the LD program and increasing requirements of PLC, much more research needs to be done to improve this work. Acknowledgement The authors wish to express their sincere appreciation for the generous support from Mori Seiki Co. Ltd., which makes this work possible. sensitive signals state variable related to activated processes ‘001’ m v1 ‘010’ al v4 h ‘011’ v2 tl ‘100’ v3 CCD m v1 al v4,v2,v3 htl ‘010’ ‘001’‘011’ m v1 al v4 htl ‘010’ ‘001’‘011’ v2 ‘100’ v3 Fig. 11 CCD for ‘v4,v2,v3’ nodes and the assigned sensitive signal ‘010’, ‘011’ and ‘100’ Int J Adv Manuf Technol (2009) 40:1181–1190 1189
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