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Public ii cielution_imaps_chip_to_system_codesign
 

Public ii cielution_imaps_chip_to_system_codesign

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    Public ii cielution_imaps_chip_to_system_codesign Public ii cielution_imaps_chip_to_system_codesign Presentation Transcript

    • Technologies and Tools Enabling Chip-to-System Co-Design of Electronics Kamal Karimanal Cielution LLC 12/18/2012 Confidential © Cielution LLC
    • AgendaIntroducing Cielution LLCSmartmobile Era & The Need for Thermally AwareChip-System Co Design• Case StudyCompact Thermal Model for Thermal/System AwareIC DesignChip-to-System Thermal Co-Design FlowValidationConclusions 12/18/2012 Confidential © Cielution LLC
    • Who is Cielution?12/18/2012 Confidential © Cielution LLC
    • Cielution Product PipelineCielSpot™ CielMech™• Package Thermal Modeling • Thermo-Mechanical• Package Compact Model Analysis of Assembly GenerationCielSpot-CTM™ o Warpage Mitigation• Thermally Aware IC Layout o Packaging Yield o Traditional Packages Enhancement o 3D Stacked Assemblies o Interconnect Reliability 12/18/2012 Confidential © Cielution LLC
    • Cielution ServicesExpertise Areas• Thermal and Mechanical Simulation • Chip, Package Board and System Level Engineering.Tools Expertise• ANSYS, Icepak, Fluent, CFX, FlothermBusiness Model• Fixed Cost Fixed Time Projects• Hourly rate & Temporary Resources 12/18/2012 Confidential © Cielution LLC
    • 3D Stacked IC Case Study12/18/2012 Confidential © Cielution LLC
    • 3D Stack on interposer Logic 2(22x16) 4 Stacked Dies(8X6) Interposer (36x24) Substrate (40 X 28)All Dimensions in mm 12/18/2012 Confidential © Cielution LLC
    • Packaging & Cooling Scenario I Heat Sink Copper Heat SpreaderPCB Package housing 3D IC stack 12/18/2012 Confidential © Cielution LLC
    • Power Profile Scenario I-A- Non Overlapping (total Power=32.8W) XY 12/18/2012 Confidential © Cielution LLC
    • Temperature Distribution on the chips 12/18/2012 Confidential © Cielution LLC
    • Power Profile Scenario I-B: overlapping. (total Power=32.8W) XY 12/18/2012 Confidential © Cielution LLC
    • Temperature Distribution on the chipsTemperature increased by 16% due to hot spot proximity 12/18/2012 Confidential © Cielution LLC
    • Packaging & Cooling Scenario IIh = 25 W/sq.m/K, Tamb=20C Power Distribution Scenario II-A (total Power=12.7W) 1W 1W 2W 1W 1W 12/18/2012 Confidential © Cielution LLC
    • Temperature Profile for II-a 12/18/2012 Confidential © Cielution LLC
    • Power Profile II-B (total Power=12.7W) 1W 1W 2W 1W 1W 12/18/2012 Confidential © Cielution LLC
    • Power Profile for II bTemperature increased by 26% due to hot spot proximity 12/18/2012 Confidential © Cielution LLC
    • Summary of Hot spot proximity StudyA 3D SOC example was used to study layout implications on for steadystate temperature distribution2 different packaging+cooling solutions were considered • Copper lidded package with Heat sink cooling • MC encapsulated package without heat sinkEach package+cooling scenario was subjected to 2 different sets of powermaps. • Sparsest distribution of hot spots on active chips. • Closest proximity of hot spotsThe case with copper lidded packaging with heat sink predicted 16% highertemperature rise when hot spots were in close proximity.The case with MC encapsulated package without heat sink predicted 26%higher temperature rise when hot spots were in close proximity.The reason for this difference in sensitivity to hot spot alignment is thebetter ability of the heat spreader and heat sink base to spread heat evenwhen hot spots were in close proximity. 12/18/2012 Confidential © Cielution LLC
    • Moral?Heat distribution plays an important role in chip temperature rise.Hot spot proximity between chips produce unintendedconsequences after heterogeneous integration. • This is a new twist which will obsolete the existing thermal management methodologies based on jaPredicted temperature from thermal model are highly sensitive to: • Packaging, Heat sinking, 3D layout of stacked chips, orthotropic nature of laminates, and interconnect arrays.Above sensitivities can only be captured by thermal models using3D numerical discretization. • Spreading and t/KA resistance formulation based approaches have inherent assumptions which tend to introduce unknown uncertainties.However, the fast turn around & automation needed by IC designflow can only be addressed by effective compact models. 12/18/2012 Confidential © Cielution LLC
    • CielSpot for Thermal IC Package Detailed & Compact Thermal Modeling 12/18/2012 Confidential © Cielution LLC
    • CielSpot: High Level Workflow Stack InfoPackage CielSpot™ Material PropertiesInfo Automated Geometry, Meshing & Problem Setup Automated Thermal Snapshots & Temperature data Intelligent Solver Controls Solve in Commercial Thermal Solver Compact Thermal Model Access to Model in the commercial solver’s native format 12/18/2012 Confidential © Cielution LLC
    • CielSpot-CTM Usage: Compact for Fast Solve Without CFD/FEA Pmap for Chip 1 Pmap for Chip 2 Pmap for Chip 2 … Etc…Input Data CielSpot Pre-characterization CielSpot CTM Automated Thermal Snapshots & Temperature data 12/18/2012 Confidential © Cielution LLC
    • Collaborative Thermal Modeling using CielSpot™ OSAT Proprietary Details. Need Third Party Solver Package Details &PackagingOrg. Typical Heatsinking CielSpot Scenarios Package A Compact Model Library Package C Data Cannot be Package B Reverse EngineeredApplication Proprietary Details. Don’t Need Third Party SolverFabless Power Map CielSpotCustomer for Each Chip CTM™ 12/18/2012 Confidential © Cielution LLC
    • CielSpot™ Compact Model Validation12/18/2012 Confidential © Cielution LLC
    • Validation Vehicle 12/18/2012 Confidential © Cielution LLC
    • Validation Approach Stack Info Pre-CharacterizationPackage CompactInfo CielSpot using Commercial Thermal Model Thermal Solver (ANSYS)Pmap for Chip 1Pmap for Chip 2Pmap for Chip 3 CielSpot CTM Temperature Distribution (TCTM )…Etc… Compare %Error = (Tdet-TCTM )/(Tdet -Tamb )*100 Stack Info Package Detailed FEA Thermal Temperature CielSpot™ Info Simulation (ANSYS) Distribution (Tdet ) Power Maps on all Chips 12/18/2012 Confidential © Cielution LLC
    • Layout PMAP for 2.1.1 PMAP for 2.1.1.1 xY 12/18/2012 Confidential © Cielution LLC
    • Error histogram (for all the 1000 monitor locations %Error (FEA Vs 3D Solver)0.60%0.40%0.20%0.00% Probe Location-0.20% %Error (FEA Vs 3D Solver)-0.40%-0.60%-0.80%-1.00% 12/18/2012 Confidential © Cielution LLC
    • SummaryEmphasized the need for exchangeformats, compact models and effectivemethodologies.• Presented Case Study.• Simple rules of thumb such as Rja are obsolete metrics for distributed heat loads on monolithic Chips.• 3D stacks & complex supply chain complicate matters even furtherIntroduced CielSpot™ & CielSpot-CTM™• Proposed Chip-to-System thermal Co-design Methodology suited for the complex Electronics Eco-systemValidation showed that CTM can be as accurate asdetailed thermal model• Much faster than complete CFD o seconds for a complete stacked die with heat sink, PCB and distributed heat loads on each chip and thousands of probe points• Protects IP sensitive details o Suited for system OEM+OSAT to share with Fabless IC supplier. 12/18/2012 Confidential © Cielution LLC