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A Silicon-to-System Thermo-Mechanical Review of Electronics
 

A Silicon-to-System Thermo-Mechanical Review of Electronics

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A Silicon-to-System Review of Thermo-Mechanical Considerations in Electronics ...

A Silicon-to-System Review of Thermo-Mechanical Considerations in Electronics
Author: Kamal Karimanal, Cielution LLC

Thermal and Mechanical challenges to IC package reliability has been addressed with a sufficiently working system of information exchange across a supply chain that spans the foundries to system level assembly plants.The never ending market demand for miniaturization, performance, functionality and cost reduction invariably translates to manufacturing, design, assembly, and reliability challenges to the engineer. Within the Thermal and Mechanical realm these challenges manifest to the engineer in the form of seemingly disconnected problems areas such as BEOL yield, flipchip interconnect reliability, warpage mitigation, heat sink retention design, interface choice, thermally aware board and chassis layout, fan sizing and system level optimization. Evolving technology also introduces newer puzzles such as heterogeneous packaging using 3D ICs. The talk will focus on the tools, methodologies and information exchange protocols used by the thermal management and mechanical reliability professionals across the supply chain to address the various challenges.

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    A Silicon-to-System Thermo-Mechanical Review of Electronics A Silicon-to-System Thermo-Mechanical Review of Electronics Presentation Transcript

    • A Silicon-to-System Review of Thermo-Mechanical Considerations in Electronics Kamal Karimanal, PhD Cielution, LLC
    • Intended Audience Meant for anyone with interest in thermal and mechanical reliability challenges in the electronics supply chain. Technical/Tutorial style presentation… • High level overview that will help you refer to the right resources when you encounter one of the problem classes.
    • Introduction & Agenda Thermal and mechanical reliability concerns permeate all stages of the electronics supply chain. • Crucial to… o Ensuring reliability o Enhancing yield o Designing for price, performance and power goals. Today we will review tools and techniques at the mechanical engineer’s disposal for a few of classes of engineering: • System level thermal management o air cooled telecom example • Component level thermal management. • Stress and warpage management for for 3D IC assembly • Package level Thermal characterization.
    • Thermo-mechanical Challenges in the Electronics Supply Chain
    • System Level Thermal Challenge
    • Telecom System Thermal NEBS (GR-63 standards Reference: Electronics cooling Article by Majid Safavi) • Normal Operating • o 40 Deg. C Ambient Worst case o Elevation 6000 Feet o Ambient temperature = 55 C Acoustic Limits • ~ 85 dBA Component Temperature Limits • Typically 105 deg. C to 115 deg. C Junction temperature for ASICs & FPGAs • ~70 to 85 Case temperature limit for optical trasceivers o Varies depending on SFP, CFP etc., Optical Tranceivers
    • System Thermal Design Funnel Thermal Resistance Stack up Calculation Cooling technology road mapping stage Spreadsheet Calculation Using Lane Budget Method System thermal architecting & thermally aware board layout stage Air Moving Strategy Push or pull only Push+pull air movers Fan vs. blower array Specific fan part # short listing Detailed CFD Analysis & Testing
    • Thermal Resistance Stack up Calculation Heat Loss Through Package Top Heat Loss Through The PCB
    • Resistance Stack Up (Organic Interfaces) 1 Sq. Inch Chip Total Resitance = 0.45 C/W DT over ambient ~ 45 deg. C for 100 W Maybe OK considering un-pre-heated air at 55C No margin if incoming air is already pre-heated by 15 C to 70 deg. C
    • Resistance Stack Up (Solder/Indium Interfaces) Total Resitance = 0.34 C/W DT over ambient ~ 34 deg. C for 100 W OK even for 15 deg. C pre-heated air entering at 70C
    • Mechanical implications of Thermal Management Thermal Calculations Interface Choice o Thermal conductivity of interface material less relevant compared thermal resistance. o R=t/K/A o You could have a high conducting material that doesn’t spread well resulting in a thick cond line thickness (BLT) o BLT of an interface is a function of mounting pressure o Solder Joint Bridging Risk o Board Level Solder Joint Reliability Paper BLT • Mounting Pressure (PSI)
    • System Thermal Design Funnel Thermal Resistance Stack up Calculation Cooling technology road mapping stage Spreadsheet Calculation Using Lane Budget Method System thermal architecting & thermally aware board layout stage Air Moving Strategy Push or pull only Push+pull air movers Fan vs. blower array Specific fan part # short listing Detailed CFD Analysis & Testing
    • Board Level Case Study Tmax (outlet) = 95 C Lane I 250 W Lane II 250 W 55 C air at 6000 ft Elevation Lane III 500 W
    • Lane Calculations • Q = m C p ∆T • Q m= C p ∆T Using the density of air for 6000 ft elevation, we get the following flow rate requirements: • • • • • • 14 CFM for Lanes I & II 28 CFM for III Total 56 CFM. If there are 10 such cards in the Chassis, total flow needed =560 CFM Number of Fans needed on Tray= 560/Actual Flow per Fan What is athe actually realizable flow rate?
    • System Thermal Design Funnel Thermal Resistance Stack up Calculation Cooling technology road mapping stage Spreadsheet Calculation Using Lane Budget Method System thermal architecting & thermally aware board layout stage Air Moving Strategy Push or pull only Push+pull air movers Fan vs. blower array Specific fan part # short listing Detailed CFD Analysis & Testing
    • DP(“ H2O) Cumulative Fan Curve Vs. System Curve Flow Rate (CFM)
    • System Thermal Design Funnel Thermal Resistance Stack up Calculation Cooling technology road mapping stage Spreadsheet Calculation Using Lane Budget Method System thermal architecting & thermally aware board layout stage Air Moving Strategy Push or pull only Push+pull air movers Fan vs. blower array Specific fan part # short listing Detailed CFD Analysis & Testing
    • More than Color Plot Engineering! System Impedence Curve Generation? Accurate estimation of Flow distribution Accurate estimation of heat concentration and Spreading Effect of Turbulence and non-linearities What if Scenarios Optimization
    • Testing Need For Physical test? • • • • Differences between vendor measured fan curves and in-situ fan curves Actual Power generated. Actual Power Distribution on the Chip Variabilities in surface flatness – associated nonuniformity in interface thermal resistance. System
    • Other Classes of System Level Thermal Problems
    • SomeOther Classes of System Level Thermal Problems Conduction Cooled Avionics with External Heat Exchangers Pole Mounted Electronics Enclosure with Solar Irradiation Can you Outsmart the Insulating Sleeve?
    • Warpage and Stress during 3DIC Package Assembly
    • Traditional Flip Chip Process Steps Step I: Silicon, solder bump and substrate bond at reflow temperature (~230 C) 400 to 800 um die Step II: Cool down from 230 C to room temperature Step III: Underfilling, cure at 150 C, Cool to room temperature Step IV: Lid attach/encapsulation at ~120C, cool down to room temp Step V: Ball attach & reflow at ~ 230C, (c) Cielution LLC
    • 3D Assembly Flows "3DIC & TSV Interconnects 2010 Report Series" by Yole development published at http://www.imicronews.com/upload/Rapports/3DTSV_Market_Report_Sample_2010.pdf (viewed on June 10, 2012) (c) Cielution LLC
    • 3D Assembly Flow I: D2D, Chip Stack First, CUF Step 1: Mem Stack to Logic (@ reflow Temperature 230 C) Step 4: Capillary Underfill Step 2: Capillary Underfill Step 3: Chip Stack to Substrate (@ reflow Temperature 230 C) Step 5: Overmolding or Lid Attach (c) Cielution LLC
    • Other Variations Wafer Thinning Carrier Wafer Wafer to be Thinned Wafer to Wafer (W2W) Singulation Chip Stack Follow one of the 3D Assembly Flows (c) Cielution LLC
    • Other Variations Wafer Thinning Carrier Wafer Wafer to be Thinned Die to Wafer (D2W) Bonding Thinned Wafer Carrier Wafer Options? Wafer Level Underfilling? Encapsulation? Carrier Removal Followed by Singulation Follow one of the 3D Assembly Flows (c) Cielution LLC
    • Options for Chip to Chip Attach Micro Bumps Copper Pillar Copper Nails + Thermo Compression (c) Cielution LLC
    • Underfilling Options Capillary Underfill (CUF) No Flow Underfill Copper Nails + Thermo Compression Molded Underfill (Vacuum Assist) No Need to Underfill (c) Cielution LLC
    • 3D IC Stacking Case Study
    • Stack up Description Logic Die (23mmX16mm) Substrate FSRDL Films BSRDL Films Memory Chips 4X4 Memory Stacks (10X6.5) Underfill Regions Logic Die (c) Cielution LLC
    • Assembly Flow I: D2D, Chip Stack First, CUF Step 1: Mem Stack to Logic (@ reflow Temperature 230 C) Step 4: Capillary Underfill Step 2: Capillary Underfill Step 3: Chip Stack to Substrate (@ reflow Temperature 230 C) Step 5: Overmolding (c) Cielution LLC
    • T=20 Deg C results No Warpage at attach temperature since intrinsic stresses at attach were not considered Warpage (um) Flow I Chip Stack warpage on attach+underfill & Cool down -74 um Distance Along Diagonal (um) (c) Cielution LLC
    • Flow I substrate warpage on attach to Chip Stack & Cool down Warpage (um) T=20 Deg C results No Warpage at attach temperature since intrinsic stresses at attach were not considered 412 um Distance Along Diagonal (um) (c) Cielution LLC
    • T=20 Deg C results No Warpage at attach temperature since intrinsic stresses at attach were not considered Warpage (um) Flow I & Flow II substrate warpage on attach to Chip stack, overmolding & Cool down 80 um Distance Along Diagonal (um) (c) Cielution LLC
    • Flow I Consolidated Room Temperature Warpage Evolution T=20 Deg Title Chart C results 500 400 Warpage (um) 300 200 100 0 0 5000 10000 15000 20000 -100 25000 30000 35000 40000 Distance Along Diagonal (um) Logic_die_warpage_after_stack_attach Substrate_warpage_after_stack_attach Sub_warpage_after_full_assembly (c) Cielution LLC
    • Realistic Factors Influencing Warpage @ Attach Material choice for RDL, underfill, encapsulation etc., R, radius of curvature • Film Stress, σ Affects CTE, Modulus Intrinsic Stress in RDL films tf • Affected by process temperature tSi σ f = σ Thermal + σ Intrinsic σf = Chip Attach Temperature E∆α (TD − T ) + E∆α (Tv − TD ) ⇒ E∆α (Tv − T ) (1 −ν ) (1 −ν ) (1 −ν ) 2 t si 1 σ f = − ESi tf R Stoney ' s Formula Besser, Paul R.; Zhai, Charlie, “STRESS-INDUCED PHENOMENA IN METALLIZATION: Seventh International Workshop on Stress-Induced Phenomena in Metallization. AIP Conference Proceedings, Volume 741, pp. 207-216 (2004).” # of Metal layers in RDL & their mismatch between front and back side Process difference between different IC stacks • For Example, Memory Cube using Thermo compression Bond, C4 using traditional reflow + CUF (c) Cielution LLC
    • Assembly Flow II: D2D, Substrate Stack First, CUF Step 1: Mem Stack to Logic (@ reflow Temperature 230 C) Step 4: Capillary Underfill Step 2: Capillary Underfill Step 3: Memory Stack Attach Step 5: Overmolding (c) Cielution LLC
    • Flow II substrate warpage on attach+underfill to thinned logic & Cool down T=20 Deg C results No Warpage at attach temperature since intrinsic stresses at attach were not considered 500 Substrate 1st: Thinned Die on Substrate 400 300 200 Chip Stack 1st: Stacked Chip on Substrate 100 0 0 5000 10000 15000 20000 25000 30000 35000 40000 -100 sub+thinned_die_warpage_Rt sub+chip_stac_Rt (c) Cielution LLC
    • Package Assembly Yield Challenge: Low K Dielectric Risk During Assembly (AKA White Bump Risk) (c) Cielution LLC
    • White Bump Failure Driver Low K Dielectric Step I: Silicon, solder bump and substrate bond at reflow temperature (~230 C) Differential Shrinkage Step II: Cool down from 230 C to room temperature Compressive Stresses Tensile & Shear Stresses Step III: Underfilling, cure at 150 C, Cool to room temperature Step IV: Lid attach/encapsulation at ~120C, cool down to room temp Step V: Ball attach & reflow at ~ 230C, (c) Cielution LLC
    • FEA Modeling Details for White Bump Risk Bond bump array and chip 2 to chip 1 at reflow solidification temperature Displacement BC Change temperature as load steps to realize warpage and stresses. Cut out sub-model, transfer displacement profile, and simulate temperature load steps Additional Sub Model levels as needed for Fracture Mechanics Analysis (c) Cielution LLC
    • Package Level Thermal
    • Current Package Level Thermal Characterization
    • Package Level Characterization needed form 3D ICs Automated Thermal Snapshots & Temperature data
    • Collaborative Thermal Modeling using CielSpot™ OSAT Proprietary Details. Need Third Party Solver Packaging Org. Package Details & Typical Heatsinking Scenarios Package A CielSpot Compact Model Library Package B Package C Data Cannot be Reverse Engineered Application Proprietary Details. Don’t Need Third Party Solver Fabless Customer Power Map for Each Chip CielSpot CTM™ (c) Cielution LLC
    • Conclusions Reviewed a few commonly practiced thermal and mechanical methodologies for design and assembly. Hand Calculations, Spreadsheet, Numerical analysis as well as Testing are essential parts of the overall product development cycle.