ARM cortex A15
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ARM cortex A15 ARM cortex A15 Presentation Transcript

  • By Komal Yamgar 1
  • AGEND A SLIDE NO • INTRODUCTION 3 3 • GENERAL CONCEPT 4 4 • ARM CORTEX A15 5 5 • FEATURES 6 6 • APPLICATION 12 12 • SUMMARY 14 14 • REFERENCES 15 15 2
  • ARM CORTEX A15 is in production late 2011, to market late 2012. Designed by ARM. The Cortex-A15 MPCore processor is the latest member of the Cortex-A series of processors. The ARM Cortex -A15 MP Core processor is the highestperformance licensable processor the industry has ever seen. It delivers unprecedented processing capability, combined with low power consumption. 3
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  • ARM CORTEX A 15 ARM Cortex-A15 Core Produced In production late 2011, to market late 2012 Designed by ARM Max. CPU clock rate 1.0 GHz to 2.5 GHz Min. feature size 32 nm/28 nm initially to 20 nm roadmap Instruction set ARMv7 Cores 1-4 per cluster, 1-2 clusters per physical chip L1 cache 64 kB (32 kB I-Cache, 32 kB D-Cache) per core L2 cache up to 4 MB L3 cache None 5
  • Key features of the Cortex-A15 core •NEON •SIMD. •VFPv4 Floating Point Unit. •Thumb-2 instruction set encoding reduces the size of programs with little impact on performance. •TrustZone security. •Jazelle . 6
  • Single Instruction Multiple Data (SIMD) • Some modern software, particularly media codecs and graphics accelerators, operate on large amounts of data that is less than wordsized. • Generally audio applications uses 16-bit data , graphics and video uses 8bit data . • When performing these operations on a 32-bit microprocessor, parts of the computation units are unused, but continue to consume power. • uses a single instruction to perform the same operation in parallel on multiple data elements of the same type and size. • This way, the hardware that normally adds two 32-bit values instead performs four parallel additions of 8-bit values in the same amount of time.
  • EXAMPLE Instruction UADD8 R0, R1, R2. This operation performs a parallel addition of four lanes of 8-bit elements packed into vectors stored in general purpose registers R1 and R2, and places the result into a vector in register R0. 4-way 8-bit unsigned integer add operation
  • NEON NEON technology is implemented on all current ARM Cortex-A series processors. NEON instructions are executed as part of the ARM or Thumb instruction stream. This simplifies software development, debugging, and integration compared to using an external accelerator. Traditional ARM or Thumb instructions manage all program flow and synchronization. The NEON instructions perform: • memory accesses • data copying between NEON and general purpose registers • data type conversion • data processing. 9
  • EXAMPLE INSTRUCTION :- VADD.I16 Q0, Q1, Q2 VADD.I16 Q0, Q1, Q2 instruction performs a parallel addition of eight lanes of 16-bit elements from vectors in Q1 and Q2, storing the result in Q0. The NEON instructions support 8-bit, 16-bit, 32-bit, and 64-bit signed and unsigned integers. 8-way 16-bit integer add operation. 10
  • TrustZone security It enbles system-wide security by integrating protective measures into the ARM processor and system peripheral IP. This ensure that the sensitive data remains safe. ARM Jazelle Technology Jazelle technology accelerates mobile phone Java applications and increases battery life. NewJazelle technology to dramatically reduce application memory footprint Increases performance and power saving in a wide range of applications including • Mobile phones • Consumer devices. 11
  • APPLICATIONS Smartphone and Computing Usage range: •1 GHz – 1.5 GHz single or dual-core configurations Device characteristics: •Elastic performance: o Instant web-browsing, high-bandwidth operation o Increasing media and floating-point performance •Optimum power: o Extended low-power range and better battery life •Richer experience: o Console-quality gaming, navigation applications Digital Home Entertainment Usage range: •1 GHz – 2 GHz dual-core or quad-core configurations Device characteristics: • High-end performance: o General-purpose and media performance . o Intensive streaming, o Media and graphics and compute workloads. •Larger physical memory: o Larger than 4GB of memory attached 12
  • Samsung outs a dual-core ARM Cortex A15 chip with 2560x1600 display support The block diagram for Samsung's new Exynos 5 Dual SoC 13
  • SUMMARY The Cortex-A15 extends the application processor family with Dramatic increase in single-thread and overall performance.Compelling new features, functionality enable exciting OEM products Scalability for large-scale computing and system-on-chip integration Cortex-A15 has strong momentum in mobile market. ARM Cortex-A family provides broadest range of processors .utra-low cost smartphonesthrough to tablets and beyondFull upward software and feature-set compatibility Address cloud computing challenges from end to end. 14
  • REFERENCES RESEARCH PAPERS [1] Cortex™-A15 Revision: r2p0 Technical Reference Manual. [2] W H I T E P A P E R Brian Carlson OMAP 5 Product Line Manager Member of Group Technical Staff (MGTS) Wireless business unit. © 2011 Texas Instruments Incorporated. [3] W H I T E P A P E R ‘ARM NEON support in the ARM’ REFERENCE BOOKS [4] Embedded Real Time System: Concepts , Design & Programming, Dr.K.VK.K.Prasad,Dreamtech Publication. WEBSITE [5] WWW.ARM.COM [6]www.google.com [7] www.wikipedia.com [8] New Samsung Cortex A15-based chip opens door to “Retina” Android tablets _ Ars Technica.htm 15
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