ARM CORTEX A15
ARM CORTEX A15 is in production late 2011, to market late
Designed by ARM.
The Cortex-A15 MPCore processor is the latest member of the
Cortex-A series of processors.
The ARM Cortex -A15 MP Core processor is the highestperformance licensable processor the industry has ever seen.
It delivers unprecedented processing capability, combined with
low power consumption.
ARM CORTEX A 15
ARM Cortex-A15 Core
In production late 2011, to market late 2012
Max. CPU clock rate
1.0 GHz to 2.5 GHz
Min. feature size
32 nm/28 nm initially to 20 nm roadmap
1-4 per cluster, 1-2 clusters per physical chip
64 kB (32 kB I-Cache, 32 kB D-Cache) per core
up to 4 MB
Key features of the Cortex-A15
•VFPv4 Floating Point Unit.
•Thumb-2 instruction set encoding reduces the size of
programs with little impact on performance.
Single Instruction Multiple Data (SIMD)
Some modern software, particularly media codecs and graphics
accelerators, operate on large amounts of data that is less than wordsized.
Generally audio applications uses 16-bit data , graphics and video uses 8bit data .
When performing these operations on a 32-bit microprocessor, parts of
the computation units are unused, but continue to consume power.
uses a single instruction to perform the same operation in parallel on
multiple data elements of the same type and size.
This way, the hardware that normally adds two 32-bit values instead
performs four parallel additions of 8-bit values in the same amount of
Instruction UADD8 R0, R1, R2.
This operation performs a parallel addition of four lanes of 8-bit elements packed
into vectors stored in general purpose registers R1 and R2, and places the result
into a vector in register R0.
4-way 8-bit unsigned integer add operation
NEON technology is implemented on all current ARM Cortex-A
NEON instructions are executed as part of the ARM or Thumb
This simplifies software development, debugging, and integration
compared to using an external accelerator.
Traditional ARM or Thumb instructions manage all program flow and
The NEON instructions perform:
• memory accesses
• data copying between NEON and general purpose registers
• data type conversion
• data processing.
VADD.I16 Q0, Q1, Q2
VADD.I16 Q0, Q1, Q2 instruction performs a parallel addition of eight
lanes of 16-bit elements from vectors in Q1 and Q2, storing the result in Q0.
The NEON instructions support 8-bit, 16-bit, 32-bit, and 64-bit signed and
8-way 16-bit integer add operation.
It enbles system-wide security by integrating protective measures into
the ARM processor and system peripheral IP.
This ensure that the sensitive data remains safe.
ARM Jazelle Technology
Jazelle technology accelerates mobile phone Java applications and increases
NewJazelle technology to dramatically reduce application memory footprint
Increases performance and power saving in a wide range of applications
• Mobile phones
• Consumer devices.
Smartphone and Computing
•1 GHz – 1.5 GHz single or dual-core configurations
Instant web-browsing, high-bandwidth operation
Increasing media and floating-point performance
Extended low-power range and better battery life
Console-quality gaming, navigation applications
Digital Home Entertainment
•1 GHz – 2 GHz dual-core or quad-core configurations
• High-end performance:
General-purpose and media performance .
Media and graphics and compute workloads.
•Larger physical memory:
Larger than 4GB of memory attached
Samsung outs a dual-core ARM Cortex A15 chip with
2560x1600 display support
The block diagram for Samsung's new Exynos 5 Dual SoC
The Cortex-A15 extends the application processor family with Dramatic
increase in single-thread and overall performance.Compelling new features,
functionality enable exciting OEM products Scalability for large-scale computing
and system-on-chip integration Cortex-A15 has strong momentum in mobile
ARM Cortex-A family provides broadest range of processors .utra-low cost
smartphonesthrough to tablets and beyondFull upward software and feature-set
compatibility Address cloud computing challenges from end to end.