1. ENGIN 112
Intro to Electrical and Computer
Engineering
Lecture 25
State Reduction and Assignment
ENGIN112 L25: State Reduction and Assignment October 31, 2003

2. Overvie
w
° Important to minimize the size of digital circuitry
° Analysis of state machines leads to a state table (or
diagram)
° In many cases reducing the number of states reduces
the number of gates and flops
• This is not true 100% of the time
° In this course we attempt state reduction by examining
the state table
° Other, more advanced approaches, possible
° Reducing the number of states generally reduces
complexity.
ENGIN112 L25: State Reduction and Assignment October 31, 2003

3. Fini
te
°Stat
Example: Edge Detector
e
Mac Bit are received one at a time (one per cycle),
hin
es such as: 000111010 time CLK
IN FSM OUT
Design a circuit that asserts
its output for one cycle when
the input bit stream changes
from 0 to 1.
Try two different solutions.
ENGIN112 L25: State Reduction and Assignment October 31, 2003

4. Stat
e
Tra IN=0
nsit
ion
ZERO
Dia IN=0
IN PS NS OUT
OUT=0
gra 0 00 00 0
m IN=1 ZERO
IN=0 1 00 01 0
Sol
utio CHANGE
0 01 00 1
nA CHANGE 1 01 11 1
OUT=1
ONE 0 11 00 0
IN=1 1 11 11 0
ONE
OUT=0
IN=1
ENGIN112 L25: State Reduction and Assignment October 31, 2003

5. Sol
utio PS
n A, 00 01 11 10
circIN PS NS OUT
0 0 0 0 -
ZERO 0
uit 00 00 0 IN NS 1 = IN PS0
1 0 1 1 -
deri 1 00 01 0
CHANGE 0
vati 01 00 1 PS
on 1 01 11 1 00 01 11 10
ONE 0 11 00 0 0 0 0 0 - NS 0 = IN
IN
1 11 11 0 1 1 1 1 -
PS
NS1
FF PS1 00 01 11 10
IN
0 0 1 0 - OUT= PS 1 PS 0
OUT
1 0 1 0 -
NS0
IN FF PS0
ENGIN112 L25: State Reduction and Assignment October 31, 2003

6. Sol
utio
nOutput depends non only on PS but also on input, IN
B
IN=0
IN PS NS OUT
OUT=0 Let ZERO=0,
ONE=1 0 0 0 0
ZERO 0 1 0 0
1 0 1 1
1 1 1 0
IN=1
OUT=1 IN=0 NS = IN, OUT = IN PS’
OUT=0
ONE NS PS
IN FF
IN=1
OUT=0 OUT
What’s the intuition about this solution?
ENGIN112 L25: State Reduction and Assignment October 31, 2003

7. Edg
e
det
ect
CLK
or
timi
INng
dia
gra
OUT (solution A)
ms
OUT (solution B)
° Solution A: output follows the clock
° Solution B: output changes with input rising edge and is
asynchronous wrt the clock.
ENGIN112 L25: State Reduction and Assignment October 31, 2003

8. FS
M
Co Solution B
Solution A
mp Mealy Machine
aris Moore Machine ° output function of both PS &
° onoutput function only of PS input
° maybe more state ° maybe fewer states
° synchronous outputs ° asynchronous outputs
• no glitching • if input glitches, so does output
• one cycle “delay” • output immediately available
• full cycle of stable output • output may not be stable long
enough to be useful:
CLK
IN CLK
OUT OUT CL
ENGIN112 L25: State Reduction and Assignment October 31, 2003

9. FS
M
Rec
Moore Machine Mealy Machine
ap
input value input value/output values
STATE
[output values] STATE
Both machine types allow one-hot implementations.
ENGIN112 L25: State Reduction and Assignment October 31, 2003

10. FS
M
°Opti Reduction:
State ° Example: Odd parity checker
miz
Motivation:
atio
n lower cost 0
- fewer flip-flops in one-
hot implementations S0
- possibly fewer flip- [0]
0 0
flops in encoded 1 Moore machine
implementations
S1 S0
- more don’t cares in [0]
[1]
next state logic
- fewer gates in next 1 1 1 1
state logic S2 S1
Simpler to design with [0] [1]
extra states then reduce
later.
0 0
ENGIN112 L25: State Reduction and Assignment October 31, 2003

11. Stat
e
° Red Matching” is based on the state-transition table:
“Row
• ucti states
If two
on • have the same output and both transition to the same next state
• or both transition to each other
• or both self-loop
• then they are equivalent.
• Combine the equivalent states into a new renamed state.
• Repeat until no more states are combined
State Transition Table
NS output
PS x=0 x=1
S0 S0 S1 0
S1 S1 S2 1
S2 S2 S1 0
ENGIN112 L25: State Reduction and Assignment October 31, 2003

12. FS
M
°Opti
Merge state S2 into S0 ° Example: Odd parity
miz checker.
°atio
Eliminate S2
n
° New state machine
shows same I/O 0
behavior S0
[0]
0 0
State Transition Table 1
S1 S0
NS output
[1] [0]
PS x=0 x=1
S0 S0 S1 0 1 1 1 1
S1 S1 S0 1 S2 S1
[0] [1]
0 0
ENGIN112 L25: State Reduction and Assignment October 31, 2003

13. Ro
w
Mat State Transition Table
chi NS output
ng PS x=0 x=1 x=0 x=1
Exa a a b 0 0
mpl b c d 0 0
e c a d 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1
ENGIN112 L25: State Reduction and Assignment October 31, 2003

14. Ro
w
Mat NS output
chi
PS x=0 x=1 x=0 x=1
ng a b Reduced State Transition Diagram
a 0 0
Exa c d
b 0 0
mpl a d
c 0 0
e e f
d 0 1
e a f 0 1
f e f 0 1
NS output
PS x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1
ENGIN112 L25: State Reduction and Assignment October 31, 2003

15. Stat
e
°Red “row matching” method is not guaranteed to
The
ucti
result in the optimal solution in all cases, because
on only looks at pairs of states.
it
° For example: 0/1
S0
° Another (more complicated)
1/0 method guarantees the optimal
solution:
0/1 S1
° “Implication table” method:
1/0 1/0
See Mano, chapter 9.
S2 (not responsible for chapter 9
material)
0/1
ENGIN112 L25: State Reduction and Assignment October 31, 2003

16. Encoding State Variables
° Option 1: Binary values
° 000, 001, 010, 011, 100 …
° Option 2: Gray code
° 000, 001, 011, 010, 110 …
° Option 3: One hot encoding
° One bit for every state
° Only one bit is a one at a given time
° For a 5-state machine
° 00001, 00010, 00100, 01000, 10000
ENGIN112 L25: State Reduction and Assignment October 31, 2003

17. State Transition Diagram Solution
B
IN=0
IN PS NS OUT
ZERO IN=0 ZERO
0 01 01 0
OUT=0 1 01 10 0
IN=1 IN=0 CHANGE
0 10 01 1
1 10 00 1
CHANGE ONE 0 00 01 0
OUT=1
1 00 00 0
IN=1
ONE ° How does this change the combinational logic?
OUT=0
IN=1
ENGIN112 L25: State Reduction and Assignment October 31, 2003

18. Summary
° Important to create smallest possible FSMs
° This course: use visual inspection method
° Often possible to reduce logic and flip flops
° State encoding is important
• One-hot coding is popular for flip flop intensive designs.
ENGIN112 L25: State Reduction and Assignment October 31, 2003