ENGIN 112                  Intro to Electrical and Computer                             Engineering                       ...
Overvie       w  ° Latches respond to trigger levels on control inputs          • Example: If G = 1, input reflected at ou...
D Latch                                            S                   D                             S’                   ...
Clocking Event° What if the output only changed on a C transition?            Positive edge triggered                     ...
Master-Slave D Flip            Flop ° Consider two latches combined together ° Only one C value active at a time ° Output ...
D    Flip ° Stores a value on the positive edge of C    -    Flo ° Input changes at other times have no effect on output  ...
Clocked D Flip-Flop ° Stores a value on the positive edge of C ° Input changes at other times have no effect on outputENGI...
Positive and Negative Edge D Flip-   Flop ° D flops can be triggered on positive or negative edge ° Bubble before Clock (C...
Positive Edge-Triggered J-K Flip-Flop  °Created from D flop                              J K CLK Q Q’  °J sets            ...
Clocked J-K Flip       Flop ° Two data inputs, J and K ° J -> set, K -> reset, if J=K=1 then toggle output                ...
Positive Edge-Triggered T Flip-Flop  °Created from D flop                                                T C            Q ...
Asynchronous Inputs• J, K are synchronous inputs      o Effects on the output are synchronized with the CLK input.• Asynch...
Asynchronous InputsENGIN112 L20: Sequential Circuits: Flip flops   October 20, 2003
Asynchronous Inputs                                                • Note reset signal (R) for                            ...
Parallel Data Transfer ° Flip flops store outputs from combinational logic ° Multiple flops can store a collection of data...
Summary ° Flip flops are powerful storage elements         • They can be constructed from gates and latches! ° D flip flop...
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Lect20 Engin112

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  • Give qualifications of instructors: DAP teaching computer architecture at Berkeley since 1977 Co-athor of textbook used in class Best known for being one of pioneers of RISC currently author of article on future of microprocessors in SciAm Sept 1995 RY took 152 as student, TAed 152,instructor in 152 undergrad and grad work at Berkeley joined NextGen to design fact 80x86 microprocessors one of architects of UltraSPARC fastest SPARC mper shipping this Fall
  • credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.
  • credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.
  • Lect20 Engin112

    1. 1. ENGIN 112 Intro to Electrical and Computer Engineering Lecture 20 Sequential Circuits: Flip flopsENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003
    2. 2. Overvie w ° Latches respond to trigger levels on control inputs • Example: If G = 1, input reflected at output ° Difficult to precisely time when to store data with latches ° Flip flips store data on a rising or falling trigger edge. • Example: control input transitions from 0 -> 1, data input appears at output • Data remains stable in the flip flop until until next rising edge. ° Different types of flip flops serve different functions ° Flip flops can be defined with characteristic functions.ENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003
    3. 3. D Latch S D S’ Q C Q’ R R’ S R C Q Q’ D C Q Q’ 0 0 1 Q0 Q0’ Store 0 1 0 1 1 1 1 0 0 1 1 0 1 Reset X 0 Q0 Q0’ 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q0 Q0’ Store ° When C is high, D passes from input to output (Q)ENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003
    4. 4. Clocking Event° What if the output only changed on a C transition? Positive edge triggered D C Q Q’ D Q 0 0 1 C Q’ 1 1 0 X 0 Q0 Q0’ Hi-Lo edge Lo-Hi edgeENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003
    5. 5. Master-Slave D Flip Flop ° Consider two latches combined together ° Only one C value active at a time ° Output changes on falling edge of the clockENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003
    6. 6. D Flip ° Stores a value on the positive edge of C - Flo ° Input changes at other times have no effect on output p Positive edge triggered D C Q Q’ D Q 0 0 1 C Q’ 1 1 0 X 0 Q0 Q0’ D gets latched to Q on the rising edge of the clock.ENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003
    7. 7. Clocked D Flip-Flop ° Stores a value on the positive edge of C ° Input changes at other times have no effect on outputENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003
    8. 8. Positive and Negative Edge D Flip- Flop ° D flops can be triggered on positive or negative edge ° Bubble before Clock (C) input indicates negative edge trigger Lo-Hi edge Hi-Lo edgeENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003
    9. 9. Positive Edge-Triggered J-K Flip-Flop °Created from D flop J K CLK Q Q’ °J sets 0 0 ↑ Q0 Q0’ 0 1 ↑ 0 1 °K resets 1 0 ↑ 1 0 °J=K=1 -> invert output 1 1 ↑ TOGGLEENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003
    10. 10. Clocked J-K Flip Flop ° Two data inputs, J and K ° J -> set, K -> reset, if J=K=1 then toggle output Characteristic TableENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003
    11. 11. Positive Edge-Triggered T Flip-Flop °Created from D flop T C Q Q’ °T=0 -> keep current 0 ↑ Q0 Q0’ °K resets TOGGLE 1 ↑ °T=1 -> invert currentENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003
    12. 12. Asynchronous Inputs• J, K are synchronous inputs o Effects on the output are synchronized with the CLK input.• Asynchronous inputs operate independently of the synchronousinputs and clock o Set the FF to 1/0 states at any time. ENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003
    13. 13. Asynchronous InputsENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003
    14. 14. Asynchronous Inputs • Note reset signal (R) for D flip flop • If R = 0, the output Q is cleared •This event can occur at any time, regardless of the value of the CLKENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003
    15. 15. Parallel Data Transfer ° Flip flops store outputs from combinational logic ° Multiple flops can store a collection of dataENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003
    16. 16. Summary ° Flip flops are powerful storage elements • They can be constructed from gates and latches! ° D flip flop is simplest and most widely used ° Asynchronous inputs allow for clearing and presetting the flip flop output ° Multiple flops allow for data storage • The basis of computer memory! ° Combine storage and logic to make a computation circuit ° Next time: Analyzing sequential circuits.ENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003
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