Published on

nota CMOS

Published in: Education
1 Like
  • Be the first to comment

No Downloads
Total Views
On Slideshare
From Embeds
Number of Embeds
Embeds 0
No embeds

No notes for slide


  1. 1. 7/4/2013 1 EE603 – CMOS IC DESIGN TOPIC 1 Introduction to Integrated Circuit Faizah Bt. AmirFaizah Bt. AmirFaizah Bt. AmirFaizah Bt. Amir Introduction to Integrated Circuit • explain the historical perspective of integrated circuit • explain the issues in digital IC design • explain the quality design metrics of a digital design Lesson Learning Outcome : At the end of this session, you should be able to:
  2. 2. 7/4/2013 2 What is an Integrated Circuit ? A complex set of tiny components and their interconnections that are imprinted onto a tiny slice of semiconductor material (e.g silicon). Integrated circuits are usually called ICs or chips. Introduction to Integrated Circuit Introduction to Integrated Circuit • Different Types of IC Packages
  3. 3. 7/4/2013 3 Introduction to Integrated Circuit – Evolution of logic complexity in IC Year Technology No. of transistors Example 1947-1950 Transistor 1 - 1951 -1960 Discrete Component 1 FET, Diode 1961 -1966 SSI - Small scale integration 10 Logic Gates, Flip-flop 1967-1971 MSI - Medium scale integration 100 – 1000 Counter, Multiplexer 1972-1980 LSI - Large scale integration 1000 – 20,000 RAM, Microprocessor 1981 -1990 VLSI - Very large scale integration 20,000 – 1,000,000 16 bits and 32 bits Microprocessor 1990-2000 ULSI - Ultra large scale integration 1,000,000 – 10,000,000 Graphic microprocessor 2000 - nowadays GSI - Giga scale integration > 10,000,000 - Transistor Revolution • First Transistor –Bardeen Labs) in 1947 • First Bipolar transistor –Shockley in 1949 • First monolithic IC –Jack Kilby in 1958 • First commercial IC logic gates –Fairchild 1960
  4. 4. 7/4/2013 4 Transistor Revolution • Dr. John Bardeen, Dr. Walter Brattain, and Dr. William Shockley discovered the transistor effect and developed the first device in December, 1947. They were members of the technical staff at Bell Laboratories in Murray Hill, NJ. They were awarded the Nobel Prize in physics in 1956. John Bardeen, William Shockley and Walter Brattain at Bell Labs, 1948. 1947 First BJT Bardeen, Shockley, Brattain (Bell Labs) Transistor Revolution • William Shockley developed the theory for the junction transistor in 1948 at Bell Labs. • He left for Caltech in 1953 and founded Shockley Semiconductor in 1956 and starting Silicon Valley in Mountain View, California.
  5. 5. 7/4/2013 5 Transistor Revolution • Jack Kilby completed his first integrated circuit on September 12, 1958 which was actually constructed on germanium rather than silicon, as he could not find a suitable piece of silicon at the time. • The integrated circuit was fully functional, and Texas Instrument officially announced it in January 1959. 1958: The Integrated Circuit was invented by Jack Kilby Transistor Revolution In August 1959 Fairchild Semiconductor begin the development of an integrated circuit. Fairchild presented advanced information at engineering conferences and provided prototype samples to customers in 1960. 1962 Fairchild IC
  6. 6. 7/4/2013 6 MOSFET TECHNOLOGY • MOSFET transistor was first proposed and patented by Lilienfeld (Canada) in 1925 and Heil (England) in 1935. • The devices was not successfully demonstrated for several years but only became important in mid and late 1960s. • Initially semiconductor research had focussed in developing the bipolar transistor, because they have problems in fabricating MOSFETs, particularly with the insulating oxide layers. • Now the technology is one of the most widely used semiconductor techniques and become one of the principle elements in integrated circuit technology today. • Their performance has enabled power consumptions in ICs to be reduced and enabled the portable gadgets to become a reality. • As a result of this the MOSFET is the most widely used form of transistor in existence today. Moore’s Law • In 1965, Gordon Moore (Co-Founder of Intel) predicted that the number of transistors per chip will grow exponentially with time. • He predicted that : the transistor density will double every 18-24 months the chip performance will double every 18-24 months
  7. 7. 7/4/2013 7 Moore’s Law 1965: Cost vs time Moore’s law 1960-1975 Moore’s Law
  8. 8. 7/4/2013 8 Evolution in DRAM Chip Capacity Die Size Growth
  9. 9. 7/4/2013 9 Power Density Issues in Digital IC Design Functionality Cost Reliability, Robustness Performance Time to market Design Complexity High Levels of Abstraction
  10. 10. 7/4/2013 10 QUALITY DESIGN METRICS IN DIGITAL DESIGN • Functionality • Cost – NRE (fixed) costs - design effort – RE (variable) costs - cost of parts, assembly, test • Reliability, robustness – Noise margins – Noise immunity • Performance – Speed (delay) – Power consumption; energy • NRE (non-recurring engineering) costs – Fixed cost to produce the design • design effort • design verification effort • mask generation – Influenced by the design complexity and designer productivity – More pronounced for small volume products • Recurring costs – proportional to product volume – Silicon processing • also proportional to chip area – Assembly (packaging) – Test
  11. 11. 7/4/2013 11 • Prime requirement – IC performs the function it is designed for • Normal behaviour deviates due to – variations in the manufacturing process (dimensions and device parameters vary between runs and even on a single wafer or die) – presence of disturbing on- or off-chip noise sources • Noise: Unwanted variation of voltages or currents at the logic nodes • from two wires placed side by side – inductive coupling • current change on one wire can influence signal on the neighbouring wire – capacitive coupling • voltage change on one wire can influence signal on the neighbouring wire • cross talk • from noise on the power and ground supply rails – can influence signal levels in the gate
  12. 12. 7/4/2013 12 Inverter Voltage Transfer Characteristic (VTC) in out VOH , VIH - nominal high voltage VOL, VIL - nominal low voltage VM – gate or switching threshold voltage VM can be found graphically at the intersection of the VTC curve and the line given by Vout = Vin. The gate threshold voltage presents the midpoint of the switching characteristics.IL IH • The regions of acceptable high and low voltages are delimited by VIH and VIL that represent the points on the VTC curve where the gain = -1 or dVout/dVin = -1
  13. 13. 7/4/2013 13 Noise Margins is a measure of the sensitivity of a gate to noise. Noise margins represent the levels of noise that can be sustained when gates are cascaded. For robust circuits, we want the “0” and “1” intervals to be as large as possible. Large noise margins are desirable.
  14. 14. 7/4/2013 14 • A gate with regenerative property ensure that a disturbed signal converges back to a nominal voltage level. v0 v1 v2 v3 v4 v5 v6 The signal voltage gradually converges to the nominal signal after a number of inverter stages, as indicated by the arrows. The signal does not converge to any of the nominal voltage levels but to an intermediate voltage level. Hence, the characteristic is nonregenerative.
  15. 15. 7/4/2013 15 • Noise margin expresses the ability of a circuit to overpower a noise source. – noise sources: supply noise, cross talk, interference, offset. • Noise immunity, on the other hand, expresses the ability of the system to process and transmit information correctly in the presence of noise. • Noise immunity is the ability of a circuit to reject a noise source rather than overpower it. • A gate must be unidirectional: changes in an output level should not appear at any unchanging input of the same circuit. – In real circuits full directivity is an illusion (e.g., due to capacitive coupling between inputs and outputs). • Key metrics: output impedance of the driver and input impedance of the receiver. – ideally, the output impedance of the driver should be zero. – input impedance of the receiver should be infinity.
  16. 16. 7/4/2013 16 Fan-out – number of load gates connected to the output of the driving gate. o gates with large fan-out are slower Fan-in – the number of inputs to the gate. o gates with large fan-in are bigger and slower • The ideal gate should have: – infinite gain in the transition region – a gate threshold located in the middle of the logic swing – high and low noise margins equal to half the swing – input and output impedances of infinity and zero, respectively.
  17. 17. 7/4/2013 17 Performance • The performance of a digital circuit is expressed by the propagation delay and the power consumption of a gate. •The propagation delay, tp of a gate defines how quickly it responds to a change at its input(s). • It expresses the delay experienced by a signal when passing through a gate. • It is measured between the 50% transition points of the input and output waveforms.
  18. 18. 7/4/2013 18
  19. 19. 7/4/2013 19 • Power consumption: how much energy is consumed per operation and how much heat the circuit dissipates. – supply line sizing (determined by peak power) Ppeak = Vdd ipeak – battery lifetime (determined by average power dissipation) p(t) = v(t)i(t) = Vddi(t) Pavg= 1/T ∫ p(t) dt = Vdd/T ∫ idd(t) dt – packaging and cooling requirements • Two important components: static and dynamic • Propagation delay and the power consumption of a gate are related. • Propagation delay is (mostly) determined by the speed at which a given amount of energy can be stored on the gate capacitors. – the faster the energy transfer (higher power dissipation) the faster the gate.
  20. 20. 7/4/2013 20 • Digital integrated circuits have come a long way and still have quite some potential left for the coming decades. • A lot of issues and challenges in digital integrated circuit design and the potential solutions are needed in order to survive in the industry. • Design metrics is used to evaluate the quality of a design: cost, functionality, robustness, performance and energy/power dissipation.