Ijarcet vol-2-issue-7-2328-2332

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Ijarcet vol-2-issue-7-2328-2332

  1. 1. ISSN: 2278 – 1323 International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Volume 2, Issue 7, July 2013 2328 www.ijarcet.org Performance Investigation of Two-Stage Operational Amplifier C.K.Kalawade, S.A.Shaikh Abstract: As CMOS technology scaling down transistor channel lengths to satisfy the thrust of low power consumption in modern electronics system . There is need to investigate the performance of the upcoming scaled channel length CMOS devices. At lower technology nodes mixed signal issues increases significantly this limits the performance of devices. In this paper two stage op-amp at different technology nodes of CMOS is designed and its performance has been investigated .CMOS technology nodes 16nm , 22nm ,32nm are used for evaluating the performance of two stage op-amp. Effect of temperature variations has been observed on two stage op-amp at 32nm CMOS technology. Index Terms: Two stage op-amp , differential amplifier, common mode gain , slew rate I INTRODUCTION As technology is scaling down the transistor lengths to reduce power consumption , the variability issues increases. Also static power dissipation and subthreshold leakage current becomes dominant at lower technology[1] .Sacaling of CMOS in deca nanometer results in degradation of gmb/gm ratio to from 0.38 to 0.12 between representative 0.25 lm and 65 nm technologies[5]. A common-mode adapter with a folded cascaded op-amp is used to reduce the common-mode voltage , circuitry and save power[6].In this paper the performance of CMOS devices at different technology for analog and mixed signal processing has been investigated .Op-amp ideally have infinite differential gain, infinite bandwidth ,infinite CMRR ,infinite slew rate in practical op-amp approaches to these values [3].Two stage op-amp is designed for different technology nodes of CMOS. Electrical characteristics of two stage op-amp at different technology nodes of CMOS are compared to study the technology scaling effects on the conventional CMOS .The effect of temperature variation on two stage op-amp at 32nm CMOS technology has been observed as temperature is also considered to be important factor for affecting the performance of circuit . II TWO STAGE OP-AMP Operational Amplifier is an elementary building block of the many electronics system. They are integral part of many analog and mixed signal systems. C.K.Kalawade, Electronics and Telecommunication Department , University Pune,P.D.V.V.P.C.O.E.,Ahmednagar,Maharashtra,India S.A.Shaikh , Electronics and Telecommunication Department, University Pune,P.R.E.C.Loni,Ahmednagr,Maharashtra,India Figure.1 Block diagram of Op-amp The block diagram of an op-amp is as shown in figure1 it consists of mainly four stages. The differential amplifier act as an input stage of the op-amp and sometimes provides the differential to single ended conversion normally, a most of the portion of the overall gain is provided by the differential input stage and the second stage is typically an inverter [3]. If the differential input stage does not perform the differential to single ended conversion, then it is accomplished in the second stage inverter. If the op-amp must drive a low resistance load, the second stage must be followed by a buffer stage whose objective is to lower the output resistance and maintain a large signal swing .Bias circuits are provided to establish the proper operating point for each transistor in its quiescent state[3].Ideal op-amp has infinite differential voltage gain, infinite input resistance and zero output resistance. In reality op-amp only approaches these values. .The output voltage Vout can be expressed as Vout = AV (V1 - V2) (1) Where AV is used to designate the open-loop differential- voltage gain.V1 and V2 Are the input voltages applied to the non-inverting and inverting terminals, respectively [3]. V1 V2 Vout High gain stage (Inverter) Output Buffer Bias Circuitry Compensation Circuitry Differential Amplifier
  2. 2. ISSN: 2278 – 1323 International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Volume 2, Issue 7, July 2013 2329 www.ijarcet.org Figure 2.The circuit diagram of two stage Op-amp The circuit diagram consist of M1 and M2 are acting as a differential amplifier for converting the input differential voltage to differential current. Figure.2 shows the single ended. Confugaration of two stage Op-amp here M1 is connected at ground and input signal applied to M2 .Differential current is then converted to voltage by load formed using MOSFETs M3 and M4. In the second stage voltage is converted to current by using MOSFET M6.The common current sink inverter by using MOSFET M7 [3]. Formulae’s for designing op-amp .Assuming that gm1= gm2= gmI, gm6= gmII and gds2 + gds4 =GI , gds6 + gds7 =GII 1) Slew rate SR =I5 /Cc (2) 2) First stage gain Av1=-gm1/(gds2+gds4) (3) 3) Second stage gain Av2= -gm6/( gds6+gds7) (4) 4) Gain bandwidth GB=gm1/Cc (5) MOSFETS (W/L) M1 2 M2 2 M3 10 M4 10 M5 3 M6 60 M7 10 Table1.Aspect Ratios . Figure 3. Variation in Dynamic power for different CMOS technologies III SIMULATION AND RESULTS Synopsys Hspice 2005.09 simulator is used for circuit simulation. Performance of the two stage op-amps electrical characteristics differential gain, bandwidth , slew rate, common mode rejection ratio , dynamic power dissipation for different technology nodes of CMOS are shown in graphs from figure 3 to figure 7 .The supply voltage and other circuit parameters except technology are kept constant for comparison .The temperature variation effects at 32 nm CMOS technology are shown in figure 8 to figure 15 are Figure 4. Variation in Common mode rejection ratio (CMRR) for the different CMOS technologies C L Cc M4 Vdd M7 M5 M3 M2M1 M6 Vss Vin Vout Vbias
  3. 3. ISSN: 2278 – 1323 International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Volume 2, Issue 7, July 2013 2330 www.ijarcet.org Figure 5 . Variation in Bandwidth for the different CMOS technologies Figure6.Variation in slew rate for the different CMOS technologies Figure7.Variation in differential gain for the different CMOS technologies Figure 8.Effect of temperature variation on differential gain at 32nm technology Figure 9.Effect of temperature variation on common mode rejection ratio(CMRR) Figure10. Figure 7.Effect of temperature variation on dynamic power
  4. 4. ISSN: 2278 – 1323 International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Volume 2, Issue 7, July 2013 2331 www.ijarcet.org Figure 11.Effect of temperature variation on slew rate Figure 12..Effect of temperature variation on Bandwidth Figure 12..Effect of temperature variation on input resistance Figure 13..Effect of temperature variation on output resistance Figure 14.Effect of temperature variation on input noise Figure 15.Effect of temperature variation on output noise
  5. 5. ISSN: 2278 – 1323 International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Volume 2, Issue 7, July 2013 2332 www.ijarcet.org IV CONCLUSION Performance of the two stage amplifier’s electrical characteristics at different technology node has been analyzed. It shows that as technology is scaled down the transistor channel lengths dynamic power ,differential gain ,CMRR, slew rate reduces and bandwidth increases. From the result it can be observed that performance decreases as technology scales down but power dynamic dissipation is also reduces. Temperature variation for 32nmtechnology CMOS two stage amplifier has been analyzed. It shows that with temperature rise dynamic power ,differential gain ,CMRR, slew rate, bandwidth ,input resistance and output noise reduces and input noise and output resistance increases. REFERENCES . [1] J. Mahattanakul “Design Procedure for Two-Stage CMOS Operational Apmlifier Employing Current Buffer” IEEE Trans. on Circuits and System —II,VOL. 52, NO. 11, November 2005 [2] M.Geetha Priya, Dr.K.Baskaran, D.Krishnaveni ,“ Leakage Power Reduction Techniques in Deep Submicron Technologies For VLSI Applications” International Conference on Communication Technology and system design 2011, doi10.1016/j.proeng.2012.01.976 [3] P.E. Allen and D.R.Holberg,,L CMOS Analog Circuit Design New York :oxford Univ. Press 2002 [4] J. Mahattanakul ,Jamorn chutichatuporn “Design Procedure for Two-Stage L CMOS Operational Amplifiers Emp with Flexible Noise-Power Balancing scheme” IEEE Transactions on Circuits and system—I,VOL. 52, NO. 8, August 2005 [5] James E. Moon, P.R. Mukund, Christopher Urban “Scaling the bulk-driven MOSFET into deca-nanometer bulk CMOS processes” Microelectronics Reliability 51 (2011) 727–732, doi:10.1016/j.microrel.2010.11.016 [6] David Baez-Villegas, Jose Silva-Martinez “Quasi Rail-to-Rail Very Low- Voltage OPAMP With a Single pMOS Input Differential Pair” IEEE transactions on circuits and systems—ii: express briefs, vol. 53, no. 11, november 2006 . First Author: C.K.Kalawade, B.E. from Pune university in 2007, working as lecturer in P.D.V.V.P.C.O.E. Ahmednagar , Pune university Maharashtra,India. Second Author: S.A.Shaikh, B.E. from P.R.E.C. Loni Pune university in 1990,M.E from J.N.E.C.Aurangabad in 2001,Has 21years of teching experience working as Assistant Prof. in P.R.E.C. Loni ,Pune university Maharashtra, India.

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