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Know enterprise storage performance Hands-on Lab

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HP Technology Services’ Master Technologists Chris and Greg Tinker will demonstrate the advanced debugging and technical tactics HP Enterprise Technical Services engineers use to triage back-office IT …

HP Technology Services’ Master Technologists Chris and Greg Tinker will demonstrate the advanced debugging and technical tactics HP Enterprise Technical Services engineers use to triage back-office IT events that could critically impact the business. This is a deep technical session with engineers demonstrating the methodologies they employ to address enterprise storage issues.

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  • 1. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. Knowenterprisestorage performance Greg Tinker – HP Master Technologist Chris Tinker – HP Master Technologist June 11, 2013
  • 2. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.3 My background Title HP Master Technologist IT industry experience • Published Author • Patents pending • Social media/white papers Professional information • HP MVP • Social media ambassador Years at HP 14 Current responsibilities • Lead technologist for HP’s Global Solution Support Engineering (GSSE) team Name: Chris Tinker E-mail: chris.tinker@hp.com
  • 3. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.4 My background Title HP Master Technologist IT industry experience • Published Author • Patents pending • Social media/white papers Professional information • HP MVP • Social media ambassador Years at HP 14 Current responsibilities • Lead technologist for HP’s Global Solution Support Engineering (GSSE) team Name: Greg Tinker E-mail: greg.tinker@hp.com
  • 4. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. Storagearchitecture
  • 5. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.6 Active/Active – Symmetric logical unit access Storage architecture Active/Active or ALUA IOCTL() are weighted equally on all external host ports. ALUA – Asymmetric logical unit acce IOCTL() are NOT weighted equally on all external host ports. A controller is assigned a LDEV – All associated LUNpaths, Pdev’s, Cache slot control, etc…
  • 6. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.7 Monolithic or Modular Storage Architecture What defines Monolithic Storage vs. Modular Storage? Sufficient to say – Global Cache access… Monolithic • Having many controllers (FA/host ports) that share access to large global cache • Usually NUMA based with SMP (P9500, V-MAX) • EVA, and other older arrays are not SMP based arch: Processors use high speed interconnect, not a common memory bus Modular • Usually 2 or more nodes (controllers) with Non-Uniform Memory Access (NUMA) V-Max, 3PAR and similar are multiple node (controllers) using (NUMA) • Using multiple RAID (Redundant Array of Inexpensive Disk) – Highly specialized JBOD’s
  • 7. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. Physicaldisk&virtualization
  • 8. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.9 Physical disk Physical / virtualization Overview (Physical Disk) 15K RPM drive has the same performance in all array models, regardless of vendor. Note: 15,000 RPM = 250 Revolutions per Second – or 4ms/revolution… (typical ½ rev is all that is needed so the response time is always documented ½ of full revolution. Track Sector Data Preamble Cylinder - same sector location on each platter
  • 9. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.10 Virtualization Physical / virtualization Fault tolerance requires parity stripping across Multiple canisters (XP) / Drive Cage (3PAR) / Shelves (EVA) / EMC (term???) P10000 (3PAR) has some huge advantages by doing software level raid • HA Cage – meaning stripping across chunklet (1GB size) that reside on PDEV– 1 disk per cage. • HA Magazine – Having only one Drive Cage, and stripping horizontal across single drive in each Magazine within the drive cage. Physical disk Physical disk Physical disk Physical disk Physical disk Physical disk Physical disk Physical disk Physical disk Physical disk Physical disk Physical disk Physical disk Physical disk Physical disk Physical disk
  • 10. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.11 Virtualization Physical / virtualization Physical space (partition) from 4 or more drives from difference enclosures combine to build a Logical Device (Ldev). PDev Pdev Pdev Pdev PDev Pdev Pdev Pdev PDev Pdev Pdev Pdev PDev Pdev Pdev Pdev Stripe Size or Chunklet (depends on array) 3PAR – RaidSet ~all other array – Logical device Combine: Called Hitachi LUSE (Concatenated) EMC Component Luns – MetaVolume (concatenated or stripped)
  • 11. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. Controllerarchitecture
  • 12. EVA Arch Controller architecture PowerPC • EVA 6300/6500 AMCC Purchased from IBM 2004, IBM continues development – HP Uses 533 MHz & 667 MHz (Max in IBM dev is 800 MHz) – Intergraded Raid Engine used for Parity computation and Integrated Memory controller for Data Movement. • EVA Gen 2 (8400) Uses Motorola 7447 – worked with IBM to develop, and Freescale Semiconductor owns it today – PPC Run rate is around 960 MHz (~1 GHz) (on PCI-133 Mhz Bus - Pathway between host/disk and CPU) – Sprite ASIC used for Data Movement and Parity Computation. – Dedicated Policy Memory (2 or 3 GB SDRAM) Asymmetric Logical Unit Access (ALUA) Source: Mark Walsh Michael Kielhauser provides CPU details for EVA Sec Gen Full History http://en.wikipedia.org/wiki/PowerPC_G4 PPC CACHE DDR2 Sprite FPGA (ASIC) Discovery II Bridge Memory Controller (SDRAM – Policy mem) Down Stream CLPD, FPGA, ETC… (Location of flash 32 MB boot code) SFP SFP SFP SFP Tachyon Tachyon Tachyon Tachyon Tachyon Tachyon SFP SFP SFP SFP SFP SFP SFP SFP HDD HDD
  • 13. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.14 3PAR Arch Controller architecture Intel E5440 Quad Core Intel Harpertown 2.83 GHz w/ 12MB L2 Cache Used for Program Product/management, etc. Harrier ASIC Motorola (now owned by Google) made the first Harrier ASIC late 90’s early 2000 – if my memory is right (GT)… High level flow for all PCIe Gen1 or 2 using the PEX Switch along with ASIC & CPU Source: http://en.wikipedia.org/wiki/Intel_Core_(microarchitecture) www.plxtech.com/download/file/587 Intel E5440 Quad Core 2.83 GHz Intel E5440 Quad Core 2.83 GHz 3PAR Gen4 Harrier ASIC 3PAR Gen4 Harrier ASIC Control Cache Data Cache (MCH) Memory Controller Intel 5000P PCIe Switch PEX 8648 PCIe Switch PEX 8648 PCIe Switch PEX 8648 Data Cache
  • 14. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.15 Controller architecture Source: http://en.wikipedia.org/wiki/Intel_Core_(microarchitecture) www.plxtech.com/download/file/587 Harrier ASIC PEX (Switch) PCIe Emulex 8 Gb FC 4 Port 8 Gb SFP LSI 6 Gb SAS 2 * (4 * 6Gb) SFP SFP SFP SFP SFP SFP SFP SFP 8 Gb SFP HDD8 Gb SFP 8 Gb SFP 3PAR Arch – High-level block diagram Harrier ASIC Used for Data Movement and Parity Computation Determines rate at which host data can be flushed from memory to disk Determines rate at which host data can be transferred between nodes. Emulex IOC (embedded I/O controller)
  • 15. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.16 Controller architecture XP24000 • With the XP24000, up to 128 MPs were located directly on the CHAs and DKAs • Each MP has specific task sets and limited performance. • All MPs competed for Share Memory (MP) access and locks • NEC MIPS 800 MHz for CHA, 400 MHz for DKA • MIPS – MicroProcessor without Interlocked Pipleline Stages – Reduced Instruction set Computer (RISC) instruction set Architecture (ISA) developed by MIPS Technologies founded in 1981, bought by SGI in 1992 P9500 With the P9500, the much faster multi-core MPs reside on Micro Processor Blades (MPB) and are independent of specific responsibilities All MPs share responsibility for the operation of the whole array. The MP Blades do have Local Memory (LM) to store Shared Memory content and reducing SM traffic 2.33 GHz Zeon L5410 Quad Core CPU (1 Per MPB) - HarperTown Total of 32 Cores W/ 4 GB of local mem per MPB & 1 TB of cache L1 Cache 256K; L2 Cache 12MB ; L3 off-die (4 Gb shared on MPB) DKA CHA CHA DKA MP MP CACHE Shared Memory MP MP MP MPMP MP MPB MP MP MP MP CACHE ESWCSW SM LM Source: Intel L5410 http://ark.intel.com/products/33090 http://en.wikipedia.org/wiki/Intel_Core_(microarchitecture) HDD HDD P9000 Arch – XP24K vs. P9500
  • 16. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. ProgramProducts
  • 17. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.18 Thin provisioning Program products Do not mix AG Raid and Spindle types within a ThP. Performance will be that of weakest link Parity Group (4 or 8 disk) HDD or SSD LDEV – When allocating LDEV from a AG into a ThP – make sure the LDEV count = HDD/SSD and that the size is equal to all LDEVS in the ThP… ThP #1 V V O L
  • 18. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.19 Traditional vs. ThP Program Products 2TB 3.5TB 1.8TB 3TB 1.9TB 2.1TB 14.3TB logically provisioned capacity (V-Volumes) 5TB ThP pool 3.1TB used/written 1.9TB free/unused HP ThP OS visible 14.3TB (Projected requirements) Server view 14.3TB physically provisioned capacity 3.1TB of data actually written 11.2TB stranded Physical capacity required 14.3TB net Array groups/Disk drives ThP Pool Net physical pool capacity 5TB Array presentation 0.6TB 0.4TB0.5TB0.7TB0.5TB 0.4TB 2TB 3.5TB1.8TB 3TB 1.9TB 2.1TB No pool Traditional OS visible 14.3TB (Projected requirements)
  • 19. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.20 Program Products • A Snapshot is a Victual Copy of a base Volume • Snapshots can include: • Fully provisioned VV (thick) • Thin-Provisions VV • Physical copies • Snapshot of a snapshot (another virtual copy snapshot) • All the above use Copy-On-Write (COW) P10000 Virtual Copy
  • 20. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.21 StoreServe 10000 AO & P9000 Smart Tier Program Products P9000 Moves X segments at any single time Each Segment is comprised for 48MB AO moves max of 10 segments at any single time. Each Segment is comprised of 128 MAX regions Each region has a size of 128 MB. Spindle Power By Drive Type SSD or Flash Tier 1 FC 15K Tier 2 NL Tier 3 Capacity By Drive Type FC 15K Tier 2 NL Tier 3 SSD or Flash Tier 1Using Data Density reports, hot regions will be auto migrated to different tiers automatically V-Vol
  • 21. © Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. Thankyou LABtime 

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