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Mission critical computing by intel


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  • 1. Itanium inMission Critical Computing<speaker name><designation>
  • 2. Itanium Momentum New OEMs APAC Itanium-based system customer revenue as percentage of Power* and SPARC* By Quarter Source: IDC Q4 ‘11 APAC Server Tracker225%200%175%150%125% 134%100%75% 77%50%25% 0% 04Q1 04Q2 04Q3 04Q4 05Q1 05Q2 05Q3 05Q4 06Q1 06Q2 06Q3 06Q4 07Q1 07Q2 07Q3 07Q4 08Q1 08Q2 08Q3 08Q4 09Q1 09Q2 09Q3 09Q4 10Q1 10Q2 10Q3 10Q4 11Q1 11Q2 11Q3 Itanium-based customer revenue as a percentage of SPARC It’s A $4B Business…
  • 3. Mission Critical Workloads Business Transaction Intelligence and Database Processing Analytics• 1,000s – 1,000,000+ • Enable all users • Large scalable enterprise online users databases • Complex queries• Support large • No single point • Multiple data transactional of failure sources databases • Extremely fast operational • Large data• 24 x 7 operation speed warehouse Growth in Volume & Velocity of Data and Transactions
  • 4. New Mission Critical Economics HP NonStop Open VMS Buffers Common Chipset Interconnects Ingredients MemoryPowering the next generation of mission critical computing
  • 5. Beyond Mission Critical Economics...Performance Performance Energy Efficiency RAS
  • 6. Commitment to Itanium Roadmap 65nm 32n 22n m m Tukwila Poulson Kittson Poulson • New architecture for breakthrough in Itanium Performance • Greater reliability to extend mainframe class resiliency • Fully compatible with existing applications • With HP-UX… the Leading UNIX platform
  • 7. Poulson: Most Significant Itanium®Processor to Date Key Highlights • New architecture - 2x the cores, 2x instructions throughput • Total 54MB on-die memory • 3.1 Billion Transistors on 32nm process Key Capabilities • Intel® Instruction Replay Technology • Intel® Hyper-Threading Technology, enhanced with dual-domain multi- threading support • Intel® Itanium New Instructions On track for 2012!
  • 8. Poulson Advances Itanium® Architecture • Doubles the number of high capacity coresNew Itanium • Delivers maximum 12-issue execution EPIC architectureArchitecture • Supports higher speed system interconnects (QPI, SMI) • Enables accurate Core power prediction and managementImproved Power • Expands cache and logic error detection and correctionManagement and • Achieves mainframe reliability and resiliency with highRAS features levels of RAS feature integration • First reported 3.1B transistors general purpose processorInnovative • New core design for next decade of Itanium computingengineering work • Industry leading cache design and density Most Significant Itanium Processor To Date
  • 9. Improved Power Management Note: Lower is better Rati• Accurate power monitoring o and control to deliver power where it is needed• Design optimizations to reduce dynamic and leakage power +30% +70% +60% Enhanced DIMM clock gating Better* Better*• Better* to reduce system power consumption Idle Activity TDP Activity Reduced overall socket power Leakage• Current Core Power Scaling consumption Note: Poulson compared to Tukwila when scaled to equivalent process technology Power savings beyond technology scaling
  • 10. Poulson RAS Advances Increase System and Application Resiliency Error Improved Instruction End to End Prevention and Firmware Error Replay Error Detection Correction Handling Technology• Expanded soft • Enhanced Cache • Expanded • Expanded error error resilient error coverage coverage of detection captures flops and logic potential error more errors • Residual error structures usage events for • Errant instructions protection for• Hardware/Softw floating-point automatic are then re- are mechanisms operations recovery executed from enabling • Improved logging Instruction buffer correctable and configurations to auto recover parity errors for higher from severe availability and errors serviceability Increases Improves Minimizes Improves Process Execution Service System Resiliency Integrity Interruption Resiliency Enhanced error prevention, detection and correction
  • 11. Greater Parallelism with Intel® Hyper-Threading Technology Improvements Front-End Back-End Instruction Instruction Buffer Buffer Dual-Domain Multithreading support enhances performance • Minimizes thread switching costs of traditional Itanium MT implementation • Maximizes efficiency of concurrent threads to complement 12-issue instruction execution Unique EPIC architecture implementation to increase overall throughput11
  • 12. Itanium® Processor New Instructions Mid- Branch Floating Point Mid- Expanded Data Level Predict Execution Level Integer Operations Inst. Access Hints Cache BR Integer Floating Data • mpy4 • mov dahr CTL Register Pt RF Cache • mpyshl4 1st Integer Execution • clz Instruction level Cache Queues 1st level Cache 1st level Cache Buffers Thread Control Pipe Line Interface Expanded Software Prefetch Buffers Logic • hint@priority Control • ifetch.count Individual Poulson Core • Poulson continues to optimize for legacy Itanium code without recompilation • New instructions simplify common tasks and branch operations to help take future Itanium performance to the next level Poulson Architecture & The New Instructions – Foundation For Future Itanium12
  • 13. Delivering Mission Critical Computing• Improve economic • Modernize mission- efficiency critical solutions• Lower operational costs infrastructure• Highly reliable, scalable • Innovate to keep up performing systems with market dynamics Transactions at your fingertips Performance Real-time Business Analytics Data to support customers
  • 14. Summary HP & Intel have a history of transforming IT Strong roadmaps for Itanium & XeonHP and Intel committed to Mission Critical computing
  • 15. Announced at IDF Beijing, 2011 Two New Itanium OEMs…
  • 16. Family of Mission Critical ProcessorsItanium 9300 Series Xeon E7 Series Architected for Architected for Mission Critical UNIX scalable Windows with mainframe and Linux resiliency and performance with scalability advanced reliability • Hardened Operating • OEM System Capability System • OEM Service & Support • Application Availability Two server platforms to meet a wide range of mission critical requirements
  • 17. Intel® Xeon® Processor E7-8800/4800/2800 Product Families More Performance More Expandable• 10 cores / 20 • Supports 32GB DDR3 DIMMs threads (2TB per 4-socket system)1• 30MB of last level cacheMore Security & RAS More EfficientSECURITY • Lower partial active &• Intel® Advanced Encryption idle power via Intel Standard-New Instructions Intelligent Power Technology2 RELIABILITY, AVAILABILITY, SERVICEABILITY • Support for Low Voltage- DIMMs3• Enhanced DRAM Double Device Data Correction Accelerating Mission Critical Transformation All dates, product features and plans are subject to change without notice.
  • 18. New Poulson Core Architecture Mid- Branch Floating Point Key Architectural Advances Mid-Level Predict Execution Level • New Data and Instruction Pipelines Inst.Cache BR CTL Integer Register File Floating Pt RF Data Cache • New Floating Point Pipeline 1st • New Instruction Buffer level • Double max execution width Instruction Cache Integer Execution Queues 1st level (6 to12) Cache 1st level Cache Derived Benefits Buffers Pipe Line Interface Logic Buffers Control • Increased instruction throughput • Improved performance/watt Individual Poulson Core • Improved RAS coverage • Process optimized core layoutEnables leap in performance, power reduction and reliability
  • 19. Poulson Delivers Investment Protection Poulson-basedItanium 9300 series- Platform • Pin compatible support for based Platform Itanium® 9300 processor • 33% Bandwidth Poulson improvement via higher bus speeds (QPI and SMI) Common Platform Ingredients with Xeon • Poulson continues to take Intel® QuickPath and Scalable Memory advantage of common Interconnects Intel® Scalable Memory Buffer and DDR3 platform ingredients with Intel® Chipset Xeon architecture Building on the common platform vision