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# Logic Design - Chapter 7: Sequential Circuit Analysis and Design

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- CLASSIFICATION OF COUNTERS.
- RIPPLE COUNTERS (ASYNCHRONOUS COUNTERS).
- 3-bit Asynchronous Binary counter.
- COUNT SEQUENCE .
- DOWN COUNTERS.
- DESIGN OF DIVIDE – BY – N COUNTERS.
- SYNCHRONOUS COUNTERS.
- SYNCHRONOUS BINARY DOWN-COUNTER.
- UP/DOWN SYNCHRONOUS COUNTERS.

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### Logic Design - Chapter 7: Sequential Circuit Analysis and Design

1. 1. Chapter 7 Sequential Circuit Analysis and Design 1
2. 2. Characteristic ( Function ) tables of the four types of flip-flops analysis ((Q(t),Q (t+1) design S-R 2
3. 3. excitation table of SR flip – flop 3
4. 4. excitation tables of all types of flipflops 4
5. 5. BASIC DEFINITIONS OF SEQUENTIAL CIRCUITS  Sequential circuit  Any digital circuit with memory due to feedback, particularly a circuit with latches or flip-flops is a sequential circuit 5
6. 6. Moore Circuits  In a Moore circuit, the outputs are function of the present state only, i.e.; function of flip-flops outputs 6
7. 7. Mealy Circuits  In a Mealy circuit, the output is a function of both the present state and the external inputs 7
8. 8.  Counters  A counter is a sequential circuit that goes through a prespecified sequence of states upon the application of input pulses 8
9. 9. State Diagram  The sequence of states of a sequential circuit, along with the external input and the output of the circuit, can be represented graphically using a state diagram 9
10. 10. B ANALYSIS OF A SEQUENTIAL CIRCUIT get the flip-flops input functions: RA =B’ x , SA = BX’ , RB = AX’ , SB = A’ x , also get the output function(s) : Y = A’ x 10
11. 11. 11
12. 12. ANALYSIS OF A SEQUENTIAL CIRCUIT   RA =B’ x , SA = BX’ , RB = AX’ , SB = A’ x , Y=A’x Make the state table of the circuit as follows : 12
13. 13. ANALYSIS OF A SEQUENTIAL CIRCUIT  Draw the state diagram for the circuit 13
14. 14. Analysis of synchronous counters  Starting at QC QB QA = 000, what sequence does the synchronous circuit of three D flip-flops shown in figure(53) step through ? 14
15. 15. 15
16. 16. Step1: FF input (excitation) functions    DA = Q’A DB = QC ⊕ QA + QB Q’A + QB Q’C = QA Q’C + Q’A QC + Q’A QB + QB Q’C DC = QB (QA ⊕ QC ) = QA Q’C QB + Q’A QC QB 16
17. 17. STEP2: State table    DA = Q’A DB = QC ⊕ QA + QB Q’A + QB Q’C DC = QA Q’C QB + Q’A QC QB 17
18. 18. The resulting sequence of states  18
19. 19. STEP 3: State diagram Self starting Self correcting 19
20. 20. DESIGN OF SEQUENTIAL CIRCUITS  Design a clocked sequential circuit with the given state diagram. Use JK flip-flops. 0 20
21. 21. Excitation table 0 21
22. 22. Karnaugh map 22
23. 23. Logic diagram 23
24. 24. Design with unused states  Design a sequential circuit to satisfy the state diagram shown in figure(57). Use SR flip-flops. Treat the unused states as do not care conditions. 24
25. 25. Excitation table : 25
26. 26. Karnaugh map 26
27. 27. Karnaugh map 27
28. 28. Logic diagram 28
29. 29. Effect Of The Unused States    Analyze the sequential circuit obtained and determine the effect of the unused states The unused states are : 000 , 110 , 111. We can solve this problem like any analysis problem Flip-flops input functions  29
30. 30.  Draw the state table of the unused states 30
31. 31. State diagram  The circuit is self- starting and self-correcting. 31
32. 32. Design of counters  Design a counter with the following binary sequence and repeat ( 0,1,2, 4,5,6 ). Use J K flip flops. 32
33. 33.  Excitation table : 33
34. 34. JA=B JB = C KA = B JC = B‘ 34
35. 35. Effect of the two unused states :  State table 35
36. 36. State diagram of the counter 36
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