The objectives of scaling digital CMOS is to enable smaller, faster, lower power, and lower cost logic circuits and microprocessors.
High-k gate insulators are desperately need to maintain higher gate currents.
Ultra-thin SOI can also enhance device designs.
Improvement in CMOS device designs will greatly increase gate current and device off current: will reach power crisis and make the power problem much worse.
2) System Memory
Full Custom Processor designers have been integrating increasing amounts of high-speed cache SRAM memory on processor chips to minimize cache-miss penalty and to reduce power dissipation associated with memory access.
Trend for improving system performance is to increase the amount of on chip high-speed embedded DRAM compatible with a high-performance logic process to reduce power dissipation.
Alternatively, embedded DRAM technology compatible with a high-performance logic process can be used to design stand-alone or embedded high-density 1T SRAM to improve system performance and power dissipation.
SoC integration is certainly one direction for improving system performance and reducing system power dissipation.
SoC will be very attractive as a technology trend for meeting system needs.
Hower, designers often find SoC integration not the lowest-cost solution sometimes. In-Package integration may be able to offer a lower-cost solution to connect processor and memory chips then the embedded memory on SoC case.
Embedded memory in SoC can offer higher performance and lower power dissipation because data transfer on chip is much faster than off chip case.
7) SiPs Step Into the Mainstream
Multi-chip package (MCP) are increasingly being used in small, portable consumer and computing systems, such as cell phones and PDAs, to enable the lower power, smaller form factors, and lower cost than system designers seek when developing these medium-to high-volume products.
In the future SiP are used instead of pricier SoC for RF components, as well as for combining processors, logic and memory in a single package.
For the purposes of reducing power consumption, cost and size, the needs to increase silicon density and gain higher reliability have combined to use MCP for many applications consist of DRAM, SRAM, NAND Flash, ROM and RF components, etc.
The number of dual handsets, supporting both Global System for Mobile Communication/General Packet Radio Service (GSM/GPRS) and wideband code division multiple access (W-CDMA) is expected to soar very soon. This will drive the full custom IC designers to integrate the transceiver and baseband circuits using the same CMOS technology with high-Q inductors and MIM capacitors, first for the GSM/GPRS single chip. As the next step, the designers are considering integrating the W-CDMA chip and the GSM/GPRS chip into a single IC.