ECE 353 Introduction to Microprocessor Systems Michael J. Schulte Week 9
Administrative Matters <ul><li>Quiz #2 is Thursday, April 10 th  from 7:15 to 8:30 PM </li></ul><ul><ul><li>Covers modules...
Topics <ul><li>Memory technologies </li></ul><ul><li>Organization and operation of typical SRAM, EPROM and flash memory de...
Memory Terminology <ul><li>How could we classify memory devices? </li></ul><ul><li>Read-Only Memory (ROM) </li></ul><ul><u...
Memory Technologies <ul><li>ROM (non-volatile) </li></ul><ul><ul><li>Masked ROM </li></ul></ul><ul><ul><li>Field programma...
Memory Organization <ul><li>Logical organization </li></ul><ul><ul><li>Organization as seen looking at the device from the...
SRAM Interfaces <ul><li>RAM with 3 control inputs </li></ul><ul><ul><li>/CS, /OE, /WE </li></ul></ul><ul><ul><li>Read </li...
SRAM Organization <ul><li>Logical Organization </li></ul><ul><ul><li>Typically 1, 4 , 8 or 16 bit widths </li></ul></ul><u...
EPROM <ul><li>Electrically programmable, non-volatile </li></ul><ul><li>Requires UV light to erase </li></ul><ul><ul><li>Q...
Flash Memory <ul><li>Actually Flash EEPROM, commonly just called flash memory </li></ul><ul><li>Characteristics </li></ul>...
Memory Subsystem Design <ul><li>Memory banks  </li></ul><ul><ul><li>Increasing memory width </li></ul></ul><ul><ul><li>Inc...
Memory Architectures <ul><li>Wide (n-byte) buses </li></ul><ul><ul><li>Addressing effects </li></ul></ul><ul><ul><li>Byte ...
Memory Subsystems Review <ul><li>What is the purpose of an address decoder circuit, and where does its output usually get ...
SRAM Timing Characteristics <ul><li>An SRAM device has key timing parameters specified for the read cycle. </li></ul><ul><...
Sample Timing Diagram
7C1046 SRAM
27C512 EPROM
HM624100HC SRAM
SRAM Timing Compatibility <ul><li>In order to ensure that we will be able to reliably read and write the memory device, we...
Wrapping Up <ul><li>Quiz #2 will be held Thursday 4/10/2008 at 7:15-8:30pm </li></ul><ul><ul><li>Covers educational object...
Physical Memory Organization 32K x 8 SRAM
 
 
FAMOS Gate Operation Programming Erasing
JEDEC
Flash Blocks
Flash Memory Application: Disk-on-Key <ul><li>Up to 4GB nonvolatile storage </li></ul><ul><li>No battery or power supply <...
RAM Read – 3 control signals
RAM Write – 3 control signals
Increasing Memory Depth
Increasing Memory Width
Increasing Memory Depth & Width
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Week 1 PowerPoint

  1. 1. ECE 353 Introduction to Microprocessor Systems Michael J. Schulte Week 9
  2. 2. Administrative Matters <ul><li>Quiz #2 is Thursday, April 10 th from 7:15 to 8:30 PM </li></ul><ul><ul><li>Covers modules 3 and 4 (weeks 5-8, hw 3, 4) </li></ul></ul><ul><li>Readings for week 9 </li></ul><ul><ul><li>Textbook 7.5, 9 </li></ul></ul><ul><ul><li>ADUC 9-10, 33-36, 43-47, 79-82 </li></ul></ul><ul><li>Discussion section tonight </li></ul><ul><ul><li>Review for Quiz #2 </li></ul></ul><ul><ul><li>Problems post on course webpage </li></ul></ul>
  3. 3. Topics <ul><li>Memory technologies </li></ul><ul><li>Organization and operation of typical SRAM, EPROM and flash memory devices </li></ul><ul><li>Memory subsystem design </li></ul><ul><li>Address decoder implementation </li></ul><ul><li>SRAM timing characteristics </li></ul>
  4. 4. Memory Terminology <ul><li>How could we classify memory devices? </li></ul><ul><li>Read-Only Memory (ROM) </li></ul><ul><ul><li>In common usage, it is memory that is nonvolatile. </li></ul></ul><ul><li>Random-Access Memory (RAM) </li></ul><ul><ul><li>The time required to access any memory location is the same – it does not need to be accessed in any order. </li></ul></ul><ul><ul><li>In common usage, it is memory that can be read or written with equal ease. </li></ul></ul>
  5. 5. Memory Technologies <ul><li>ROM (non-volatile) </li></ul><ul><ul><li>Masked ROM </li></ul></ul><ul><ul><li>Field programmable </li></ul></ul><ul><ul><ul><li>EPROM </li></ul></ul></ul><ul><ul><ul><li>OTP PROM (fuse or EPROM) </li></ul></ul></ul><ul><ul><li>Electrically erasable </li></ul></ul><ul><ul><ul><li>EEPROM (or E 2 PROM) </li></ul></ul></ul><ul><ul><ul><li>Flash memory </li></ul></ul></ul><ul><li>RAM (volatile) </li></ul><ul><ul><li>SRAM </li></ul></ul><ul><ul><li>DRAM </li></ul></ul><ul><ul><li>Pseudo-SRAM </li></ul></ul><ul><li>Emerging memory technologies </li></ul>
  6. 6. Memory Organization <ul><li>Logical organization </li></ul><ul><ul><li>Organization as seen looking at the device from the outside </li></ul></ul><ul><ul><li>Linear array of registers (memory locations) </li></ul></ul><ul><li>Physical organization </li></ul><ul><ul><li>Different physical organizations can be used to implement the same logical organization </li></ul></ul><ul><ul><li>Physical organization affects performance and cost </li></ul></ul>
  7. 7. SRAM Interfaces <ul><li>RAM with 3 control inputs </li></ul><ul><ul><li>/CS, /OE, /WE </li></ul></ul><ul><ul><li>Read </li></ul></ul><ul><ul><li>Write </li></ul></ul><ul><li>RAM with 2 control inputs </li></ul><ul><ul><li>/CS, /WE (or R/W) </li></ul></ul>
  8. 8. SRAM Organization <ul><li>Logical Organization </li></ul><ul><ul><li>Typically 1, 4 , 8 or 16 bit widths </li></ul></ul><ul><li>Physical Organization </li></ul><ul><ul><li>Rectangular bit array </li></ul></ul><ul><ul><li>Two-level decoding (row and column) </li></ul></ul><ul><ul><li>Characteristic delays and timing requirements are specified in memory devices datasheet ( Example ) </li></ul></ul><ul><li>NV-SRAM </li></ul><ul><ul><li>Uses an alternate power source to maintain SRAM when system power is off </li></ul></ul><ul><ul><li>Requires logic to switch power sources and prevent spurious writes during power-up/power-down </li></ul></ul>
  9. 9. EPROM <ul><li>Electrically programmable, non-volatile </li></ul><ul><li>Requires UV light to erase </li></ul><ul><ul><li>Quartz window in package </li></ul></ul><ul><li>Floating polysilicon gate avalanche injection MOS transistor (FAMOS) </li></ul><ul><ul><li>Operation </li></ul></ul><ul><li>Programmer loads device out-of-circuit </li></ul><ul><li>OTP EPROMs eliminate quartz window </li></ul><ul><li>EEPROMs are electrically erasable </li></ul><ul><ul><li>Byte-erasable / writeable </li></ul></ul><ul><ul><li>Low-density </li></ul></ul><ul><li>JEDEC Packages </li></ul>
  10. 10. Flash Memory <ul><li>Actually Flash EEPROM, commonly just called flash memory </li></ul><ul><li>Characteristics </li></ul><ul><ul><li>Technologies </li></ul></ul><ul><ul><li>Endurance </li></ul></ul><ul><ul><li>Blocking , programming and erasing </li></ul></ul><ul><li>Applications </li></ul><ul><ul><li>ROM replacement </li></ul></ul><ul><ul><li>GP NV-RAM </li></ul></ul><ul><ul><li>Solid-state disk (flash-disk) Example </li></ul></ul>
  11. 11. Memory Subsystem Design <ul><li>Memory banks </li></ul><ul><ul><li>Increasing memory width </li></ul></ul><ul><ul><li>Increasing memory depth </li></ul></ul><ul><ul><li>Increasing memory width and depth </li></ul></ul><ul><li>Address decoding </li></ul><ul><ul><li>Boundaries </li></ul></ul><ul><ul><ul><li>If address is a 2 m boundary, then what is the result of ( address AND (2 m -1))? </li></ul></ul></ul><ul><ul><ul><li>We normally decode memory devices to be aligned on boundaries at least as large as they are </li></ul></ul></ul><ul><ul><li>Exhaustive (full) vs. partial (reduced) decoding </li></ul></ul>
  12. 12. Memory Architectures <ul><li>Wide (n-byte) buses </li></ul><ul><ul><li>Addressing effects </li></ul></ul><ul><ul><li>Byte transfer support </li></ul></ul><ul><ul><ul><li>Data lanes </li></ul></ul></ul><ul><ul><ul><li>Control signals </li></ul></ul></ul><ul><li>Bus resizing </li></ul><ul><ul><li>Static </li></ul></ul><ul><ul><li>Configurable </li></ul></ul><ul><ul><li>Dynamic </li></ul></ul>
  13. 13. Memory Subsystems Review <ul><li>What is the purpose of an address decoder circuit, and where does its output usually get connected? </li></ul><ul><li>What is exhaustive decoding, and what effects does it have? </li></ul><ul><li>What is partial decoding, and what effects does it have? </li></ul>
  14. 14. SRAM Timing Characteristics <ul><li>An SRAM device has key timing parameters specified for the read cycle. </li></ul><ul><ul><li>t AA – address access time </li></ul></ul><ul><ul><ul><li>t RDHA – data valid after address changes </li></ul></ul></ul><ul><ul><li>t ACS – chip select access time </li></ul></ul><ul><ul><ul><li>t RHCS – data valid after chip select </li></ul></ul></ul><ul><ul><ul><li>t CHZ – time until device floats bus after chip select dis-asserted </li></ul></ul></ul><ul><ul><li>t OE – output enable access time </li></ul></ul><ul><ul><ul><li>t OHZ – time until device floats bus after output enable dis-asserted </li></ul></ul></ul><ul><ul><li>t RC – read cycle time </li></ul></ul><ul><li>The write cycle has a complementary set of specifications. </li></ul>
  15. 15. Sample Timing Diagram
  16. 16. 7C1046 SRAM
  17. 17. 27C512 EPROM
  18. 18. HM624100HC SRAM
  19. 19. SRAM Timing Compatibility <ul><li>In order to ensure that we will be able to reliably read and write the memory device, we need to ensure that the processor system bus interface is compatible with the memory device. </li></ul><ul><li>This is accomplished by analyzing the timing for all relevant parameters of both the processor and memory, and ensuring that the operations can be completed reliably. </li></ul>
  20. 20. Wrapping Up <ul><li>Quiz #2 will be held Thursday 4/10/2008 at 7:15-8:30pm </li></ul><ul><ul><li>Covers educational objectives for modules 3 and 4 (weeks 5 through 8) </li></ul></ul><ul><ul><li>Single 3x5 card with original handwritten notes </li></ul></ul><ul><ul><li>No calculators </li></ul></ul><ul><ul><li>Instruction set references and any needed datasheets will be provided </li></ul></ul><ul><li>Reading for next week </li></ul><ul><ul><li>Supplement #3, review chapter 9 in text </li></ul></ul>
  21. 21. Physical Memory Organization 32K x 8 SRAM
  22. 24. FAMOS Gate Operation Programming Erasing
  23. 25. JEDEC
  24. 26. Flash Blocks
  25. 27. Flash Memory Application: Disk-on-Key <ul><li>Up to 4GB nonvolatile storage </li></ul><ul><li>No battery or power supply </li></ul>Specifications: Data retention up to 10 years Erase cycles: 1,000,000 times Shock resistance: 1000 G (maximum)
  26. 28. RAM Read – 3 control signals
  27. 29. RAM Write – 3 control signals
  28. 30. Increasing Memory Depth
  29. 31. Increasing Memory Width
  30. 32. Increasing Memory Depth & Width

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