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Utilizing the SPI Flash Memory on the Desktop NanoBoard NB2DSK01
Utilizing the SPI Flash Memory on the Desktop NanoBoard NB2DSK01
Utilizing the SPI Flash Memory on the Desktop NanoBoard NB2DSK01
Utilizing the SPI Flash Memory on the Desktop NanoBoard NB2DSK01
Utilizing the SPI Flash Memory on the Desktop NanoBoard NB2DSK01
Utilizing the SPI Flash Memory on the Desktop NanoBoard NB2DSK01
Utilizing the SPI Flash Memory on the Desktop NanoBoard NB2DSK01
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Utilizing the SPI Flash Memory on the Desktop NanoBoard NB2DSK01

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  • 1. Utilizing the SPI Flash Memory on the Desktop NanoBoard NB2DSK01 Summary This application note describes how the serial Flash memory on the Desktop NanoBoard NB2DSK01 can be Application Note used as embedded memory within an FPGA design. AP0162 (v1.1) December 17, 2007 The Desktop NanoBoard NB2DSK01 provides serial Flash memory for use as embedded memory in an FPGA design. This enables you to load and store an embedded software file that will be used when the target design is running. One example of where such functionality would prove useful is in a design that takes, as input, an audio data file, and subsequently processes the data from that file. The audio file would be just the candidate for storage in the serial Flash memory provided by the NB2DSK01. For detailed information on the Desktop NanoBoard NB2DSK01, refer to the document TR0143 Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01. Serial SPI Flash memory on the NB2DSK01 The NB2DSK01 provides serial Flash memory in the form of two M25P80 8-Mbit devices (from STMicroelectronics). These devices support a serial data rate of 25MHz. The M25P80 is an SPI- compatible device, with both devices accessed through the NB2DSK01's SPI Controller, which itself resides within the Xilinx Spartan-3 NanoTalk Controller. The function of the two devices (designated U20 and U21) can be summarized as follows: • U20 – used as Embedded memory. This device is used to provide embedded memory functionality within an FPGA design, enabling you to load and store an embedded software file that will be used when the target design is running. • U21 – used as either Embedded memory or Boot memory. This device can be used from within an FPGA design, as described above. It can also be used to store the programming file required for implementing a design within the daughter board FPGA. This gives you the ability to 'bootstrap' the FPGA device upon powering-up the NB2DSK01. For more information on the M25P80 device, refer to the datasheet (m25p80.pdf) available at www.st.com. AP0162 (v1.1) December 17, 2007 1
  • 2. Utilizing the SPI Flash Memory on the Desktop NanoBoard NB2DSK01 Wiring the Flash memory into an FPGA design Accessing the Serial Flash memory from within an FPGA design is most easily accomplished by placing and wiring a Serial Peripheral Interface Controller device (SPI_W) and the SERIALFMEMORY port component, which represents the pins of the physical FPGA device. Of course, you may be using your own HDL-based controller or, if feeling brave, attempt bit-banging direct from the processor in your design. The SPI_W however provides a simple and efficient interface solution. This Wishbone-compliant device offers full duplex communications and a serial clock that is configurable for polarity, phase and frequency. It is readily available for placement within your design: • From a schematic document, the SPI_W device can be found in the FPGA Peripherals integrated library (Program FilesAltium Designer 6LibraryFpgaFPGA Peripherals.IntLib). • From an OpenBus System document, the SPI component can be found in the Peripherals region of the OpenBus Palette panel. A word addressing variant is also provided. For more information on the SPI_W peripheral, refer to the document CR0153 SPI_W Serial Peripheral Interface Controller. The SERIALFMEMORY port component can be found in the FPGA NB2DSK01 Port-Plugin integrated library (Program FilesAltium Designer 6LibraryFpgaFPGA NB2DSK01 Port- Plugin.IntLib). Figure 1 illustrates how the SPI Flash memory can be wired into a schematic-based design that uses a 32-bit processor – in this case a TSK3000A. A configurable Wishbone Interconnect device (WB_INTERCON) is used to simplify connection and also handle the address mapping – taking the 24- bit address line from the processor and mapping it to the 2-bit address line used to drive the intermediate SPI Controller device (SPI_W). Figure 1. Accessing the SPI Flash memory from an FPGA design. 2 AP0162 (v1.1) December 17, 2007
  • 3. Utilizing the SPI Flash Memory on the Desktop NanoBoard NB2DSK01 Communicating with multiple SPI devices When interfacing to a single SPI device from an FPGA design, access to the device is straightforward – simply place the specific port component representing the interface to that device, and wire to it (typically from an interface controller in the design). If your design is to communicate with multiple SPI devices, you can not simply place the corresponding specific port component for each device. To do so would result in multiple port components with the same pin names being used. This duplication of names will lead to errors when the design is processed for the target FPGA device. The solution is to place, and wire to, a single SPI-based port component. To use a specific port component can make the design hard to read, especially if the device represented graphically by the component is not even targeted by that design! To avoid this situation, a generic SPI-based port component is provided. Table 1 summarizes this component, which can be placed from the FPGA NB2DSK01 Port-Plugin.IntLib. Note: Your design may need to communicate with multiple SPI-based resources, but remember that communications can only be carried out with one such resource at a time. Access to each device, in turn, would be achieved through the embedded software for your design. Table 1. Generic SPI port-plugin component. Component Symbol Component Name Description SPI_BUS Place this component to include a generic interface to the NB2DSK01 motherboard's SPI bus within your FPGA design. SPI communications The NB2DSK01 SPI system involves a variety of SPI-compatible slave resources, located across the hardware system – on the NB2DSK01 motherboard itself and also on certain peripheral boards that plug in to the motherboard. These SPI resources are accessible by three distinct SPI masters: • Altium Designer (via the parallel or USB connection) • The firmware – more specifically a TSK3000A processor therein – loaded onto the motherboard's Spartan-3 FPGA device (the NanoTalk Controller) • The design loaded onto the currently plugged-in daughter board FPGA device. Providing the required SPI bus arbitration between the masters, and access to the SPI devices, is the NB2DSK01's SPI Controller. The Controller, which is part of the NanoBoard firmware, plays the role of multiplexer/router – determining which master has access to the SPI bus and which SPI slave device is selected for communications. During operation, the daughter board FPGA design communicates with the NB2DSK01's SPI Controller to establish a path between the design and a specific motherboard/peripheral board SPI device. For detailed information on the Desktop NanoBoard's SPI communications system, refer to the document AP0163 SPI Communications on the Desktop NanoBoard NB2DSK01. AP0162 (v1.1) December 17, 2007 3
  • 4. Utilizing the SPI Flash Memory on the Desktop NanoBoard NB2DSK01 Programming the Flash memory The procedure for loading an embedded software file into the Flash memory can be carried out at any time – with or without an FPGA project open and irrespective of whether a design is currently programmed into the target FPGA device (on the daughter board). Controls to download to, and erase, the Flash memory, can be found in the Flash RAM Controller For Embedded Software dialog. Access to this dialog and use of its controls are detailed in the following sections. Accessing Flash memory controls The Flash RAM Controller For Embedded Software dialog is accessed directly from the instrument panel for the NB2DSK01's NanoTalk Controller. From the Devices view (View » Devices View), simply double-click on the icon for the NanoBoard (in the NanoBoard Controllers chain) whose embedded Flash memory you wish to load. The Instrument Rack – NanoBoard Controllers panel will appear. Click on the Embedded button to access the dialog (Figure 3). Note: If using the SPI Flash memory device that can be used for embedded or boot purposes, click on the FPGA Boot button to access the Flash RAM Controller For FPGA Boot dialog. The programming process is identical. Figure 2. Accessing controls for the embedded Flash memory. The Device ID region of the dialog reflects the communications link between the NanoTalk Controller and the Flash memory device. If communications are successful, upon accessing the dialog a value of $13 will be entered into the far right field and the confirmatory message "Device Found: M25P80 4 AP0162 (v1.1) December 17, 2007
  • 5. Utilizing the SPI Flash Memory on the Desktop NanoBoard NB2DSK01 (8M-Bit Serial Flash RAM)" will be displayed. If this is not the case, try to manually interrogate the communications link by pressing the Read Electronic Signature button. Erasing the Flash memory Before loading the required embedded software file into the Flash memory device, the memory must first be cleared. To erase the entire 8Mbit of Flash memory, press the Erase Entire Device button, in the Erase region of the Flash RAM Controller For Embedded Software dialog. The erasing process will take approximately five to eight seconds, after which a confirmation dialog will appear (Figure 4). Controls are also available for erasing a particular sector of Figure 3. Confirming full memory erasure. memory. Each M25P80 device is organized into 16 sectors. Each sector contains 256 pages, and each page is 256 bytes wide. Therefore each sector is 65536 bytes or 512Kbits. Simply use the available drop-down to select the sector you wish to erase (or enter the sector number directly) and then click the Erase Sector button. Erasure time is typically less than a second, after which time you will receive a dialog to confirm completion of the erase (Figure 5). To verify that the device has been successfully erased, press the Figure 4. Confirming sector erasure. Blank Check button. The verification process will take approximately sixty seconds, after which time you will receive another confirmation dialog (Figure 6). Figure 5. Verification of memory erasure. Downloading to Flash memory Once the Flash memory has been erased, the embedded software file can be downloaded. From the Download region of the Flash RAM Controller For Embedded Software dialog, press the ... button to the right of the File Name field. The Choose Embedded Software File For Download dialog will appear. Use this dialog to browse to, and open, the required file. After choosing the file and clicking Open, you will be returned to the Flash RAM Controller For Embedded Software dialog. The chosen file (including path) will be displayed in the File Name field (Figure 7). AP0162 (v1.1) December 17, 2007 5
  • 6. Utilizing the SPI Flash Memory on the Desktop NanoBoard NB2DSK01 Figure 6. Embedded software file chosen and ready for download. To download this file to the Flash memory device, simply click the Save File To Flash button. If you want to download to a specific area of memory, enter the required address in the Memory Address field. The download process will proceed, with progress shown in Altium Designer's Status bar. At the end of the download an information dialog will appear, confirming the end of the process (Figure 8). Figure 7. Confirmation of file download to the Flash memory device. 6 AP0162 (v1.1) December 17, 2007
  • 7. Utilizing the SPI Flash Memory on the Desktop NanoBoard NB2DSK01 Verifying the download After you have downloaded the embedded software file to the Flash memory device, a check should be made to ensure the integrity of the file. To do this, simply click on the Verify against File button, in the Download region of the Flash RAM Controller For Embedded Software dialog. The contents of the Flash memory are read back and compared against the original embedded software file. Progress is again reflected in Altium Designer's Status bar. An information dialog will appear at the end of the process, providing details of the verification results (Figure 9). If the download process is shown to have failed, the dialog will report an error count. A large number of errors typically indicates that the Flash memory device was not successfully erased prior to downloading the embedded software file. In this Figure 8. Successful verification of downloaded file. case, try erasing the device again – using the Erase Entire Device button – and then using the Blank Check button to verify that the device's memory has indeed been successfully erased. The embedded software file can then be downloaded again. Revision History Date Version No. Revision 06-Nov-2007 1.0 Initial release 17-Dec-2007 1.1 Updated for Altium Designer 6.9 Software, hardware, documentation and related materials: Copyright © 2007 Altium Limited. All rights reserved. You are permitted to print this document provided that (1) the use of such is for personal use only and will not be copied or posted on any network computer or broadcast in any media, and (2) no modifications of the document is made. Unauthorized duplication, in whole or part, of this document by any means, mechanical or electronic, including translation into another language, except for brief excerpts in published reviews, is prohibited without the express written permission of Altium Limited. Unauthorized duplication of this work may also be prohibited by local statute. Violators may be subject to both criminal and civil penalties, including fines and/or imprisonment. Altium, Altium Designer, Board Insight, Design Explorer, DXP, LiveDesign, NanoBoard, NanoTalk, P-CAD, SimCode, Situs, TASKING, and Topological Autorouting and their respective logos are trademarks or registered trademarks of Altium Limited or its subsidiaries. All other registered or unregistered trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed. AP0162 (v1.1) December 17, 2007 7

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