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USB MCU with 64KB Flash Memory

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  • 1. Features • Programmable Audio Output for Interfacing with Common Audio DAC – PCM Format Compatible – I2S Format Compatible • 8-bit MCU C51 Core-based (FMAX = 20 MHz) • 2304 Bytes of Internal RAM • 64K Bytes of Code Memory – AT89C5132: Flash (100K Write/Erase Cycles) • 4K Bytes of Boot Flash Memory (AT89C5132) – ISP: Download from USB (standard) or UART (option) • USB Rev 1.1 Device Controller – “Full Speed” Data Transmission USB • • Built-in PLL MultiMedia Card® Interface Compatibility Microcontroller • Atmel DataFlash® SPI Interface Compatibility • IDE/ATAPI Interface with 64K Bytes • 2 Channels 10-bit ADC, 8 kHz (8 True Bits) – Battery Voltage Monitoring Flash Memory – Voice Recording Controlled by Software • Up to 44 Bits of General-purpose I/Os – 4-bit Interrupt Keyboard Port for a 4 x n Matrix – SmartMedia® Software Interface AT89C5132 • Two Standard 16-bit Timers/Counters • Hardware Watchdog Timer • Standard Full Duplex UART with Baud Rate Generator • Two Wire Master and Slave Modes Controller • SPI Master and Slave Modes Controller • Power Management – Power-on Reset – Software Programmable MCU Clock – Idle Mode, Power-down Mode • Operating Conditions – 3V, ±10%, 25 mA Typical Operating at 25°C – Temperature Range: -40°C to +85°C • Packages – TQFP80, PLCC84 (Development Board Only) – Dice 1. Description The AT89C5132 is a mass storage device controlling data exchange between various Flash modules, HDD and CD-ROM. The AT89C5132 includes 64K Bytes of Flash memory and allows In-System Program- ming through an embedded 4K Bytes of Boot Flash Memory. The AT89C5132 include 2304 Bytes of RAM memory. The AT89C5132 provides all the necessary features for man-machine interface including, timers, keyboard port, serial or parallel interface (USB, SPI, IDE), ADC input, I2S output, and all external memory interface (NAND or NOR Flash, SmartMe- dia, MultiMedia, DataFlash cards). 2. Typical Applications • Flash Recorder/Writer • PDA, Camera, Mobile Phone • PC Add-on 4173ES–USB–09/07
  • 2. 3. Block Diagram Figure 3-1. AT89C5132 Block Diagram INT0 INT1 VDD VSS UVDD UVSS AVDD AVSS AREF AIN1:0 TXD RXD T0 T1 SS MISO MOSI SCK SCL SDA 1 1 1 1 1 1 2 2 2 2 1 1 Interrupt Flash Handler Unit UART RAM 64K Bytes 10-bit A-to-D Timers 0/1 SPI/DataFlash TWI and 2304 Bytes Converter BRG Watchdog Controller Controller Flash Boot 4K Bytes C51 (X2 CORE) 8-BIT INTERNAL BUS I/O I2S/PCM USB MMC Keyboard Ports Audio Interface Controller Interface Interface IDE Clock and PLL Interface Unit 3 FILT X1 X2 RST DOUT DCLK DSEL SCLK D+ D- MCLK MDAT MCMD KIN3:0 P0 - P5 Notes: 1. Alternate function of Port 3 2. Alternate function of Port 4 3. Alternate function of Port 1 2 AT89C5132 4173ES–USB–09/07
  • 3. AT89C5132 4. Pin Description Figure 4-1. AT89C5132 80-pin TQFP Package P4.1/MOSI P4.0/MISO P4.2/SCK P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P4.3/SS P2.0/A8 P2.1/A9 VDD P5.1 P5.0 P4.7 P4.6 VSS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ALE 1 60 P4.5 ISP 2 59 P4.4 P1.0/KIN0 3 58 P2.2/A10 P1.1/KIN1 4 57 P2.3/A11 P1.2/KIN2 5 56 P2.4/A12 P1.3/KIN3 6 55 P2.5/A13 P1.4 7 54 P2.6/A14 P1.5 8 53 P2.7/A15 P1.6/SCL 9 52 VSS P1.7/SDA 10 51 VDD VDD 11 TQFP80 50 MCLK PVDD 12 49 MDAT FILT 13 48 MCMD PVSS 14 47 RST VSS 15 46 SCLK X2 16 45 DSEL X1 17 44 DCLK TST 18 43 DOUT UVDD 19 42 VSS UVSS 20 41 VDD 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 D- VSS AVSS AREFP VDD P3.7/RD AVDD AREFN AIN0 AIN1 P5.2 P5.3 D+ P3.6/WR 3 4173ES–USB–09/07
  • 4. Figure 4-2. AT89C5132 84-pin PLCC (1) P4.1/MOSI P4.0/MISO P4.2/SCK P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P4.3/SS P2.0/A8 P2.1/A9 VDD P5.1 P5.0 P4.7 P4.6 VSS NC 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 ALE 12 74 NC ISP 13 73 P4.5 P1.0/KIN0 14 72 P4.4 P1.1/KIN1 15 71 P2.2/A10 P1.2/KIN2 16 70 P2.3/A11 P1.3/KIN3 17 69 P2.4/A12 P1.4 18 68 P2.5/A13 P1.5 19 67 P2.6/A14 P1.6/SCL 20 66 P2.7/A15 P1.7/SDA 21 65 VSS VDD 22 PLCC84 64 VDD PAVDD 23 63 MCLK FILT 24 62 MDAT PAVSS 25 61 MCMD VSS 26 60 RST X2 27 59 SCLK NC 28 58 DSEL X1 29 57 DCLK TST 30 56 DOUT UVDD 31 55 VSS UVSS 32 54 VDD 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD VDD P3.0/RXD AVDD AREFN AIN0 AIN1 P5.2 P5.3 NC D+ P3.1/TXD D- VSS AVSS AREFP Note: 1. For development board only. 4.1 Signals All the AT89C5132 signals are detailed by functionality in Table 1 to Table 14. Table 1. Ports Signal Description Signal Alternate Name Type Description Function Port 0 P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written P0.7:0 I/O AD7:0 to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, floating P0 inputs must be polarized to VDD or VSS. KIN3:0 Port 1 P1.7:0 I/O SCL P1 is an 8-bit bidirectional I/O port with internal pull-ups. SDA 4 AT89C5132 4173ES–USB–09/07
  • 5. AT89C5132 Signal Alternate Name Type Description Function Port 2 P2.7:0 I/O A15:8 P2 is an 8-bit bidirectional I/O port with internal pull-ups. RXD TXD INT0 Port 3 INT1 P3.7:0 I/O P3 is an 8-bit bidirectional I/O port with internal pull-ups. T0 T1 WR RD MISO Port 4 MOSI P4.7:0 I/O P4 is an 8-bit bidirectional I/O port with internal pull-ups. SCK SS Port 5 P5.3:0 I/O - P5 is a 4-bit bidirectional I/O port with internal pull-ups. Table 2. Clock Signal Description Signal Alternate Name Type Description Function Input to the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. X1 I - If an external oscillator is used, its output is connected to this pin. X1 is the clock source for internal timing. Output of the on-chip inverting oscillator amplifier X2 O To use the internal oscillator, a crystal/resonator circuit is connected to this pin. - If an external oscillator is used, leave X2 unconnected. PLL Low Pass Filter input FILT I - FILT receives the RC network of the PLL low pass filter. Table 3. Timer 0 and Timer 1 Signal Description Signal Alternate Name Type Description Function Timer 0 Gate Input INT0 serves as external run control for timer 0, when selected by GATE0 bit in TCON register. INT0 I External Interrupt 0 P3.2 INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set, bit IE0 is set by a falling edge on INT0. If bit IT0 is cleared, bit IE0 is set by a low level on INT0. Timer 1 Gate Input INT1 serves as external run control for timer 1, when selected by GATE1 bit in TCON register. INT1 I External Interrupt 1 P3.3 INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set, bit IE1 is set by a falling edge on INT1. If bit IT1 is cleared, bit IE1 is set by a low level on INT1. 5 4173ES–USB–09/07
  • 6. Signal Alternate Name Type Description Function Timer 0 External Clock Input T0 I When timer 0 operates as a counter, a falling edge on the T0 pin increments P3.4 the count. Timer 1 External Clock Input T1 I When timer 1 operates as a counter, a falling edge on the T1 pin increments P3.5 the count. Table 4. Audio Interface Signal Description Signal Alternate Name Type Description Function DCLK O DAC Data Bit Clock - DOUT O DAC Audio Data - DAC Channel Select Signal DSEL O - DSEL is the sample rate clock output. DAC System Clock SCLK O SCLK is the oversampling clock synchronized to the digital audio data (DOUT) - and the channel selection signal (DSEL). Table 5. USB Controller Signal Description Signal Alternate Name Type Description Function USB Positive Data Upstream Port D+ I/O - This pin requires an external 1.5 KΩ pull-up to VDD for full speed operation. D- I/O USB Negative Data Upstream Port - Table 6. MutiMediaCard Interface Signal Description Signal Alternate Name Type Description Function MMC Clock output MCLK O - Data or command clock transfer. MMC Command line Bidirectional command channel used for card initialization and data transfer MCMD I/O - commands. To avoid any parasitic current consumption, unused MCMD input must be polarized to VDD or VSS. MMC Data line MDAT I/O Bidirectional data channel. To avoid any parasitic current consumption, unused - MDAT input must be polarized to VDD or VSS. 6 AT89C5132 4173ES–USB–09/07
  • 7. AT89C5132 Table 7. UART Signal Description Signal Alternate Name Type Description Function Receive Serial Data RXD I/O RXD sends and receives data in serial I/O mode 0 and receives data in serial P3.0 I/O modes 1, 2 and 3. Transmit Serial Data TXD O TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O P3.1 modes 1, 2 and 3. Table 8. SPI Controller Signal Description Signal Alternate Name Type Description Function SPI Master Input Slave Output Data Line MISO I/O When in master mode, MISO receives data from the slave peripheral. When in P4.0 slave mode, MISO outputs data to the master controller. SPI Master Output Slave Input Data Line MOSI I/O When in master mode, MOSI outputs data to the slave peripheral. When in P4.1 slave mode, MOSI receives data from the master controller. SPI Clock Line SCK I/O When in master mode, SCK outputs clock to the slave peripheral. When in P4.2 slave mode, SCK receives clock from the master controller. SPI Slave Select Line SS I P4.3 When in controlled slave mode, SS enables the slave mode. Table 9. TWI Controller Signal Description Signal Alternate Name Type Description Function TWI Serial Clock When TWI controller is in master mode, SCL outputs the serial clock to the SCL I/O P1.6 slave peripherals. When TWI controller is in slave mode, SCL receives clock from the master controller. TWI Serial Data SDA I/O P1.7 SDA is the bidirectional Two Wire data line. Table 10. A/D Converter Signal Description Signal Alternate Name Type Description Function AIN1:0 I A/D Converter Analog Inputs - AREFP I Analog Positive Voltage Reference Input - Analog Negative Voltage Reference Input AREFN I - This pin is internally connected to AVSS. 7 4173ES–USB–09/07
  • 8. Table 11. Keypad Interface Signal Description Signal Alternate Name Type Description Function Keypad Input Lines KIN3:0 I Holding one of these pins high or low for 24 oscillator periods triggers a P1.3:0 keypad interrupt. Table 12. External Access Signal Description Signal Alternate Name Type Description Function Address Lines A15:8 I/O Upper address lines for the external bus. P2.7:0 Multiplexed higher address and data lines for the IDE interface. Address/Data Lines AD7:0 I/O Multiplexed lower address and data lines for the external memory or the IDE P0.7:0 interface. Address Latch Enable Output ALE signals the start of an external bus cycle and indicates that valid address ALE O - information is available on lines A7:0. An external latch is used to demultiplex the address from address/data bus. ISP Enable Input ISP I/O This signal must be held to GND through a pull-down resistor at the falling - reset to force execution of the internal bootloader. Read Signal RD O P3.7 Read signal asserted during external data memory read operation. Write Signal WR O P3.6 Write signal asserted during external data memory write operation. Table 13. System Signal Description Signal Alternate Name Type Description Function Reset Input Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage lower than VIL is applied, whether or not the oscillator is running. RST I - This pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and VDD. Asserting RST when the chip is in Idle mode or Power-Down mode returns the chip to normal operation. Test Input TST I - Test mode entry signal. This pin must be set to VDD. 8 AT89C5132 4173ES–USB–09/07
  • 9. AT89C5132 Table 14. Power Signal Description Signal Alternate Name Type Description Function Digital Supply Voltage VDD PWR - Connect these pins to +3V supply voltage. Circuit Ground VSS GND - Connect these pins to ground. Analog Supply Voltage AVDD PWR - Connect this pin to +3V supply voltage. Analog Ground AVSS GND - Connect this pin to ground. PLL Supply voltage PVDD PWR - Connect this pin to +3V supply voltage. PLL Circuit Ground PVSS GND - Connect this pin to ground. USB Supply Voltage UVDD PWR - Connect this pin to +3V supply voltage. USB Ground UVSS GND - Connect this pin to ground. 9 4173ES–USB–09/07
  • 10. 4.2 Internal Pin Structure Table 15. Detailed Internal Pin Structure Circuit(1) Type Pins VDD RTST Input TST VDD Watchdog Output P Input/Output RST RRST VSS VDD VDD VDD 2 osc periods P1(2) Latch Output P1 P2 P3 P2(3) Input/Output P3 P4 N P53:0 VSS VDD P0 P MCMD Input/Output MDAT ISP N PSEN VSS VDD ALE SCLK P DCLK Output DOUT DSEL N MCLK VSS D+ D+ Input/Output D- D- Notes: 1. For information on resistors value, input/output levels, and drive capability, refer to the Section “DC Characteristics”, page 183. 2. When the Two Wire controller is enabled, P1, P2, and P3 transistors are disabled allowing pseudo open-drain structure. 3. In Port 2, P1 transistor is continuously driven when outputting a high level bit address (A15:8). 10 AT89C5132 4173ES–USB–09/07
  • 11. AT89C5132 5. Address Spaces The AT8xC5132 derivatives implement four different address spaces: • Program/Code Memory • Boot Memory • Data Memory • Special Function Registers (SFRs) 5.0.1 Code Memory The AT89C5132 implements 64K Bytes of on-chip program/code memory in Flash technology. The Flash memory increases ROM functionality by enabling in-circuit electrical erasure and pro- gramming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD voltage. Thus, the AT89C5132 can be programmed using only one voltage and allows in application software programming commonly known as IAP. Hardware programming mode is also available using specific pro- gramming tools. 5.0.2 Boot Memory The AT89C5132 implements 4K Bytes of on-chip boot memory provided in Flash technology. This boot memory is delivered programmed with a standard bootloader software allowing in sys- tem programming commonly known as ISP. It also contains some Application Programming Interfaces routines commonly known as API allowing user to develop his own bootloader. 5.0.3 Data Memory The AT89C5132 derivatives implement 2304 bytes of on-chip data RAM. This memory is divided in two separate areas: • 256 bytes of on-chip RAM memory (standard C51 memory). • 2048 bytes of on-chip expanded RAM memory (ERAM accessible via MOVX instructions). 11 4173ES–USB–09/07
  • 12. Peripherals The AT8xC5132 peripherals are briefly described in the following sections. For further details on how to interface (hardware and software) to these peripherals, please refer to the AT8xC5132 complete datasheet. Clock Generator System The AT8xC5132 internal clocks are extracted from an on-chip PLL fed by an on-chip oscillator. Four clocks are generated respectively for the C51 core, the audio interface, and the other peripherals. The C51 and peripheral clocks are derived from the oscillator clock. The audio interface sample rates are also obtained by dividing the PLL output clock. Ports The AT8xC5132 implement five 8-bit ports (P0 to P4) and one 4-bit port (P5). In addition to performing general-purpose I/Os, some ports are capable of external data memory operations; others allow for alternate functions. All I/O Ports are bidirectional. Each Port contains a latch, an output driver and an input buffer. Port 0 and Port 2 output drivers and input buffers facilitate external memory operations. Some Port 1, Port 3 and Port 4 pins serve for both general-purpose I/Os and alternate functions. Timers/Counters The AT8xC5132 implement the two general-purpose, 16-bit Timers/Counters of a stan- dard C51. They are identified as Timer 0, Timer 1, and can independently be configured each to operate in a variety of modes as a Timer or as an event Counter. When operat- ing as a Timer, a Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, a Timer/Counter counts negative transi- tions on an external pin. After a preset number of counts, the Counter issues an interrupt request. Watchdog Timer The AT8xC5132 implement a hardware Watchdog Timer that automatically resets the chip if it is allowed to time out. The WDT provides a means of recovering from routines that do not complete successfully due to software or hardware malfunctions. Audio Output Interface The AT8xC5132 implements an audio output interface allowing the decoded audio bit- stream to be output in various formats. They are compatible with right and left justification PCM and I2S formats and the on-chip PLL allows connection of almost all commercial audio DAC families available on the market. Universal Serial Bus The AT8xC5132 implements a full-speed Universal Serial Bus Interface. The USB inter- Interface face can be used for the following purposes: • Download of files by supporting the USB mass storage class. • In-System Programming by supporting the USB firmware upgrade class. MultiMedia Card The AT8xC5132 implements a MultiMedia Card (MMC) interface compliant to the V2.2 Interface specification in MultiMedia Card mode. The MMC allows storage of files in removable Flash memory cards that can be easily plugged or removed from the application. It can also be used for In-System Programming. IDE/ATAPI Interface The AT8xC5132 provide an IDE/ATAPI interface allowing connection of devices such as CD-ROM reader, CompactFlash™ cards, Hard Disk Drive, etc. It consists of a 16-bit bidi- rectional bus part of the low-level ANSI ATA/ATAPI specification. It is provided for mass storage interface but could be used for In-System Programming using CD-ROM. 12 AT89C5132 4173ES–USB–09/07
  • 13. AT89C5132 Serial I/O Interface The AT89C5132 implements a serial port with its own baud rate generator providing one single synchronous communication mode and three full-duplex Universal Asynchronous Receiver Transmitter (UART) communication modes. It is provided for the following purposes: • In System Programming. • Remote control of the AT89C5132 by a host. Serial Peripheral The AT89C5132 implements a Serial Peripheral Interface (SPI) supporting master and Interface slave modes. It is provided for the following purposes: • Remote control of the AT89C5132 by a host. • In System Programming. Two-wire Controller The AT89C5132 implements a 2-wire controller supporting the four standard master and slave modes with multimaster capability. It is provided for the following purposes: • Connection of slave devices like LCD controller, audio DAC… • Remote control of the AT89C5132 by a host. • In System Programming. A/D Controller The AT89C5132 implements a 2-channel 10-bit (8 true bits) analog to digital converter (ADC). It is provided for the following purposes: • Battery monitoring. • Voice recording. • Corded remote control. 13 4173ES–USB–09/07
  • 14. 6. Electrical Characteristics 6.1 Absolute Maximum Ratings Storage Temperature ..................................... -65°C to +150°C *NOTICE: Stressing the device beyond the “Absolute Maxi- mum Ratings” may cause permanent damage. Voltage on any other Pin to VSS ..................................... -0.3 to +4.0V These are stress ratings only. Operation beyond the “operating conditions” is not recommended IOL per I/O Pin ................................................................. 5 mA and extended exposure beyond the “Operating Power Dissipation ............................................................. 1 W Conditions” may affect device reliability. Ambient Temperature Under Bias.................... -40°C to +85°C VDD ....................................................................................... 2.7V to 3.3V 6.2 DC Characteristics 6.2.1 Digital Logic Table 1. Digital DC Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85°C Symbol Parameter Min Typ(1) Max Units Test Conditions VIL Input Low Voltage -0.5 0.2·VDD - 0.1 V VIH1 Input High Voltage (except RST, X1) 0.2·VDD + 1.1 VDD V VIH2 Input High Voltage (RST, X1) 0.7·VDD(2) VDD + 0.5 V Output Low Voltage VOL1 (except P0, ALE, MCMD, MDAT, MCLK, 0.45 V IOL= 1.6 mA SCLK, DCLK, DSEL, DOUT) Output Low Voltage VOL2 (P0, ALE, MCMD, MDAT, MCLK, SCLK, 0.45 V IOL= 3.2 mA DCLK, DSEL, DOUT) Output High Voltage VOH1 VDD - 0.7 V IOH= -30 μA (P1, P2, P3, P4 and P5) Output High Voltage (P0, P2 address mode, ALE, MCMD, VOH2 VDD - 0.7 V IOH= -3.2 mA MDAT, MCLK, SCLK, DCLK, DSEL, DOUT, D+, D-) Logical 0 Input Current (P1, P2, P3, P4 IIL -50 μA Vin = 0.45 V and P5) 14 AT89C5132 4173ES–USB–09/07
  • 15. AT89C5132 Table 1. Digital DC Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85°C Symbol Parameter Min Typ(1) Max Units Test Conditions Input Leakage Current (P0, ALE, MCMD, ILI MDAT, MCLK, SCLK, DCLK, DSEL, 10 μA 0.45< VIN< VDD DOUT) Logical 1 to 0 Transition Current ITL -650 μA Vin = 2.0 V (P1, P2, P3, P4 and P5) RRST Pull-Down Resistor 50 90 200 kΩ CIO Pin Capacitance 10 pF TA= 25°C VRET VDD Data Retention Limit 1.8 V X1 / X2 mode VDD < 3.3 V (3) 6.5 / 10.5 12 MHz IDD Operating Current mA 8 / 13.5 16 MHz 9.5 / 17 20 MHz X1 / X2 mode VDD < 3.3 V (3) 5.3 / 8.1 12 MHz IDL Idle Mode Current mA 6.4 / 10.3 16 MHz 7.5 / 13 20 MHz IPD Power-Down Mode Current 20 500 μA VRET < VDD < 3.3 V Notes: 1. Typical values are obtained using VDD= 3 V and TA= 25°C. They are not tested and there is no guarantee on these values. 2. Flash retention is guaranteed with the same formula for VDD min down to 0V. 3. See Table 154 for typical consumption in player mode. 6.2.2 IDD, IDL and IPD Test Conditions Figure 6-1. IDD Test Condition, Active Mode VDD VDD VDD IDD RST PVDD UVDD AVDD (NC) X2 VDD Clock Signal X1 P0 VSS PVSS TST UVSS AVSS VSS All other pins are unconnected 15 4173ES–USB–09/07
  • 16. Figure 6-2. IDL Test Condition, Idle Mode VDD VDD IDL RST PVDD UVDD VSS AVDD (NC) X2 VDD Clock Signal X1 P0 VSS PVSS TST UVSS AVSS VSS All other pins are unconnected Figure 6-3. IPD Test Condition, Power-Down Mode VDD VDD IPD RST PVDD UVDD VSS AVDD VDD (NC) X2 X1 P0 VSS MCMD PVSS MDAT UVSS AVSS TST VSS All other pins are unconnected 6.2.3 A-to-D Converter Table 2. A-to-D Converter DC Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85°C Symbol Parameter Min Typ Max Units Test Conditions AVDD Analog Supply Voltage 2.7 3.3 V AVDD = 3.3V AIDD Analog Operating Supply Current 600 μA AIN1:0 = 0 to AVDD AVDD = 3.3V AIPD Analog Standby Current 2 μA ADEN = 0 or PD = 1 AVIN Analog Input Voltage AVSS AVDD V Reference Voltage AVREF AREFN AVSS V AREFP 2.4 AVDD V RREF AREF Input Resistance 10 30 kΩ TA = 25°C CIA Analog Input capacitance 10 pF TA = 25°C 16 AT89C5132 4173ES–USB–09/07
  • 17. AT89C5132 6.2.4 Oscillator and Crystal 6.2.4.1 Schematic Figure 6-4. Crystal Connection X1 C1 Q C2 VSS X2 Note: For operation with most standard crystals, no external components are needed on X1 and X2. It may be necessary to add external capacitors on X1 and X2 to ground in special cases (max 10 pF). X1 and X2 may not be used to drive other circuits. 6.2.4.2 Parameters Table 3. Oscillator and Crystal Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85°C Symbol Parameter Min Typ Max Unit CX1 Internal Capacitance (X1 - VSS) 10 pF CX2 Internal Capacitance (X2 - VSS) 10 pF CL Equivalent Load Capacitance (X1 - X2) 5 pF DL Drive Level 50 μW F Crystal Frequency 20 MHz RS Crystal Series Resistance 40 Ω CS Crystal Shunt Capacitance 6 pF 6.2.5 Phase Lock Loop 6.2.5.1 Schematic Figure 6-5. PLL Filter Connection FILT R C2 C1 VSS VSS 17 4173ES–USB–09/07
  • 18. 6.2.5.2 Parameters Table 4. PLL Filter Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85°C Symbol Parameter Min Typ Max Unit R Filter Resistor 100 Ω C1 Filter Capacitance 1 10 nF C2 Filter Capacitance 2 2.2 nF 6.2.6 USB Connection 6.2.6.1 Schematic Figure 6-6. USB Connection VDD VBUS To Power RFS Supply D+ D+ RUSB D- D- RUSB GND VSS 6.2.6.2 Parameters Table 16. USB Characteristics VDD = 3 to 3.3 V, TA = -40 to +85°C Symbol Parameter Min Typ Max Unit RUSB USB Termination Resistor 27 Ω RFS USB Full Speed Resistor 1.5 KΩ 6.2.7 In-system Programming 6.2.7.1 Schematic Figure 6-7. ISP Pull-down Connection ISP RISP VSS 6.2.7.2 Parameters Table 5. ISP Pull-Down Characteristics VDD = 3 to 3.3V , TA = -40 to +85°C Symbol Parameter Min Typ Max Unit RISP ISP Pull-Down Resistor 2.2 kΩ 18 AT89C5132 4173ES–USB–09/07
  • 19. AT89C5132 6.3 AC Characteristics 6.3.1 External 8-bit Bus Cycles 6.3.1.1 Definition of Symbols Table 6. External 8-bit Bus Cycles Timing Symbol Definitions Signals Conditions A Address H High D Data In L Low L ALE V Valid Q Data Out X No Longer Valid R RD Z Floating W WR 6.3.1.2 Timings Test conditions: capacitive load on all pins = 50 pF. Table 7. External 8-bit Bus Cycle – Data Read AC Timings VDD = 2.7 to 3.3V, TA = -40° to +85°C Variable Clock Variable Clock Standard Mode X2 Mode Symbol Parameter Min Max Min Max Unit TCLCL Clock Period 50 50 ns TLHLL ALE Pulse Width 2·TCLCL-15 TCLCL-15 ns TAVLL Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLRL ALE Low to RD Low 3·TCLCL-30 1.5·TCLCL-30 ns TRLRH RD Pulse Width 6·TCLCL-25 3·TCLCL-25 ns TRHLH RD high to ALE High TCLCL-20 TCLCL+20 0.5·TCLCL-20 0.5·TCLCL+20 ns TAVDV Address Valid to Valid Data In 9·TCLCL-65 4.5·TCLCL-65 ns TAVRL Address Valid to RD Low 4·TCLCL-30 2·TCLCL-30 ns TRLDV RD Low to Valid Data 5·TCLCL-30 2.5·TCLCL-30 ns TRLAZ RD Low to Address Float 0 0 ns TRHDX Data Hold After RD High 0 0 ns TRHDZ Instruction Float After RD High 2·TCLCL-25 TCLCL-25 ns 19 4173ES–USB–09/07
  • 20. Table 8. External 8-bit Bus Cycle – Data Write AC Timings VDD = 2.7 to 3.3V, TA = -40° to +85°C Variable Clock Variable Clock Standard Mode X2 Mode Symbol Parameter Min Max Min Max Unit TCLCL Clock Period 50 50 ns TLHLL ALE Pulse Width 2·TCLCL-15 TCLCL-15 ns TAVLL Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLWL ALE Low to WR Low 3·TCLCL-30 1.5·TCLCL-30 ns TWLWH WR Pulse Width 6·TCLCL-25 3·TCLCL-25 ns TWHLH WR High to ALE High TCLCL-20 TCLCL+20 0.5·TCLCL-20 0.5·TCLCL+20 ns TAVWL Address Valid to WR Low 4·TCLCL-30 2·TCLCL-30 ns TQVWH Data Valid to WR High 7·TCLCL-20 3.5·TCLCL-20 ns TWHQX Data Hold after WR High TCLCL-15 0.5·TCLCL-15 ns 6.3.1.3 Waveforms Figure 6-8. External 8-bit Bus Cycle – Data Read Waveforms ALE TLHLL TLLRL TRLRH TRHLH RD TRLDV TRLAZ TRHDZ TAVLL TLLAX TRHDX P0 A7:0 D7:0 TAVRL Data In TAVDV P2 A15:8 20 AT89C5132 4173ES–USB–09/07
  • 21. AT89C5132 Figure 6-9. External 8-bit Bus Cycle – Data Write Waveforms ALE TLHLL TLLWL TWLWH TWHLH WR TAVWL TAVLL TLLAX TQVWH TWHQX P0 A7:0 D7:0 Data Out P2 A15:8 6.3.2 External IDE 16-bit Bus Cycles 6.3.2.1 Definition of Symbols Table 9. External IDE 16-bit Bus Cycles Timing Symbol Definitions Signals Conditions A Address H High D Data In L Low L ALE V Valid Q Data Out X No Longer Valid R RD Z Floating W WR 6.3.2.2 Timings Test conditions: capacitive load on all pins = 50 pF. 21 4173ES–USB–09/07
  • 22. Table 10. External IDE 16-bit Bus Cycle – Data Read AC Timings VDD = 2.7 to 3.3V, TA = -40° to +85°C Variable Clock Variable Clock Standard Mode X2 Mode Symbol Parameter Min Max Min Max Unit TCLCL Clock Period 50 50 ns TLHLL ALE Pulse Width 2·TCLCL-15 TCLCL-15 ns TAVLL Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLRL ALE Low to RD Low 3·TCLCL-30 1.5·TCLCL-30 ns TRLRH RD Pulse Width 6·TCLCL-25 3·TCLCL-25 ns TRHLH RD high to ALE High TCLCL-20 TCLCL+20 0.5·TCLCL-20 0.5·TCLCL+20 ns TAVDV Address Valid to Valid Data In 9·TCLCL-65 4.5·TCLCL-65 ns TAVRL Address Valid to RD Low 4·TCLCL-30 2·TCLCL-30 ns TRLDV RD Low to Valid Data 5·TCLCL-30 2.5·TCLCL-30 ns TRLAZ RD Low to Address Float 0 0 ns TRHDX Data Hold After RD High 0 0 ns TRHDZ Instruction Float After RD High 2·TCLCL-25 TCLCL-25 ns Table 11. External IDE 16-bit Bus Cycle – Data Write AC Timings VDD = 2.7 to 3.3V, TA = -40° to +85°C Variable Clock Variable Clock Standard Mode X2 Mode Symbol Parameter Min Max Min Max Unit TCLCL Clock Period 50 50 ns TLHLL ALE Pulse Width 2·TCLCL-15 TCLCL-15 ns TAVLL Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLWL ALE Low to WR Low 3·TCLCL-30 1.5·TCLCL-30 ns TWLWH WR Pulse Width 6·TCLCL-25 3·TCLCL-25 ns TWHLH WR High to ALE High TCLCL-20 TCLCL+20 0.5·TCLCL-20 0.5·TCLCL+20 ns TAVWL Address Valid to WR Low 4·TCLCL-30 2·TCLCL-30 ns TQVWH Data Valid to WR High 7·TCLCL-20 3.5·TCLCL-20 ns TWHQX Data Hold after WR High TCLCL-15 0.5·TCLCL-15 ns 22 AT89C5132 4173ES–USB–09/07
  • 23. AT89C5132 6.3.2.3 Waveforms Figure 6-10. External IDE 16-bit Bus Cycle – Data Read Waveforms ALE TLHLL TLLRL TRLRH TRHLH RD TRLDV TRLAZ TRHDZ TAVLL TLLAX TRHDX P0 A7:0 D7:0 TAVRL Data In TAVDV P2 A15:8 D15:81 Data In Note: D15:8 is written in DAT16H SFR. Figure 6-11. External IDE 16-bit Bus Cycle – Data Write Waveforms ALE TLHLL TLLWL TWLWH TWHLH WR TAVWL TAVLL TLLAX TQVWH TWHQX P0 A7:0 D7:0 Data Out P2 A15:8 D15:81 Data Out Note: D15:8 is the content of DAT16H SFR. 6.3.3 SPI Interface 6.3.3.1 Definition of Symbols Table 12. SPI Interface Timing Symbol Definitions Signals Conditions C Clock H High I Data In L Low O Data Out V Valid X No Longer Valid Z Floating 23 4173ES–USB–09/07
  • 24. 6.3.3.2 Timings Table 13. SPI Interface Master AC Timing VDD = 2.7 to 3.3V, TA = -40° to +85°C Symbol Parameter Min Max Unit Slave Mode TCHCH Clock Period 8 TOSC TCHCX Clock High Time 3.2 TOSC TCLCX Clock Low Time 3.2 TOSC TSLCH, TSLCL SS Low to Clock edge 200 ns TIVCL, TIVCH Input Data Valid to Clock Edge 100 ns TCLIX, TCHIX Input Data Hold after Clock Edge 100 ns TCLOV, TCHOV Output Data Valid after Clock Edge 100 ns TCLOX, TCHOX Output Data Hold Time after Clock Edge 0 ns TCLSH, TCHSH SS High after Clock Edge 0 ns TIVCL, TIVCH Input Data Valid to Clock Edge 100 ns TCLIX, TCHIX Input Data Hold after Clock Edge 100 ns TSLOV SS Low to Output Data Valid 130 ns TSHOX Output Data Hold after SS High 130 ns (1) TSHSL SS High to SS Low TILIH Input Rise Time 2 μs TIHIL Input Fall Time 2 μs TOLOH Output Rise Time 100 ns TOHOL Output Fall Time 100 ns Master Mode TCHCH Clock Period 4 TOSC TCHCX Clock High Time 1.6 TOSC TCLCX Clock Low Time 1.6 TOSC TIVCL, TIVCH Input Data Valid to Clock Edge 50 ns TCLIX, TCHIX Input Data Hold after Clock Edge 50 ns TCLOV, TCHOV Output Data Valid after Clock Edge 65 ns TCLOX, TCHOX Output Data Hold Time after Clock Edge 0 ns TILIH Input Data Rise Time 2 μs TIHIL Input Data Fall Time 2 μs TOLOH Output Data Rise Time 50 ns TOHOL Output Data Fall Time 50 ns Notes: 1. Value of this parameter depends on software. 2. Test conditions: capacitive load on all pins = 100 pF 24 AT89C5132 4173ES–USB–09/07
  • 25. AT89C5132 6.3.3.3 Waveforms Figure 6-12. SPI Slave Waveforms (SSCPHA = 0) SS (input) TSLCH TCLSH TSLCL TCHCH TCHSH TSHSL TCLCH SCK (SSCPOL = 0) (input) TCHCX TCLCX TCHCL SCK (SSCPOL = 1) (input) TCLOV TCLOX TSLOV TCHOX TSHOX TCHOV MISO (output) SLAVE MSB OUT BIT 6 SLAVE LSB OUT 1 TIVCH TCHIX TIVCL TCLIX MOSI (input) MSB IN BIT 6 LSB IN Note: 1. Not Defined but generally the MSB of the character which has just been received. Figure 6-13. SPI Slave Waveforms (SSCPHA = 1) SS1 (output) TCHCH TCLCH SCK (SSCPOL = 0) (output) TCHCX TCLCX TCHCL SCK (SSCPOL = 1) (output) TIVCH TCHIX TIVCL TCLIX SI (input) MSB IN BIT 6 LSB IN TCLOV TCLOX TCHOV TCHOX SO (output) Port Data MSB OUT BIT 6 LSB OUT Port Data Note: 1. Not Defined but generally the LSB of the character which has just been received. 25 4173ES–USB–09/07
  • 26. Figure 6-14. SPI Master Waveforms (SSCPHA = 0) SS1 (input) TSLCH TCLSH TSLCL TCHCH TCHSH TSHSL TCLCH SCK (SSCPOL = 0) (input) TCHCX TCLCX TCHCL SCK (SSCPOL = 1) (input) TCHOV TCHOX TSLOV TCLOV TCLOX TSHOX MISO (output) 1 SLAVE MSB OUT BIT 6 SLAVE LSB OUT TIVCH TCHIX TIVCL TCLIX MOSI MSB IN BIT 6 LSB IN (input) Note: 1. SS handled by software using general purpose port pin. Figure 6-15. SPI Master Waveforms (SSCPHA = 1) SS1 (output) TCHCH TCLCH SCK (SSCPOL = 0) (output) TCHCX TCLCX TCHCL SCK (SSCPOL = 1) (output) TIVCH TCHIX TIVCL TCLIX SI (input) MSB IN BIT 6 LSB IN TCLOV TCLOX TCHOV TCHOX SO (output) Port Data MSB OUT BIT 6 LSB OUT Port Data Note: 1. SS handled by software using general purpose port pin. 6.3.4 Two-wire Interface 6.3.4.1 Timings Table 17. TWI Interface AC Timing 26 AT89C5132 4173ES–USB–09/07
  • 27. AT89C5132 VDD = 2.7 to 3.3 V, TA = -40 to +85°C INPUT OUTPUT Min Min Symbol Parameter Max Max THD; STA Start condition hold time 14·TCLCL(4) 4.0 μs(1) TLOW SCL low time 16·TCLCL(4) 4.7 μs(1) THIGH SCL high time 14·TCLCL(4) 4.0 μs(1) TRC SCL rise time 1 μs -(2) TFC SCL fall time 0.3 μs 0.3 μs(3) TSU; DAT1 Data set-up time 250 ns 20·TCLCL(4)- TRD TSU; DAT2 SDA set-up time (before repeated START condition) 250 ns 1 μs(1) TSU; DAT3 SDA set-up time (before STOP condition) 250 ns 8·TCLCL(4) THD; DAT Data hold time 0 ns 8·TCLCL(4) - TFC TSU; STA Repeated START set-up time 14·TCLCL(4) 4.7 μs(1) TSU; STO STOP condition set-up time 14·TCLCL(4) 4.0 μs(1) TBUF Bus free time 14·TCLCL(4) 4.7 μs(1) TRD SDA rise time 1 μs -(2) TFD SDA fall time 0.3 μs 0.3 μs(3) Notes: 1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 μs. 3. Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered out. Maxi- mum capacitance on bus-lines SDA and SCL= 400 pF. 4. TCLCL= TOSC= one oscillator clock period. 6.3.4.2 Waveforms Figure 6-16. Two Wire Waveforms START or Repeated START condition Repeated START condition START condition STOP condition Tsu;STA Trd SDA 0.7 VDD (INPUT/OUTPUT) 0.3 VDD Tfd Tsu;STO Tbuf Tsu;DAT3 Trc Tfc SCL 0.7 VDD (INPUT/OUTPUT) 0.3 VDD Thd;STA Tlow Thigh Tsu;DAT1 Thd;DAT Tsu;DAT2 27 4173ES–USB–09/07
  • 28. 6.3.5 MMC Interface 6.3.5.1 Definition of Symbols Table 14. MMC Interface Timing Symbol Definitions Signals Conditions C Clock H High D Data In L Low O Data Out V Valid X No Longer Valid 6.3.5.2 Timings Table 15. MMC Interface AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85°C, CL ≤ 100pF (10 cards) Symbol Parameter Min Max Unit TCHCH Clock Period 50 ns TCHCX Clock High Time 10 ns TCLCX Clock Low Time 10 ns TCLCH Clock Rise Time 10 ns TCHCL Clock Fall Time 10 ns TDVCH Input Data Valid to Clock High 3 ns TCHDX Input Data Hold after Clock High 3 ns TCHOX Output Data Hold after Clock High 5 ns TOVCH Output Data Valid to Clock High 5 ns 6.3.5.3 Waveforms Figure 6-17. MMC Input Output Waveforms TCHCH TCHCX TCLCX MCLK TCHCL TCLCH TCHIX TIVCH MCMD Input MDAT Input TCHOX TOVCH MCMD Output MDAT Output 28 AT89C5132 4173ES–USB–09/07
  • 29. AT89C5132 6.3.6 Audio Interface 6.3.6.1 Definition of Symbols Table 16. Audio Interface Timing Symbol Definitions Signals Conditions C Clock H High O Data Out L Low S Data Select V Valid X No Longer Valid 6.3.6.2 Timings Table 17. Audio Interface AC timings VDD = 2.7 to 3.3V, TA = -40 to +85°C, CL ≤ 30pF Symbol Parameter Min Max Unit TCHCH Clock Period 325.5(1) ns TCHCX Clock High Time 30 ns TCLCX Clock Low Time 30 ns TCLCH Clock Rise Time 10 ns TCHCL Clock Fall Time 10 ns TCLSV Clock Low to Select Valid 10 ns TCLOV Clock Low to Data Valid 10 ns Note: 32-bit format with Fs = 48 kHz. 6.3.6.3 Waveforms Figure 6-18. Audio Interface Waveforms TCHCH TCHCX TCLCX DCLK TCHCL TCLCH TCLSV DSEL Right Left TCLOV DDAT 29 4173ES–USB–09/07
  • 30. 6.3.7 Analog to Digital Converter 6.3.7.1 Definition of Symbols Table 18. Analog to Digital Converter Timing Symbol Definitions Signals Conditions C Clock H High E Enable (ADEN bit) L Low Start Conversion S (ADSST bit) 6.3.7.2 Characteristics Table 18. Analog to Digital Converter AC Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85°C Symbol Parameter Min Max Unit TCLCL Clock Period 4 μs TEHSH Start-up Time 4 μs TSHSL Conversion Time 11·TCLCL μs Differential non- DLe 1 LSB linearity error(1)(2) Integral non-linearity ILe 2 LSB errorss(1)(3) OSe Offset error(1)(4) 4 LSB Ge Gain error(1)(5) 4 LSB Notes: 1. AVDD= AVREFP= 3.0 V, AVSS= AVREFN= 0 V. ADC is monotonic with no missing code. 2. The differential non-linearity is the difference between the actual step width and the ideal step width (see Figure 6-20). 3. The integral non-linearity is the peak difference between the center of the actual step and the ideal transfer curve after appropriate adjustment of gain and offset errors (see Figure 6-20). 4. The offset error is the absolute difference between the straight line which fits the actual trans- fer curve (after removing of gain error), and the straight line which fits the ideal transfer curve (see Figure 6-20). 5. The gain error is the relative difference in percent between the straight line which fits the actual transfer curve (after removing of offset error), and the straight line which fits the ideal transfer curve (see Figure 6-20). 30 AT89C5132 4173ES–USB–09/07
  • 31. AT89C5132 6.3.7.3 Waveforms Figure 6-19. Analog-to-Digital Converter Internal Waveforms CLK TCLCL ADEN Bit TEHSH ADSST Bit TSHSL Figure 6-20. Analog-to-Digital Converter Characteristics Code Out Offset Gain Error Error OSe Ge 1023 1022 1021 1020 1019 1018 Ideal Transfer Curve 7 Example of an Actual Transfer Curve 6 5 Center of a Step 4 Integral Non-linearity (ILe) 3 Differential Non-linearity (DLe) 2 1 1 LSB (Ideal) 0 AVIN (LSBideal) 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 Offset Error OSe 31 4173ES–USB–09/07
  • 32. 6.3.8 Flash Memory 6.3.8.1 Definition of Symbols Table 19. Flash Memory Timing Symbol Definitions Signals Conditions S ISP L Low R RST V Valid B FBUSY flag X No Longer Valid 6.3.8.2 Timings Table 20. Flash Memory AC Timing VDD = 2.7 to 3.3V, TA = -40° to +85°C Symbol Parameter Min Typ Max Unit TSVRL Input ISP Valid to RST Edge 50 ns TRLSX Input ISP Hold after RST Edge 50 ns TBHBL FLASH Internal Busy (Programming) Time 10 ms NFCY Number of Flash Write Cycles 100K Cycle TFDR Flash Data Retention Time 10 Year 6.3.8.3 Waveforms Figure 6-21. Flash Memory – ISP Waveforms RST TSVRL TRLSX ISP(1) Note: 1. ISP must be driven through a pull-down resistor (see Section “In-system Programming”, page 18). Figure 6-22. Flash Memory – Internal Busy Waveforms FBUSY bit TBHBL 6.3.9 External Clock Drive and Logic Level References 6.3.9.1 Definition of Symbols Table 21. External Clock Timing Symbol Definitions Signals Conditions C Clock H High L Low X No Longer Valid 32 AT89C5132 4173ES–USB–09/07
  • 33. AT89C5132 6.3.9.2 Timings Table 22. External Clock AC Timings VDD = 2.7 to 3.3V, TA= -40 to +85°C Symbol Parameter Min Max Unit TCLCL Clock Period 50 ns TCHCX High Time 10 ns TCLCX Low Time 10 ns TCLCH Rise Time 3 ns TCHCL Fall Time 3 ns TCR Cyclic Ratio in X2 Mode 40 60 % 6.3.9.3 Waveforms Figure 6-23. External Clock Waveform TCLCH TCHCX VDD - 0.5 VIH1 TCLCX VIL 0.45 V TCHCL TCLCL Figure 6-24. AC Testing Input/Output Waveforms INPUTS OUTPUTS VDD - 0.5 0.7 VDD VIH min 0.3 VDD VIL max 0.45 V Notes: 1. During AC testing, all inputs are driven at VDD -0.5V for a logic 1 and 0.45V for a logic 0. 2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0. Figure 6-25. Float Waveforms VLOAD + 0.1V VOH - 0.1V VLOAD Timing Reference Points VLOAD - 0.1V VOL + 0.1V Note: For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH/VOL level occurs with IOL/IOH = ±20 mA. 33 4173ES–USB–09/07
  • 34. 7. Ordering Information Possible Order Entries(1) Max Memory Size Supply Temperature Frequency Product Part Number (Bytes) Voltage Range (MHz) Package Packing Marking AT89C5132-ROTIL 64K Flash 3V Industrial 40 TQFP80 Tray 895132-IL Industrial & AT89C5132-ROTUL 64K Flash 3V 40 TQFP80 Tray 895132-UL Green Note: 1. PLCC84 package only available for development board. 34 AT89C5132 4173ES–USB–09/07
  • 35. AT89C5132 8. Package Information 8.1 TQFP80 35 4173ES–USB–09/07
  • 36. 8.2 PLCC84 36 AT89C5132 4173ES–USB–09/07
  • 37. AT89C5132 9. Datasheet Revision History for AT89C5132 9.1 Changes from 4173A-08/02 to 4173B-03/04 1. Suppression of ROM product version. 2. Suppression of TQFP64 package. 9.2 Changes from 4173B-03/04 - 4173C - 07/04 1. Add USB connection schematic in USB section. 2. Add USB termination characteristics in DC Characteristics section. 3. Page access mode clarification in Data Memory section. 9.3 Changes from 4173C-07/04 - 4173D - 01/05 1. Interrupt priority number clarification to match number defined by development tools. 9.4 Changes from to 4317D - 01/05 to 4173E - 09/07 1. Added green product ordering information. 2. Removed ‘Preliminary’ status. Product now fully Industrialised. 37 4173ES–USB–09/07
  • 38. Atmel Corporation Atmel Operations 2325 Orchard Parkway Memory RF/Automotive San Jose, CA 95131, USA 2325 Orchard Parkway Theresienstrasse 2 Tel: 1(408) 441-0311 San Jose, CA 95131, USA Postfach 3535 Fax: 1(408) 487-2600 Tel: 1(408) 441-0311 74025 Heilbronn, Germany Fax: 1(408) 436-4314 Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Regional Headquarters Microcontrollers Europe 2325 Orchard Parkway 1150 East Cheyenne Mtn. Blvd. Atmel Sarl San Jose, CA 95131, USA Colorado Springs, CO 80906, USA Route des Arsenaux 41 Tel: 1(408) 441-0311 Tel: 1(719) 576-3300 Case Postale 80 Fax: 1(408) 436-4314 Fax: 1(719) 540-1759 CH-1705 Fribourg Switzerland Biometrics/Imaging/Hi-Rel MPU/ La Chantrerie High Speed Converters/RF Datacom Tel: (41) 26-426-5555 BP 70602 Avenue de Rochepleine Fax: (41) 26-426-5500 44306 Nantes Cedex 3, France BP 123 Asia Tel: (33) 2-40-18-18-18 38521 Saint-Egreve Cedex, France Room 1219 Fax: (33) 2-40-18-19-60 Tel: (33) 4-76-58-30-00 Chinachem Golden Plaza Fax: (33) 4-76-58-34-80 ASIC/ASSP/Smart Cards 77 Mody Road Tsimshatsui Zone Industrielle East Kowloon 13106 Rousset Cedex, France Hong Kong Tel: (33) 4-42-53-60-00 Tel: (852) 2721-9778 Fax: (33) 4-42-53-60-01 Fax: (852) 2722-1369 Japan 1150 East Cheyenne Mtn. Blvd. 9F, Tonetsu Shinkawa Bldg. Colorado Springs, CO 80906, USA 1-24-8 Shinkawa Tel: 1(719) 576-3300 Chuo-ku, Tokyo 104-0033 Fax: 1(719) 540-1759 Japan Tel: (81) 3-3523-3551 Scottish Enterprise Technology Park Fax: (81) 3-3523-7581 Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN- TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically providedot- herwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as compo- nents in applications intended to support or sustain life. ©2007 Atmel Corporation. All rights reserved. Atmel ®, logo and combinations thereof, and Everywhere You Are ® are the trademarks or regis- tered trademarks, of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Printed on recycled paper. 4173ES–USB–09/07