Unleashing the Next Generation Flash Memory Architecture
Unleashing the Next
HyperLink NAND (HLNAND™) Flash
The phenomenal growth of the Flash memory market in recent years has been driven by
consumer-centric applications in mobile handsets, and digital consumer applications such as
digital cameras and media players. For these new consumer-centric applications, flash memory –
especially NAND Flash memory – is a primary enabling technology. As the cost of flash memory
falls, Solid State Drives (SSDs) using Flash memory have become a viable alternative to rotating
magnetic Hard Disk Drives (HDDs).
However, the NAND Flash memory interface and architecture has remained essentially
unchanged since the introduction of NAND Flash memory 15 years ago. The performance
requirements of SSDs cannot be adequately met by the existing NAND Flash interface and
architecture. To meet this challenge, MOSAID is introducing HyperLink NAND (HLNAND™), a
new high-performance NAND Flash memory device that delivers the most advanced capabilities
and cost-effective solution to the flash mass storage market. By meeting the demanding
requirements of future solid state mass storage applications such as SSDs, HLNAND will establish
itself as an industry leading solution in this rapidly growing market.
The Growth of NAND Flash
The flash memory market, and in particular the NAND Flash market, is growing at an impressive
rate. Web-Feet Research projects that by 2011, the NAND flash market will grow to over $41.5
billion in revenue. Figure 1 below presents the flash memory component forecast for both NOR
and NAND through 2011.
Figure 1: Flash Memory NOR and NAND Revenue Forecast, 2005-2011
Source: Web-Feet Research, Inc.
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The flash market is divided into two application groups known as code storage and data storage.
Code storage applications typically require random access to the system’s memory space and are
best served by NOR Flash memory devices. Emerging data storage applications require high read
and write throughput, as well as high density, that are more effectively provided by NAND Flash
The recent expansion of the flash market is being driven by data storage applications employing
NAND Flash. Data storage is further segmented into three key applications; media content
storage using USB flash drives and flash memory cards, embedded applications (mobile handset,
set-top boxes, etc.), and computing with flash cache and SSDs. Solid state drives are emerging as
a hard disk drive replacement due to their light weight, ruggedness, low latency, low power
consumption, and silent operation.
Driven by rapid penetration of notebook market, the total market for SSDs is forecast to reach
almost $14 billion in 2011, consisting of $10.4 billion in revenue from consumer notebook and
desktop PC applications, and almost $3.5 billion in industrial and enterprise applications.
Figure 2: SSD Revenue by Applications, 2005-2011
Source: Web-Feet Research, Inc.
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SSD Performance Trends
SSD performance is forecast to improve at less than 5% per year to 2011, limited by the media
transfer rate (MTR), which represents the number of data transfers per second between the host
controller and the storage media. In contrast, the interface transfer rate (ITR), representing the
number of commands and data transfers per second over the system bus, is expected to increase
by over 12% per annum as the industry migrates from parallel to serial interfaces and fiber
channel. Barring any breakthrough innovations, the gap between the ITR and MTR is expected to
widen and SSD performance will continue to be constrained by the MTR. Figure 3 illustrates the
ITR and MTR trend. MTR represents the aggregate media rate for SSD devices across various
applications including enterprise, industrial, military and PCs for consumer/commercial. ITR is
the aggregate data rate of the interfaces between the host and SSD device; it includes parallel
SCSI, serial attached SCSI, fiber channel, parallel ATA and serial ATA.
Figure 3: SSD MTR and ITR Trend, 2005-2011
Source: Web-Feet Research, Inc.
NAND Flash Memory Trends
As NAND Flash memory capacity continues to increase – doubling every year since 2001 – page
read and program performance have also steadily increased. However, the increase in NAND
flash memory performance has not been enough to close the gap between the MTR and ITR.
The commercial introduction of multi-level cell (MLC) technology has further reduced bit cost
and increased bit density. MLC is becoming main-stream for the vast majority of data storage
applications because it doubles the bit-density compared to devices manufactured with single-
level cell (SLC) technology on the same size die. However, the lower bit cost of MLC technology
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comes at the expense of two to three times slower data throughput, and an order of magnitude
decrease in endurance, compared to SLC technology.
Figure 4: NAND Flash Memory Performance Trends
To meet the need for higher capacity, faster read and programming, higher endurance and longer
retention without increasing cost, SSDs and other emerging applications will require a new device
and system architecture for performance and cost, and a new write scheme for reliability and
HLNAND Flash Memory
HLNAND includes improvements in three key areas:
• the Channel Architecture which defines the physical chip-to-chip interface;
• the Device Architecture which specifies the internal memory bank organization and
• a new Write Scheme enabling increased flexibility along with improved endurance and
The new device architecture and new channel architecture may be applied to any type of memory
including NOR Flash and emerging memory technologies such as Phase-change RAM (PRAM)
to create HLNOR and HLPRAM. Such devices can co-exist in the same memory subsystem as
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Figure 5: HyperLink NAND (HLNAND) Flash
The HyperLink memory architecture is a bank-oriented memory architecture with most
operations being bank- rather than device-oriented. Regardless of whether they are located on the
same device or on different devices, all banks can operate concurrently and completely
independently of each other. This provides the controller with the flexibility to schedule
operations free of unnecessary constraints, and consequently to maximize bus utilization and
The HyperLink channel architecture is based on a ring topology consisting of a variable width
serial data bus that links multiple devices in a daisy-chain fashion. The HyperLink channel, which
originates and terminates at the controller, carries addresses, commands and data in variable
length, serialized packets. The bus width can be dynamically configured from one to eight bits
depending on application requirements.
Figure 6: Controller and HLNAND Devices on HyperLink Ring
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Two types of packets travel around the packet-oriented HyperLink ring. Command and Write
Data Packets contain a command, optionally an address, and optionally some write data. Read
Data Packets contain read data heading back to the controller from a given device on the ring.
Because all the connections are point-to-point, the speed of the interface remains the same
regardless of how many memory devices are connected. The system-level Link architecture
capitalizes on the unique characteristics of the HLNAND device by linking a large number of
banks in a daisy-chain cascade. HLNAND supports up to 255 devices with no performance
degradation at up to 800MB/s per ring.
The flexibility to allow different types and densities of memories to be populated on the ring and
controlled by a single controller, results from the fact that the HyperLink channel architecture,
which defines the memory device interface, is independent of the architecture and technology of
the memory device’s core. Provided the HyperLink channel’s architectural requirements are met,
the core of a given device may be different from those of other devices on the ring.
In flash memory, individual bits must be erased before they can be re-written or programmed. In
conventional flash memory there is a mismatch between erase, which is done at the block level,
and program, which is done on a page basis. HLNAND incorporates a new write scheme to
address this mismatch, at the same time reducing stress for enhanced endurance and reliability.
The new write scheme includes unique features such as page erase, multi-page/block erase,
partial block erase, and random page program operations with a novel stress-free program
Support for unique page erase, partial block erase, and random page program capabilities
provides uniform read and write operations and dramatically reduces page copy overhead for
wear-leveling, while enhancing overall system endurance by 30%. The novel stress-free program
scheme minimizes cell Vth shift in unselected pages and results in higher reliability. The stress-
free program scheme also allows operation at significantly lower supply voltage for reduced
power. Cost reductions are achieved through the low pin count with the new architecture resulting
in a 5-10% die size reduction.
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The shift in the memory industry towards consumer computing-based products and a growing
demand for NAND-based mass storage media for data storage applications has placed pressure on
producers to develop innovations that deliver significant performance and capacity
improvements, along with reductions in overall system cost.
HLNAND Flash is a revolutionary advancement that overcomes these challenges by delivering:
• High read and write bandwidth of up to 800MB/s per ring while using existing NAND Flash
• Simpler system integration than is currently possible, using fewer pins with the advantages of
a multi-bit serial interface
• High memory expandability of up to 255 devices using daisy-chain cascade with point-to-
• Lower cost structure with a rich feature set compared to conventional NAND Flash
• High speed writes to both SLC and MLC NAND without degradation in write speed to MLC
NAND, by efficiently hiding internal core operations in the flash memory system
• Symmetrical read and write speeds, reducing system overhead
• SSD read and write interface access speeds and media throughput using HLNAND vastly
• Greatly improved reliability
• Enhances program and erase endurance by at least 30%
• Low power consumption
HLNAND Flash is a next generation flash memory device that delivers the most advanced
capabilities and cost-effective solution to the flash mass storage market. These advantages will
enable HLNAND Flash to establish itself as an industry leading solution in this rapidly growing
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