TOWARDS SYSTEM-ON-A-CHIP DESIGN OF HIGH-SPEED DATA ACQUISITION SYSTEMS TU-Delft, 2003 Angel Popov Angel Popov Technical University of Sofia e-mail: email@example.com http://www.tu-sofia.acad.bg/saer/staff/anjo/anjopopov.htm “ The principal applications of any sufficiently new and innovative technology always have been and will continue to be applications created by that new technology” … In other words, if we are going to make something truly new, we won’t know what to do with it until after we’ve brought it into being… “ T he Futility of Predicting Applications” Herbert Kroemer, 2000 Nobel laureate
TOWARDS SYSTEM-ON-A-CHIP DESIGN OF HIGH-SPEED DATA ACQUISITION SYSTEMS TU-Delft, 2003 Angel Popov 1 INTRODUCTION 2 DESIGN CONSIDERATIONS 3 ANALOG-TO-DIGITAL CONVERTER 4 MEMORY 5 TEST 6 CONCLUSIONS REFERENCES
INTRODUCTION TU-Delft, 2003 Angel Popov “ We define a System-on-a-Chip as an IC, designed by stitching together multiple stand-alone VLSI designs to provide full functionality for an application”[Rajsuman]. Fig.1. High-speed data acquisition system
SoC - concept that integrates pre-designed, reusable components, the so called Intellectual Property (IP) cores.
The pure digital SoC seems facile - a “Mouse Aided Design”. But analog, RF and mixed signal cores still are:
not easy portable
could cause a wide range of problems in terms of compatibility, power consumption, noise emissions and immunity, area etc.
The asynchronous parallel ADC has advantages in terms of power saving and noise immunity in comparison to the synchronous parallel (flash) ADC.
An analytical expression of power dissipation with respect to memory capacity and working frequency is obtained. By this means it is possible to keep power constraint at maximal rate and memory size.
RAM–based FIFO memory is very convenient for data transfer to the computer. It allows efficient use of the memory space when the sampling frequency of ADC is commensurable to the transfer rate (as is often the case);
A circuit for on–line testing of the ADC and memory requires a very small area overhead and only three additional pins.
TOWARDS SYSTEM-ON-A-CHIP DESIGN OF HIGH-SPEED DATA ACQUISITION SYSTEMS TU-Delft, 2003 Angel Popov Appendix A: Dynamic Hysteresis 1 Synthesis 2 Manova D. and A. Popov, CMOS Comparators for Asynchronous Parallel Analog - to - Digital Converters, Proc. of the Tenth International Conference Electronics 2001, September 26-28, 2001, Sozopol, Bulgaria, book 2, pp.121-125. 3 G. Panov, D. Manova and A. Popov, Comparator with dynamic hysteresis, Electronics Letters, 2 nd September 1999, Vol. 35, No. 18, pp. 1497-1498. Appendix B: 1 Hristov Hr., D. Manova, A. Popov, A Cell-Based Approach to Parallel A/D Converter Design, Proceedings of the International Scientific Conference on Energy and Information Systems and Technologies - EIST - 2001, Bitola, Macedonia, June 7-8, 2001, vol. III, pp. 638-642.