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  • accepted and to appear in the RTCSA 2007 Thanks for Chair’s introduction. We all know that NOR flash memory is usually used to store the code of programs while NAND flash is usually used to store data. However, NAND flash memory is much cheaper than NOR, but its read performance is worse than NOR flash memory. This observation motives our research. This work is to fill up the performance gap between NAND and NOR while using NAND to replace NOR to store the code of programs.
  • accepted and to appear in the RTCSA 2007
  • accepted and to appear in the RTCSA 2007
  • accepted and to appear in the RTCSA 2007
  • accepted and to appear in the RTCSA 2007
  • accepted and to appear in the RTCSA 2007
  • accepted and to appear in the RTCSA 2007
  • accepted and to appear in the RTCSA 2007

slides Presentation Transcript

  • 1. A NOR Emulation Strategy over NAND Flash Memory Jian-Hong Lin, Yuan-Hao Chang , Jen-Wei Hsieh, and Tei-Wei Kuo Embedded Systems and Wireless Networking Laboratory Dept. of Computer Science and Information Engineering National Taiwan University Taipei, Taiwan
  • 2. Agenda
    • Research Motivation
    • An Efficient Prediction Mechanism
    • Performance Evaluation
    • Conclusion
    April 15, 2010 Copyright © All Rights Reserved by Jian-Hong Lin
  • 3. Comparison between NAND and NOR April 15, 2010 Copyright © All Rights Reserved by Jian-Hong Lin NOR SLC NAND (large-block, 2KB-page) Access Method Random Sequential Access Speed Read: 23.84 MB/sec Write: 0.07 MB/sec Erase: 0.22 MB/sec Read: 15.33 MB/sec Write: 4.57 MB/sec Erase: 6.25 MB/sec Density Low High Price High (34.55 $/GB) Low (6.79 $/GB) Application
    • Code storage
    • low-end mobile handsets
    • PC BIOS chips
    • Data storage
    • MP3 player (music storage)
    • Digital Cameras (image storage)
  • 4. Motivation
    • Replace NOR with NAND for code storage
    • Challenge:
      • How to fill up the performance gap between NAND and NOR?
        • Use SRAM for data caching
        • Prediction scheme
        • Implementation design
    April 15, 2010 Copyright © All Rights Reserved by Jian-Hong Lin
  • 5. A Prediction-based Prefetching Strategy
    • An Example Scenario
    April 15, 2010 Copyright © All Rights Reserved by Jian-Hong Lin Offline: Traces analysis 1. Online: Prefetch the data based on the prediction information 2.
  • 6. The System Architecture April 15, 2010 Copyright © All Rights Reserved by Jian-Hong Lin Cache for data access Communication with the host system For code and data storage Address translation from byte addressing to LBA addressing Prefetch data from NAND to SRAM based on prediction info.
  • 7. A Prediction Graph
    • A prediction graph
      • An Illustration of the access patterns (a sequence of LBA’s)
      • One node for each LBA in the graph
    April 15, 2010 Copyright © All Rights Reserved by Jian-Hong Lin seq i … 1000, 1001, 1002, 1003, 740, … seq j … 1000, 1001, 345, 346, 347, … e.g. 1000 1001 1002 1003 740 345 346 347 Branch node Regular node branch node
  • 8. An Implementation
    • The Way to Save the Prediction Graph in the Flash Memory
    • The Spare Area Usage of Nodes
      • 1. Regular Nodes (Subsequent LBA Information)
    April 15, 2010 Copyright © All Rights Reserved by Jian-Hong Lin spare area ! small block: 16 bytes large block: 64 bytes
  • 9. An Implementation (cont.)
      • 2. Branch Nodes (Assisted by a B ranch Table )
    April 15, 2010 Copyright © All Rights Reserved by Jian-Hong Lin addr(b1) addr(b2) addr(b3) An example
  • 10. A Prefetch Procedure
    • The Objective: The Probability Maximization of Data Accesses over SRAM
    • Cyclic Buffer with Two indices: current and next
    • A Greedy Algorithm in the Prefetch Procedure
      • Regular Node  Prefetching of its Subsequent LBA
      • Branch Node  Prefetching of all Possible Following LBA Links in a Round-Robin Way
    • Stop Conditions
      • next reaches a branch node again along a link.
      • next and current point to the same page.
      • The caching buffer is full.
    April 15, 2010 Copyright © All Rights Reserved by Jian-Hong Lin … … … meet a branch node again!
  • 11. A Prefetch Procedure April 15, 2010 Copyright © All Rights Reserved by Jian-Hong Lin 1 2 3 4 5 1 6 current next the cache Prediction graph An Example
  • 12. Snapshots of the Access Patterns April 15, 2010 Copyright © All Rights Reserved by Jian-Hong Lin AOE II TTD Raiden RANDOM ACCESS! BURST READ!
  • 13. Performance Metrics and Experiment Setup
    • Performance metrics
      • Read performance
      • Cache miss rate
      • Main-memory requirement
    • Experiment setup
      • Large-block NAND flash memory:
        • Setup time (random access): 25 us/page
        • Serial access time: 50 ns/byte
      • SRAM
        • 10 ns/byte
      • NOR flash memory
        • 40 ns/byte
    April 15, 2010 Copyright © All Rights Reserved by Jian-Hong Lin
  • 14. Read Performance April 15, 2010 Copyright © All Rights Reserved by Jian-Hong Lin saturate at 4KB
  • 15. Conclusion
    • An Application-Oriented Approach to Replace NOR with NAND
      • Prefetching of data from NAND based on the trace analysis
      • Limited SRAM requirement
      • Good performance, but the results depending on the predictability of the applications
    • Performance Improvement and Overhead Evaluation
      • Read performance better than that of NOR:
        • AOE II: 24%
        • TTD: 216%
        • Raiden: 298%
      • Cache miss rate:
        • Lower than 10% in most cases
    April 15, 2010 Copyright © All Rights Reserved by Jian-Hong Lin