SemiMem_lec1.ppt
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SemiMem_lec1.ppt Presentation Transcript

  • 1. Semiconductor Memories Lecture 1: May 10, 2006 EE Summer Camp Abhinav Agarwal
  • 2. Outline
    • Concept/need of memory
    • Parameters
    • Types/classification
    • Basic features
    • Basic Cell circuits
    • Peripheral circuitry
  • 3. Concept
    • Data storage essential for processing
    • Binary storage
    • Switches
    • How do you implement this in Hardware?
  • 4. Requirements
    • Easy reading
    • Easy Writing
    • High density
    • Speed, more speed and still more speed
  • 5. Memory Chip Configuration
  • 6. Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory EPROM E 2 PROM FLASH Random Access Non-Random Access SRAM DRAM Mask-Programmed Programmable (PROM) FIFO Shift Register CAM LIFO
  • 7. RAM
    • Random write and read operation for any cell
    • Volatile data
    • Most of computer memory
    • DRAM
      • Low Cost
      • High Density
      • Medium Speed
    • SRAM
      • High Speed
      • Ease of use
      • Medium Cost
  • 8. ROM
    • Non-volatile Data
    • Method of Data Writing
    • Mask ROM
      • Data written during chip fabrication
    • PROM
      • Fuse ROM: Non-rewritable
      • EPROM: Erase data by UV rays
      • EEPROM: Erase and write through electrical means
        • Speed 2-3 times slower than RAM
        • Upper limit on write operations
        • Flash Memory – High density, Low Cost
  • 9. Basic Cells
    • DRAM
    • SRAM
  • 10. Static CAM Memory Cell ••• ••• CAM Bit Word Bit ••• CAM Bit Bit CAM Word Wired-NOR Match Line Match M1 M2 M7 M6 M4 M5 M8 M9 M3 int S Word ••• CAM Bit Bit S
  • 11. CAM in Cache Memory Address Decoder Hit Logic CAM ARRAY Input Drivers Tag Hit Address SRAM ARRAY Sense Amps / Input Drivers Data R/W
  • 12. ROM
    • Fuse ROM
    • EEPROM
    Floating Gate
  • 13. MOS NAND ROM All word lines high by default with exception of selected row WL [0] WL [1] WL [2] WL [3] V DD Pull-up devices BL [3] BL [2] BL [1] BL [0]
  • 14. Non-Volatile Memories The Floating-gate transistor (FAMOS) Floating gate Source Substrate Gate Drain n + n +_ p t ox t ox Device cross-section Schematic symbol G S D
  • 15. Floating-Gate Transistor Programming 0 V - 5 V 0 V D S Removing programming voltage leaves charge trapped 5 V - 2.5 V 5 V D S Programming results in higher V T . 20 V 10 V 5 V 20 V D S Avalanche injection
  • 16. A “Programmable-Threshold” Transistor
  • 17. Periphery
    • Decoders
    • Sense Amplifiers
    • Input/Output Buffers
    • Control / Timing Circuitry
  • 18. Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder
  • 19. Hierarchical Decoders • • • • • • A 2 A 2 A 2 A 3 WL 0 A 2 A 3 A 2 A 3 A 2 A 3 A 3 A 3 A 0 A 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 1 A 1 WL 1 Multi-stage implementation improves performance NAND decoder using 2-input pre-decoders
  • 20. Sense Amplifiers Idea: Use Sense Amplifer output input s.a. small transition t p C  V  I av ---------------- = make  V as small as possible small large
  • 21. Sense Amp Operation D V (1) V (1) V (0) t V PRE V BL Sense amp activated Word line activated
  • 22. Differential Sense Amplifier Directly applicable to SRAMs M 4 M 1 M 5 M 3 M 2 V DD bit bit SE Out y
  • 23. Reliability and Yield
  • 24. References
    • Digital Integrated Circuits, 2 nd Edition, Jan Rabaey, Anantha Chandrakasan, Borivoje Nikolic
    • Chapter 12 http://bwrc.eecs.berkeley.edu/IcBook/slides.htm
    • Sedra & Smith, Microelectronic Circuits, 4 th Edition, Chapter 13
      • Section 13.9, 13.10, 13.11, 13.12
    • VLSI Memory Chip Design, Kiyoo Itoh