SemiMem_lec1.ppt

503 views
407 views

Published on

0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total views
503
On SlideShare
0
From Embeds
0
Number of Embeds
9
Actions
Shares
0
Downloads
15
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide

SemiMem_lec1.ppt

  1. 1. Semiconductor Memories Lecture 1: May 10, 2006 EE Summer Camp Abhinav Agarwal
  2. 2. Outline <ul><li>Concept/need of memory </li></ul><ul><li>Parameters </li></ul><ul><li>Types/classification </li></ul><ul><li>Basic features </li></ul><ul><li>Basic Cell circuits </li></ul><ul><li>Peripheral circuitry </li></ul>
  3. 3. Concept <ul><li>Data storage essential for processing </li></ul><ul><li>Binary storage </li></ul><ul><li>Switches </li></ul><ul><li>How do you implement this in Hardware? </li></ul>
  4. 4. Requirements <ul><li>Easy reading </li></ul><ul><li>Easy Writing </li></ul><ul><li>High density </li></ul><ul><li>Speed, more speed and still more speed </li></ul>
  5. 5. Memory Chip Configuration
  6. 6. Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory EPROM E 2 PROM FLASH Random Access Non-Random Access SRAM DRAM Mask-Programmed Programmable (PROM) FIFO Shift Register CAM LIFO
  7. 7. RAM <ul><li>Random write and read operation for any cell </li></ul><ul><li>Volatile data </li></ul><ul><li>Most of computer memory </li></ul><ul><li>DRAM </li></ul><ul><ul><li>Low Cost </li></ul></ul><ul><ul><li>High Density </li></ul></ul><ul><ul><li>Medium Speed </li></ul></ul><ul><li>SRAM </li></ul><ul><ul><li>High Speed </li></ul></ul><ul><ul><li>Ease of use </li></ul></ul><ul><ul><li>Medium Cost </li></ul></ul>
  8. 8. ROM <ul><li>Non-volatile Data </li></ul><ul><li>Method of Data Writing </li></ul><ul><li>Mask ROM </li></ul><ul><ul><li>Data written during chip fabrication </li></ul></ul><ul><li>PROM </li></ul><ul><ul><li>Fuse ROM: Non-rewritable </li></ul></ul><ul><ul><li>EPROM: Erase data by UV rays </li></ul></ul><ul><ul><li>EEPROM: Erase and write through electrical means </li></ul></ul><ul><ul><ul><li>Speed 2-3 times slower than RAM </li></ul></ul></ul><ul><ul><ul><li>Upper limit on write operations </li></ul></ul></ul><ul><ul><ul><li>Flash Memory – High density, Low Cost </li></ul></ul></ul>
  9. 9. Basic Cells <ul><li>DRAM </li></ul><ul><li>SRAM </li></ul>
  10. 10. Static CAM Memory Cell ••• ••• CAM Bit Word Bit ••• CAM Bit Bit CAM Word Wired-NOR Match Line Match M1 M2 M7 M6 M4 M5 M8 M9 M3 int S Word ••• CAM Bit Bit S
  11. 11. CAM in Cache Memory Address Decoder Hit Logic CAM ARRAY Input Drivers Tag Hit Address SRAM ARRAY Sense Amps / Input Drivers Data R/W
  12. 12. ROM <ul><li>Fuse ROM </li></ul><ul><li>EEPROM </li></ul>Floating Gate
  13. 13. MOS NAND ROM All word lines high by default with exception of selected row WL [0] WL [1] WL [2] WL [3] V DD Pull-up devices BL [3] BL [2] BL [1] BL [0]
  14. 14. Non-Volatile Memories The Floating-gate transistor (FAMOS) Floating gate Source Substrate Gate Drain n + n +_ p t ox t ox Device cross-section Schematic symbol G S D
  15. 15. Floating-Gate Transistor Programming 0 V - 5 V 0 V D S Removing programming voltage leaves charge trapped 5 V - 2.5 V 5 V D S Programming results in higher V T . 20 V 10 V 5 V 20 V D S Avalanche injection
  16. 16. A “Programmable-Threshold” Transistor
  17. 17. Periphery <ul><li>Decoders </li></ul><ul><li>Sense Amplifiers </li></ul><ul><li>Input/Output Buffers </li></ul><ul><li>Control / Timing Circuitry </li></ul>
  18. 18. Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder
  19. 19. Hierarchical Decoders • • • • • • A 2 A 2 A 2 A 3 WL 0 A 2 A 3 A 2 A 3 A 2 A 3 A 3 A 3 A 0 A 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 1 A 1 WL 1 Multi-stage implementation improves performance NAND decoder using 2-input pre-decoders
  20. 20. Sense Amplifiers Idea: Use Sense Amplifer output input s.a. small transition t p C  V  I av ---------------- = make  V as small as possible small large
  21. 21. Sense Amp Operation D V (1) V (1) V (0) t V PRE V BL Sense amp activated Word line activated
  22. 22. Differential Sense Amplifier Directly applicable to SRAMs M 4 M 1 M 5 M 3 M 2 V DD bit bit SE Out y
  23. 23. Reliability and Yield
  24. 24. References <ul><li>Digital Integrated Circuits, 2 nd Edition, Jan Rabaey, Anantha Chandrakasan, Borivoje Nikolic </li></ul><ul><li>Chapter 12 http://bwrc.eecs.berkeley.edu/IcBook/slides.htm </li></ul><ul><li>Sedra & Smith, Microelectronic Circuits, 4 th Edition, Chapter 13 </li></ul><ul><ul><li>Section 13.9, 13.10, 13.11, 13.12 </li></ul></ul><ul><li>VLSI Memory Chip Design, Kiyoo Itoh </li></ul>

×