RD1017 - Serial Flash Boot Controller for FPGA

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RD1017 - Serial Flash Boot Controller for FPGA

  1. 1. Using a Lattice CPLD and Flash Memory to Configure an SRAM-Based FPGA October 2003 Reference Design RD1017 Introduction SRAM-based FPGA devices are volatile and require reconfiguration on power-up cycles. FPGA external configura- tion data must be held on a non-volatile device. For systems incorporating a microprocessor or host computer sys- tem, configuration data may be stored on a system’s local hard drive with a host-run application used to configure the FPGA. Similarly, a system may employ a microcontroller that could take on the responsibility of this task, retrieving the data from an on-board ROM or Flash memory. The microcontroller may use the same ROM or Flash memory to boot or hold data, reducing the Flash memory’s ability to store FPGA configuration data. However, on systems that require “quick“ configurations, or systems that do not have microprocessor resources readily avail- able, a dedicated serial PROM may be used. To accommodate a large FPGA or multiple FPGA devices, the serial PROM must be large. Alternately, a designer could use multiple serial PROMs in a daisy-chain fashion, which is a costly and space inefficient solution. An alternative solution uses an inexpensive CPLD and Flash memory (Figure 1). The large memory capacity of Flash memories permits a wide choice of Flash devices for configuring one or more FPGA devices. Flash memo- ries are available in sizes from 4 Mbits to 16 Mbits in a standard 40-pin TSOP and as large as 64 Mbits using a standard 48-pin TSOP device. One drawback of using a Flash memory is that it does not support serial download or JTAG programming like a serial PROM. Using a Lattice CPLD as the intermediate device for serializing the Flash memory to the FPGA and the CPLD Boundary Scan ring to program the Flash can make the Flash a better solution than multiple serial PROMs. Figure 1 shows a block diagram of the CPLD, Flash and ORCA® FPGA device as described in the reference design. This application note describes how a Lattice CPLD and Flash can work together to support FPGA configuration and how the Boundary Scan chain can be used to program the Flash using the standard IEEE 1149.1 interface of the Lattice CPLD. Figure 1. Master Serial PROM Emulation by a Flash and CPLD To Daisy Chained A[n:0] CCLK Devices DOUT DIN D[7:0] ORCA Vcc FPGA CPLD FLASH (Master) RESET# DONE WE# PRGM OE# CE# PROM Emulation 4 M_PRGM JTAG M_RESET Configuring an ORCA FPGA Configuration can be done at any time on an ORCA FPGA device. The ORCA FPGA supports several options for configuration, which can be broken down into two categories: Master and Slave. In Master mode the FPGA pro- vides a configuration clock CCLK and signaling to an external memory to “Read” its contents. In Slave mode, an external device must provide the configuration clock and data to the FPGA. For both Master and Slave mode, the device can be configured to accept parallel or serial data. Dedicated mode pins (M0, M1, M2, M3) on the ORCA www.latticesemi.com 1 rd1017_01
  2. 2. Using a Lattice CPLD and Flash Memory Lattice Semiconductor to Configure an SRAM-Based FPGA device determine the configuration mode for the FPGA at power up. Table 1 outlines the mode pins for the ORCA 4 device family and the Configuration Mode selected. The Flash Memory Controller uses Master Serial Mode. Master Serial Mode In the Master Serial Mode the FPGA loads its configuration data automatically from an external ROM on power up or after the PROGRAM pin is toggled. The ORCA FPGA provides signaling to the serial PROM. The ORCA FPGA device has five pins associated with configuration: INIT, PRGM, CCLK, DIN and DONE. If there are daisy chained ORCA devices, DOUT is used. In Master Serial Mode, the FPGA drives INIT pin low during a configuration cycle if there is an error. The DONE pin will drive high on the completion of a successful configuration. Table 1. Configuration Modes of the ORCA 4 FPGA Configuration Mode M3 M2 M1 M0 CCLK Data Master Serial 0 0 0 0 Output 10 MHz Serial Master Parallel 0 1 0 0 Output 10 MHz 8-bit Asynchronous Peripheral 0 1 0 1 Output 10 MHz 8-bit Maser Serial 1 0 0 0 Output 1.25 MHz Serial Slave Parallel 1 0 0 1 Input 8-bit MPI 8-bit 1 0 1 0 Output 8-bit MPI 16-bit 1 0 1 1 Output 16-bit Master Parallel 1 1 0 0 Output 1.25 MHz 8-bit Asynchronous Peripheral 1 1 0 1 Output 1.25 MHz 8-bit MPI 32-bit 1 1 1 0 Output 32-bit Slave Serial 1 1 1 1 Input Serial Power Up On power up, the ORCA FPGA device can be configured automatically. While the power is ramping up on the ORCA device, a power-on-reset is triggered, the Mode pins are sampled to set the I/Os based on the Configuration Mode, the DONE and INIT pins are driven low and the internal RAM cleared. Once the ORCA device power supply reaches between 2.7V to 3V, a time-out delay is initiated to let the power supply settle. The INIT pin (INIT is an open drain pin) is released and must be pulled up externally to allow the start of the CCLK. In Master Mode, the ORCA device remains in the initialization state an additional six internal clock cycles after INIT goes high to ensure that any daisy chained devices have a chance to clear. Using a CPLD and Flash Memory By incorporating a small inexpensive CPLD and a Flash Memory a designer can construct a circuit that emulates the serial PROM. Figure shows a block diagram for the CPLD and Flash emulation. The INIT pin from the ORCA FPGA holds the CPLD and Flash in a reset state until it is ready to be configured. When the FPGA releases the INIT pin, the clock CCLK will start shortly there after. Internally, the CPLD uses a counter to generate addresses to the Flash and control the multiplexer select lines. The CPLD gates the data from the Flash Memory multiplexer to the DIN of the FPGA on the rising edge of the CCLK. The counter changes the address of the Flash on the falling edge of CCLK. Configuration time using the CPLD/Flash Loader solution will depend on the address valid to data out valid specifi- cation of the Flash memory chosen. Using a Flash memory with large address to data out valid specification (>30 ns) requires a Master CCLK of 1.25 MHz. 2
  3. 3. Using a Lattice CPLD and Flash Memory Lattice Semiconductor to Configure an SRAM-Based FPGA Figure 2. Flash Controller Block Diagram D(0) DATA Q D Dout CLR D(7) Q(0) Counter Q(1) Q(2) Q(3) A(0) ADDR CLK Q(n + 3) A(n) M_PRGM CLR WE# RESET# M_RESET OE# DONE CE# CPLD FLASH Programming the Flash Unlike serial PROMs, which can be reprogrammed in-circuit via IEEE 1149.1 compliant JTAG programming tools, standard Flash memories do not support JTAG programming. The CPLD reference design, in order to provide greater capability, must provide a method for updating the Flash memory device while the Flash memory device is still in-circuit. The CPLD reference design does not provide a direct method of reprogramming the attached Flash memory device. Instead the Boundary Scan cells of the CPLD will be used to program the Flash device. Many JTAG tester companies support Flash memory programming through the Boundary Scan ring of a host device. Note: Lattice support for Flash programming through the CPLD JTAG port using ispVM™ software is scheduled for release in early 2004. For alternatives and software schedule, please contact Lattice Techni- cal support at 1-800-LATTICE or e-mail techsupport@latticesemi.com. Support of Flash programming by Lattice’s ispVM System software will allow a unified programming environment through a single JTAG port. The ispVM System software will take a bitstream file for the ORCA 4 FPGA and convert it into a set of vectors for controlling the CPLD boundary scan chain. The boundary scan chain will toggle the Flash memory device’s address, data, and control signals. During this mode of operation, the Flash memory WE signal will be toggled. When the Flash memory is not being programmed, the WE signal is pulled inactive by the CPLD logic. The vectors written to the boundary scan chain emulate the Flash memory’s programming sequence. The software supports flexible pin layout and either Intel or AMD Flash memories. Please see ispVM System software for more information. Implementation The Flash memory controller reference design is implemented in VHDL using Lattice’s ispLEVER® design soft- ware. The targeted device is the ispMACH™ 4000 family. The design fits in an ispMACH 4032 48-pin TQFP device when being used with small Flash memory devices. If larger memories are needed, then the ispMACH 4064 in the 100-pin TQFP package is required due to the larger pin count for the address lines to the Flash memory. The VHDL code is designed with a VHDL generic call that allows the user to specify the number of address bits to be used in the design. The VHDL code can then be compiled using the ispLEVER design software to obtain a routed CPLD solution. 3
  4. 4. Using a Lattice CPLD and Flash Memory Lattice Semiconductor to Configure an SRAM-Based FPGA Flash Memory The CCLK is generated by the FPGA and can have a period as long 1600 ns for the slow Master Serial Mode and as fast as 60 ns for the fast Master Serial Mode. The critical timing path in the design is the availability of data to meet the 10 ns setup requirement (ORCA 4 Master Serial Mode timing specification) for the next rising edge of CCLK. For Fast Master Slave Mode, the designer must ensure that: CCLK -> out (CPLD Counter) + Address valid (Flash) + tMUX (CPLD) + tSU (FPGA) ≤ 60 ns With the 10 ns setup time requirement, the delay through the CPLD is on the order of 20 ns which leaves an access time of less than 30 ns. Most standard Flash memories do not operate fast enough to meet the timing requirement if the Fast Master Serial Mode is used on the ORCA 4 FPGA. The timing requires that the configuration mode for the ORCA 4 FPGA use Slow Master Serial Mode or M[3:0] = [1000]. Further Reading The following are useful documents for this reference design: • Lattice ORCA Series 4 FPGA Data Sheet • Lattice Technical Note TN1013, ORCA Series 4 FPGA Configuration • AMD Flash Data Sheet • Intel Flash Data Sheet Technical Support Assistance Hotline: 1-800-LATTICE (Domestic) 1-408-826-6002 (International) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com 4

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