INTEGRATED CIRCUITS




                              PXA-G49
                       Flash Memory
                      Mi...
Philips Semiconductors


  PXA-G49 Parallel Programming Specification                                                 PXA-...
Philips Semiconductors


  PXA-G49 Parallel Programming Specification                                                PXA-G...
Philips Semiconductors


  PXA-G49 Parallel Programming Specification                                                     ...
Philips Semiconductors


  PXA-G49 Parallel Programming Specification                                                     ...
Philips Semiconductors


  PXA-G49 Parallel Programming Specification                                                     ...
Philips Semiconductors


    PXA-G49 Parallel Programming Specification                                                   ...
Philips Semiconductors


  PXA-G49 Parallel Programming Specification                                                     ...
Philips Semiconductors


  PXA-G49 Parallel Programming Specification                                                     ...
Philips Semiconductors


  PXA-G49 Parallel Programming Specification                                                     ...
Philips Semiconductors


  PXA-G49 Parallel Programming Specification                                                     ...
Philips Semiconductors


  PXA-G49 Parallel Programming Specification                                                     ...
Philips Semiconductors


  PXA-G49 Parallel Programming Specification                                                     ...
Philips Semiconductors


  PXA-G49 Parallel Programming Specification                                            PXA-G49

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Philips Semiconductors


  PXA-G49 Parallel Programming Specification                                           PXA-G49

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Philips Semiconductors


  PXA-G49 Parallel Programming Specification                                               PXA-G4...
Philips Semiconductors


  PXA-G49 Parallel Programming Specification                                       PXA-G49

Flash...
Philips Semiconductors


  PXA-G49 Parallel Programming Specification                                         PXA-G49




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Philips Semiconductors


  PXA-G49 Parallel Programming Specification                                                     ...
Philips Semiconductors


   PXA-G49 Parallel Programming Specification                                                    ...
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PXA-G49 Flash Memory Microcontroller Parallel Program/Erase ...

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PXA-G49 Flash Memory Microcontroller Parallel Program/Erase ...

  1. 1. INTEGRATED CIRCUITS PXA-G49 Flash Memory Microcontroller Parallel Program/Erase Specifications ATTENTION ALL USERS OF THIS DOCUMENT: ON FIGURE 7: THREE ADDITIONAL ERASE PULSES ADDED 7/19/00. Your programming algorithms must be modified to accommodate this change. 2000 Jul 27 Philips Semiconductors PHILIPS
  2. 2. Philips Semiconductors PXA-G49 Parallel Programming Specification PXA-G49 NAME DURING FUNCTION DURING PLCC LQFP PIN NAME I/O PROGRAMMING. PROGRAMMING 1 39 VSS P Ground 2 40 P1.0 A0 I Address input 3 41 P1.1 A1 I Address input 4 42 P1.2 A2 I Address input 5 43 P1.3 A3 I Address input 6 44 P1.4 A4 I Address input 7 1 P1.5 A5 I Address input 8 2 P1.6 A6 I Address input 9 3 P1.7 A7 I Address input 10 4 RST RST=0 I Reset always connected to Low 11 5 P3.0 MODE0 Mode select 12 6 N.C. 13 7 P3.1 MODE1 Mode select 14 8 P3.2 15 9 P3.3 CE Chip Select 16 10 P3.4 A14 I Address input 17 11 P3.5 A15 I Address input 18 12 P3.6 19 13 P3.7 MODE2 I Mode select 20 14 XTAL2 XTAL2 O Clock out 21 15 XTAL1 XTAL1 I Clock in 22 16 VSS VSS P Ground 23 17 VDD VDD P +5V 24 18 P2.0 A8 I Address input 25 19 P2.1 A9 I Address input 26 20 P2.2 A10 I Address input 27 21 P2.3 A11 I Address input 28 22 P2.4 A12 I Address input 29 23 P2.5 A13 I Address input 30 24 P2.6 MODE3 I Mode select 31 25 P2.7 OE I Output Enable 32 26 PSEN PSEN=0 I PSEN always connected to Low 33 27 ALE WR I Write 34 28 N.C. 35 29 EA/VPP/WAIT VPP/VIH 12V 36 30 P0.7 D7 I/O Data 37 31 P0.6 D6 I/O Data 38 32 P0.5 D5 I/O Data 39 33 P0.4 D4 I/O Data 40 34 P0.3 D3 I/O Data 41 35 P0.2 D2 I/O Data 42 36 P0.1 D1 I/O Data 43 37 P0.0 D0 I/O Data 44 38 VDD VDD P +5V 2000 Jul 27 2
  3. 3. Philips Semiconductors PXA-G49 Parallel Programming Specification PXA-G49 PROGRAMMING MODES The PXA-G49 Flash Microcontrollers have two programming modes: a. Parallel programming on a programmer, like an EPROM Microcontroller with VPP = 12V. This document speciifes Parallel programming requirements. b. ISP - In System Programming - while the Microcontroller is soldered to the board. The parallel programming is done on a programmer like an EPROM microcontroller. The parallel programming is faster than the ISP programming and can be done even faster on a gang programmer with many Microcontrollers programmed at the same time. The ISP programming is done without removing the microcontroller from the system. The programming is done by downloading the code into the microcontroller and calling non-erasable built-in subroutines in the Micro’s ROM area. The user can download the code by using loader subroutines located in the ROM area, or use other loader routines written by the user and located in the Flash area. During the ISP programming, VPP = 5V. Programming areas in the FLASH microcontroller The microcontroller has several programming areas. These areas are programmed by the manufacturer during manufacturing, or by the user. Table 1 Programming areas in the FLASH microcontroller Not erasable/ Manufacturer’s Parallel ISP Non Programming programming programming programmable Boot ROM Boot ROM at address F800H-FFFFH Mask ROM Boot Vector word X X X Status byte X X X Manufacturer’s three ID signature bytes X Three LOCK bits X X X Flash memory at address 0 - FFFFH X X X Boot ROM The “Boot ROM” area is located at address F800H-FFFFH in a non erasable masked ROM. The boot ROM area contains the following code: a. Serial communication code to talk to a PC during the ISP programming. b. Program/Erase/Verify subroutines used during the ISP programming. The Boot ROM overlays the program flash memory space at the top 2k addresses, from F800H to FFFFH. The Boot ROM may be turned off by clearing the SFR AUX bit 7, and the upper 2k bytes of FLASH memory is accessible by the user. 2000 Jul 27 3
  4. 4. Philips Semiconductors PXA-G49 Parallel Programming Specification PXA-G49 Status byte and Boot vector word The Status byte and the Boot vector word are located in the programmable flash memory. After RESET the Microcontrollers HW checks the status byte: a. If STATUS BYTE = 0; the program begins executing from the address 0000H. b. If STATUS BYTE ≠ 0 (FFH is preferred); the program jumps to the address pointed by the “Boot Vector” word BPC. The pointed address is the beginning of the ISP code. The BPSW (16-bit) is copied to PSW After programming the FLASH memory, the status byte should be erased to 00h in order to allow execution of the user’s code beginning at address 0. The user has three ways to jump to the ISP program: a. Write Status Byte ≠ 0; the program will jump to the ISP program after reset. b. Force the program to jump to the “boot vector” address by the following sequence: 1. Connect EA to VIH. 2. Connect PSEN to VIL. 3. Assert RST to VIL. 4. Release RST to VIH. 5. Release PSEN to VIH. The program will jump to the ISP program at the rising edge of RST. c. Call the ISP program from the user’s application. Boot Vector word After RESET the program jumps to the address pointed by the “Boot Vector” word. The ISP program is usually located at address F800H, thus the “boot vector” word contains “F800H”. Do not change this unless an ISP program is located elsewhere. An ISP program can be at any location in the 64K. We recommend users to have a fault tolerant ISP programming by using the following sequence: 1. Program the Boot Vector word to point to the ISP fault recovery code. Address F800H if using the default serial loader. 2. Program the status byte to non-zero value (FFH is preferred). 3. Perform the ISP programming. 4. Erase both status byte and boot vector after ISP has been successfully done. There is no way to erase the status byte without the Boot Vector word. 5. Program boot vector back to the original value(F800H) if the user wants to keep the default serial loader as the ISP communication channel after ISP is done. 6. Write 00H to the Status Byte; the program will begin at address 0 after master reset. 2000 Jul 27 4
  5. 5. Philips Semiconductors PXA-G49 Parallel Programming Specification PXA-G49 Flash memory map ROM FLASH 64K BOOT ROM ISP CODE 62K Block 4 48K Block 3 32K Block 2 16K Block 1 8K Block 0 0 Figure 1: Flash memory map ROM FLASH RESET 64K BOOT ROM ISP CODE 62K Block 4 STATUS YES BYTE = 0 48K NO PSEN = LOW Block 3 YES ALE = EA = HIGH BOOT VECTOR at RESET rising 32K edge FORCE ISP Block 2 NO 16K Block 1 8K Block 0 GO TO ADDRESS 0 0 Figure 2: Checking the Status Byte after Master Reset 2000 Jul 27 5
  6. 6. Philips Semiconductors PXA-G49 Parallel Programming Specification PXA-G49 LOCK (SECURITY) BITS Parallel Programmers must adhere to the following convention for LOCK bits: LOCK[1] Inhibits writing to the Flash memory LOCK[2] Inhibits reading FLASH memory from outside LOCK[3] Disables execution of external memory Lock bits are erased to: 000B. Table 2 Microcontroller’s ID bytes Size Mft ID Dev ID Config ID PXA-G49 64K x 8 15H EAH 01_000_100, 44H Table 3 Configuration ID bits fff Flash Size sss SRAM size 010 64K 100 2048 bytes Table 4 Block erase Block # Erase A[15:13] Erased Value 0 0 to 8K 000 FFH 1 8K to 16K 001 FFH 2 16K to 32K 010 FFH 3 32K to 48K 100 FFH 4 48K to 64K 110 FFH The Flash memory can be erased as a chip erase or a block erase. A chip erase erases 64KByte; the block erase erases blocks of 16K or 8K bytes. The first two blocks are 8Kbytes; all the other blocks are 16 Kbyte long. The erase value for data is FFH. INITIALIZE Initialize function erases the whole memory array, security lock bits,except status byte and boot vector word into their initial erased state. IInitialize has the same timing waveform as chip erase that except MS[3:0] = 1110. See table 5. The flowchart of initialize is similar to chip erase except that we erase-verify the memory array as well as security lock bits, status byte and boot vector after applying erase pulse(s). 2000 Jul 27 6
  7. 7. Philips Semiconductors PXA-G49 Parallel Programming Specification PXA-G49 Parallel Programming Below is the description of address-map from parallel progamming’s view. A[15:0]={p3.5,p3.4,p2[5:0],pl[7:01]} Dara[7:0]=pO[7:0] mode[3:O]={p2.6,p3.7,p3.1,p3.0} . mode[3:0] Function Name Description 0000 read ByteRead operation, i.e. Output of data ponited by A[15:0]. Althrough flash-module is word(2bytes) read-access. 1110 Init Initialize flash-module, i.e. after Init phase, the array(64KByte) are cleaned to 0xFF, while Lock[3:1) is cleaned to 0x0 Sbyte[7:0]is cleaned to 0x00 BPSW[15:0]is cleaned to 0x0000 BPC[15:9] is cleaned to 0x0000 Config[7:0] do not change 0001 Chip Erase Chip Erase, i.e. after Chip Erase phase, the array(64KByte) are cleaned to 0xFF, while Lock[3:1] is cleaned to 0x0, other special cells are not updated. 0010 Block Erase Block Erase, A[15:13]=000, to erase blk0( 0-- 8kByte) A[15:13]=001, to erase blk1( 8--16kByte) A[15:13]=01x, to erase blk2(16--32kByte) A[15:13]=10x, to erase blk3(32--48kByte) A[15:13]=11x, to erase blk4(48--64kByte) 0011 Erase-verify After Chip Erase of BIock Erase, use Erase-verify to check whether erase is successful or not. The dataout is pointed by A[15:0]. Althrough flash-module is word(2bytes) Erase-verify-read-access. 0100 Program-8 bits Program 1Byte data into flash pointed by A[15:0] 0110 Program-verify After Program-8 bits, use Program-verify to verify the programmed-data pointed by A[15:0] 0111 Program Lock, Program special cell, the address-map is Sbyte, BPSW, BPC A[3:0]=0000 :== BPSW[7:0] A[3:0]=0001 :== BPSW[15:8] A[3:0]=0010 :== BPC[7:0] A[3:0]=0011 :== BPC[15:8] A[3:0]=0100 :== Sbyte[7:0] A[3:0]=0101 :== reserved A[3:0]=0110 :== MftID[7:0],not allowed at pgm-mode A[3:0]=0111 :== DevID[7:0],not allowed at pgm-mode A[3:0]=1000 :== Config[7:0] A[3:0]=1001 :== reserved A[3:0]=1010 :== Lock[1] A[3:0]=1011 :== reserved A[3:0]=1100 :== Lock[2] A[3:0]=1101 :== reserved A[3:0]=1110 :== Lock[3] A[3:0]=1111 :== reserved As program is ONE-WAY direction, i.e. only to program to 1 for special cells. to program to 0 for array. 2000 Jul 27 7
  8. 8. Philips Semiconductors PXA-G49 Parallel Programming Specification PXA-G49 mode[3:0] Function Name Description 1100 Program-verify Lock, Program-verify special cell pointed by A[3:0], the address map is the same as “Pgm special cells(mode=7)”. Sbyte, BPSW, BPC, ReadID To read Device-ID or Maf. ID out. 1001 Erase Sbyte, To erase special cell pointed by A[3:0], the address map is the same as “Pgm special cells(mode=7)”. BPSW, BPC 1010 Erase-verify Lock, To erase-verify special cell pointed by A[3:0], the address map is the same as “Pgm special cells(mode=7)”. Sbyte, BPSW, BPC 1011 TestMode Reserved for tester. 1100 ChipEraseEnd Final step for ChipErase. 1101 BlockEraseEnd Final step for BlockErase, block-address-pointed by A[15:13]. 1111 Command-Key A sequential pattern-write for turn-cmd-key-on This requirement may be turn-off by pulling p3.2 low during parallel programming. 0111 Program Config reserved for tester. 1000 Program-verify To read the config out by program-verify-vt-level config 1010 Erase-verify config To read the config out by erase-verify-vt-level 2000 Jul 27 8
  9. 9. Philips Semiconductors PXA-G49 Parallel Programming Specification PXA-G49 + 5v PXA-G49 4.7K A0-A7 P1.0-P1.7 VDD Pullups A8-A13 P2.0-P2.5 P0 Data A14 P3.4 EA/VPP Vpp = 12V A15 P3.5 ALE/PROG Active Low WR Pulses CE P3.3 0 PSEN OE P2.7 XTAL2 3.5-12 MHz MODE(3:0) P2.6, P3.7, P3.1, P3.0 XTAL1 0 RST VSS Figure 3: Pin functions during Parallel Erase/Programming/Verifications Table 5 DESCRIPTION FUNCTION DURING PIN NAME I/O* FUNCTION PROGRAMMING P1.7 - P1.0 A7 - A0 I 8 LSB address bits P3.5, P3.4, P2.5 - P2.0 A15, A14, A13 - A8 I 8 MSB address bits P0.7 - P0.0 D7 - D0 I/O Data Input/Output P3.3 CE I Chip Enable Input P2.7 OE I Output Enable Input ALE WE I Write enable Input EA VPP P Programming Voltage 12V P2.6, P3.7, P3.1, P3.0 MS3 - MS0 I Flash Mode Selection RST RST = VIL I Enable programming mode PSEN PSEN = VIL I Enable programming mode VDD VDD P Power Supply Voltage (+5V) VSS VSS P Ground Pin * I = Input, O = Output, P = Power 2000 Jul 27 9
  10. 10. Philips Semiconductors PXA-G49 Parallel Programming Specification PXA-G49 Function Table Table 6 Parallel programming Function table PSEN = 0 RST=1 EA/ P3.3 P2.7 ALE A[15:0] MS[3:0] P0[7:0] VPP CE OE WE P2.6, P3.7, P3.1, P3.0 Standby X 1 X X X X X Read Note 2 0 0 1 A[15:0] 0000 Data Output Initialize Note 2 0 1 0.35 S pulse X 1110 X Chip Erase 0 to 64K Note 2 0 1 0.35 S pulse X 0001 X Block Erase Note 2 0 1 0.35 S pulse A[15:13] 0010 X Erase-verify Note 2 0 1 1 A[15:0] 0011 Data Output Program-8 bits Note 2 0 0 10 uSec pulse A[15:0] 0100 Data Input Program-verify Note 2 0 1 1 A[15:0] 0110 Data Output Program Lock Sbyte BPSW BPC Note 2 0 1 10 uSec pulse A[3:0] 0111 Data Input Program-verify Lock, Sbyte, Note 2 0 0 1 A[3:0] 1000 Data Output BPSW, BPC, ID Erase Sbyte BPSW, BPC Note 2 0 1 0.35 S pulse A[3:0] 1001 X Erase-verify Lock, Sbyte, BPSW, Note 2 0 0 1 A[3:0] 1010 Data Output BPC Test modes Note 2 0 TBD TBD TBD TBD TBD Command-Key (*) Note 2 0 1 1 A[1:0]=01 1111 Data Input ChipEraseEnd Note 2 0 1 Pulse X 1100 X BlockEraseEnd Note 2 0 1 Pulse A[15:13] 1101 X Program Config Note 2 0 1 10 uSec pulse A[3:0] 0111 Data Input Program-verify config Note 2 0 0 10 uSec pulse A[3:0] 1000 Data Output Erase-verify config Note 2 0 0 0.35 S pulse A[3:0] 1010 Data Output (*) used to turn Program-verify config "parallel-programming" on. Without this step, future erase/program operation will be stopped. Note 1. There are 2 command registers(CMD0, CMD1) within XA-G49. When mode is "command-key", sequential write will turn on Erase-verify config Command-key. A[15:0]=5555 data=AA will write CMD0 be AA. A[15:0]=AAAA data=55 will write CMD1 be 55. When CMD0==AA, CMD1==55, future erase/program is allowed. Note 2. When parallel programming the flash memory, VPP must be 12V ±5%. See Table 5. Initialize Chip Erase 0 to 64K Block Erase Erase-verify 2000 Jul 27 10
  11. 11. Philips Semiconductors PXA-G49 Parallel Programming Specification PXA-G49 Timing diagrams Read-8 signature bytes and read normal data bytes 12V VPP WE A[15:0] A[15:0] tACE CE tACE tAA tCE tCE tDF OE tOE tMSCE tMSCE tOE tMSCE MS[3:0] 1000 XXXX 0000 DATA Mft ID/ DATA[15:0] DeviceID1/ device ID2 Read Signature Standby Read data Figure 4: Read signature Table 7 AC CHARACTERISTICS TA = 0oC to 70 oC, VDD = 5V ±5%, VPP = 12V ±5% Parameter Symbol MIN MAX Unit Address to CE time tACE 100 ns Address access time tAA 200 ns CE access time tCE 200 ns OE access time tOE 200 ns OE = HIGH to data floating tDF 20 ns Mode select CE = HIGH tMSCE 100 ns 2000 Jul 27 11
  12. 12. Philips Semiconductors PXA-G49 Parallel Programming Specification PXA-G49 Erase and Erase verify-8 operations (CEB control) A[15:0] A[15:0] XXXX or {A[15:13]} A[15:13] DATA DATA[15:0] tAWE tAWE tEV OE tACE tACE tCES tWES tEV CE tER tACE WE tWES tMS tWEPW tMS tMS tMS tMS tWEPW tMS tMS MS[3:0] 0001/0010 0011 1100/1101 CHIP ERASE ERASE END BLOCK ERASE VERIFY OF CHIP ERASE AND BLOCK ERASE Figure 5: Erase and Erase Verify Table 8 Erase AC timing Parameter Symbol MIN MAX Unit tAWE 2 µs tDH 2 µs tACE 100 ns Mode select hold/setup time to CE tMS 100 ns Setup time from CE=LOW to WR=LOW tWES 0 ns Setup time from CE=LOW to OE=LOW tCES 0 ns Erase recovery tER 0 Sec Erase write pulse width tWEPW 0.35 Sec Erase/address verify access time tEV 100 ns Mode valid to CE change tMSCE 100 ns 2000 Jul 27 12
  13. 13. Philips Semiconductors PXA-G49 Parallel Programming Specification PXA-G49 Program-8 and program verify-8 operations (CEB control) A[15:0] A[15:0] tAS tAS DATA IN OUT tDWES tDWEH VPP = 12V VPP OE tVPS tPR tPV CE tMSCE WE tCES tCES tMSCE tMS tPW MS[3:0] 0011 0101 PROGRAM PROGRAM VERIFY Figure 6: Program / Program verify Table 9 Program AC timing Parameter Symbol MIN MAX Unit Address setup time to WE=LOW tAS 100 ns Data setup time to WE=LOW tDWES 100 ns Data hold time after WE=HIGH tDWEH 0 ns VPP = 12V setup time to WE=LOW tBS 90 ns CE=LOW setup time to WE=LOW tCES 0 ns Mode select setup time to WE=LOW tMS 2 µs WE=HIGH to CE=HIGH tPR 0 ns WE=LOW pulse width tPW 10 µs Access time OE=LOW to valid data tPV 100 ns Mode select setup time to CE=LOW tMSCE 100 ns 2000 Jul 27 13
  14. 14. Philips Semiconductors PXA-G49 Parallel Programming Specification PXA-G49 Programming flowcharts Erase and erase verify START X=0 If LOCK[2] is programmed, program 0 to each byte 3 times Program Chip/Block without verifying it to all 0’s Pass Erase chip/block No Erase verify from Fail the last failure address X = 30 x = x+1 We recommend to remember the last failure address, and start verify from Pass this address to save time Yes Pass Erase verify Fail device the whole chip or block failed Erase_pulse Erase_end device Erase_pulse passed Erase_end Erase_end Erase_pulse Figure 7: Erase / erase verify flowchart 2000 Jul 27 14
  15. 15. Philips Semiconductors PXA-G49 Parallel Programming Specification PXA-G49 Erase and Erase-verify LOCK bits START X=0 This step is Program LOCK bits optional to all 1’s Erase chip No Fail Erase-verify LOCK bits X =30 x = x+1 Pass Yes device device passed failed Figure 8: Erase / Erase-verify LOCK bits flowchart 2000 Jul 27 15
  16. 16. Philips Semiconductors PXA-G49 Parallel Programming Specification PXA-G49 Erase and Erase-verify Status byte & Boot Vector START X=0 LOCK[1] YES Erase is SET ? LOCK bits NO Program Status byte This step is & Boot vector to all FF’s optional PASS Erase misc No Fail Erase verify misc X = 30 x = x+1 Pass Yes device device passed failed Figure 9: Erase / Erase-verify Status byte and Boot Vector 2000 Jul 27 16
  17. 17. Philips Semiconductors PXA-G49 Parallel Programming Specification PXA-G49 Flash memory Array START first address X=0 Program one neg. pulse No Fail Program Verify X = 50 x = x+1 PASS Yes No Increment address Last address Yes VPP = 12V Fail device Normal read all failed Pass device passed Figure 10: Program array 2000 Jul 27 17
  18. 18. Philips Semiconductors PXA-G49 Parallel Programming Specification PXA-G49 Program Lock bits, status byte or boot vector START X=0 Program misc No Fail Program Verify X = 50 x = x+1 PASS Yes device device passed failed Figure 11: Program Lock bits, status byte or boot vector 2000 Jul 27 18
  19. 19. Philips Semiconductors PXA-G49 Parallel Programming Specification PXA-G49 Table 10 Security bits Conditions Parallel Programming Lock1 Lock2 Lock3 Initialize Chip Erase Block Erase X Program Array Pgm. Lock Erase/Program verify X Normal read X Erase/Program X StatByte/BootVector Erase/verify Lock/Sbyte/Bootvect Read Device ID “X” = Not Allowed. Table 11 Security The security feature protects against software piracy and prevents the contents of the Flash from being read. The Security Lock bits are located in Flash. The XA-G49 has 3 programmable security lock bits that will provide different levels of protection for the on-chip code and data. Security Lock Bits* Protection Description Level SB1 SB2 SB3 1 0 0 0 No program security features enabled. 2 1 0 0 Inhibit writing to Flash. Also, MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. 3 1 1 0 Same as level 2, plus program verification is disabled. 4 1 1 1 Same as level 3, plus external execution is disabled. * Any other combination of the Lock bits is not defined. Table 12 VPP for VPP of 12V with VDD = 5V Conditions Typ. Max. Units Program w/VPP = 12V ±5% 4.0 9.1 mA Bulk Erase w/VPP = 12V ±5% 2.0 4.6 mA Chip Erase w/VPP = 12V ±5% 2.0 4.6 mA 2000 Jul 27 19
  20. 20. Philips Semiconductors PXA-G49 Parallel Programming Specification PXA-G49 Disclaimers Life support - These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes - Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patents, copyright, or mask work right infringement, unless otherwise specified. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone: 800-234-7381 ® Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Document Order Number: 9397 750 07356 2000 Jul 27 20

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