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    ppt ppt Presentation Transcript

    • Computer Organisation & Architecture IS C351 First Semester 2008-2009 Lecture #16-17 http://discovery.bits-pilani.ac.in/discipline/csis/virendra/isc351/coarc.htm
      • What’s Next:
      • Semiconductor Main Memory
        • Organization
        • DRAM and SRAM
        • Chip Logic
        • Module Organization
      • Advanced DRAM organization
        • Synchronous DRAM
        • DDR SDRAM
        • Cache DRAM
    • Dynamic RAM
      • Bits stored as charge in capacitors charges leak so need refreshing even when powered
      • Simpler construction and smaller per bit so less expensive
      • Slower operations, used for main memory
      • Address line active when bit read or written
        • Transistor switch closed (current flows)
      • Write
        • Voltage to bit line (high for 1 low for 0)
        • Then signal address line
          • Transfers charge to capacitor
      • Read
        • Address line selected and transistor turns on
        • Charge from capacitor fed via bit line to sense amplifier
          • Compares with reference value to determine 0 or 1. Capacitor charge must be restored
    • Static RAM
      • Bits stored as on/off switches no charges to leak
      • No refreshing needed when powered
      • More complex construction so larger per bit and more expensive
      • Faster used for Cache
      • Transistor arrangement gives stable logic state
      • State 1
        • C 1 high, C 2 low, T 1 T 4 off, T 2 T 3 on
      • State 0
        • C 2 high, C 1 low, T 2 T 3 off, T 1 T 4 on
      • Address line transistors T 5 T 6 is switch
      • Write – apply value to B & compliment to B
      • Read – value is on line B
    • Read Only Memory (ROM)
      • Permanent storage
        • Nonvolatile
      • Used for-
        • Microprogramming (see later)
        • Library subroutines
        • Systems programs (BIOS)
    • Types of ROM
      • Written during manufacture
        • Very expensive for small runs
      • Programmable (once)
        • PROM
        • Needs special equipment to program
      • Read “mostly”
        • Erasable Programmable (EPROM)
          • Erased by UV
        • Electrically Erasable (EEPROM)
          • Takes much longer to write than read
        • Flash memory
          • Erase whole memory electrically
    • FF circuit Sense / Write Address decoder FF CS cells Memory circuit Sense / Write Sense / Write circuit Data input /output lines: A 0 A 1 A 2 A 3 W 0 W 1 W 15 b 7 b 1 b 0 W R / b  7 b  1 b  0 b 7 b 1 b 0 • • • • • • • • • • • • • • • • • • • • • • • • • • • Organization of 16X8 memory chip
    • 16x8 Memory Chip: Organization Details
      • Organized in the form of an array, each cell is capable to store one bit of information
      • Each row of cells constitutes a memory word, and all cells are connected to a common line referred to as the word line, driven by the address decoder
      • Cells in each column are connected to a sense/write circuit by two bit lines
      • Stores 128 bits (16x8) and requires 14 external connections for address, data and control lines
    • Organization of a 1K  1 memory chip CS Sense / Write circuitry array memory cell address 5-bit row input/output Data 5-bit decoder address 5-bit column address 10-bit output multiplexer 32-to-1 input demultiplexer 32 32  W R / W 0 W 1 W 31 and How many external connections are required?
    • Memory Organisation Issues
      • A 16Mbit chip can be organised as 1M of 16 bit words
        • 36 pins require to address
        • Chip size increases
      • It can be organized as 2M x 8
        • 29 pins are required to address
      • It can be organised 1 bit per chip
        • A 16Mbit chip can be organised as a 2048 x 2048 x 4 bit array
        • Reduces number of address pins
          • Multiplex row address and column address
          • 11 pins to address (2 11 =2048)
          • Adding one more pin doubles range of values so x4 capacity
    • Typical 16 Mb DRAM (4M x 4)
    • Packaging
    • 256kByte Module Organisation
    • 1MByte Module Organisation
    • Synchronous DRAM (SDRAM)
      • Access is synchronized with an external clock
      • Address is presented to RAM
      • RAM finds data (CPU waits in conventional DRAM)
      • Since SDRAM moves data in time with system clock, CPU knows when data will be ready
      • CPU does not have to wait, it can do something else
      • Burst mode allows SDRAM to set up stream of data and fire it out in block
    • DDR SDRAM
      • SDRAM can only send data once per clock
      • Double-data-rate SDRAM can send data twice per clock cycle
        • Rising edge and falling edge
      • Developed by Mitsubishi
      • Integrates small SRAM cache (16 kb) onto generic DRAM chip
      • Cache DRAM
      • Used as true cache
        • 64-bit lines
        • Effective for ordinary random access
      • To support serial access of block of data
          • CDRAM can prefetch data from DRAM into SRAM buffer
          • Subsequent accesses solely to SRAM
    • Flash memory
      • Similar technology as EEPROM i.e. single transistor controlled by trapped charge
      • A single cell can be read but writing is on block basis and previous contents has to be removed
      • Greater density and a lower cost per bit, and consumes less power for operation
      • Used in MP3 players, Cell phones, digital cameras
    • DIMM Memory Modules and Slots
    • SIMM Memory Modules
    • Finally Memory Interleaving
      • Main memory is structured as a collection of physically separate modules
      • Each having its own ABR and DBR
      • Memory access operation can be in more than one module at the same time
      • How the individual addresses are distributed over the modules, is the key?
      • Two common distributions are:
        • Consecutive words in a module
        • Consecutive words in consecutive modules also called memory interleaving