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Transcript

  • 1. BEE2 Hardware Status Jan 2005 Chen Chang, Pierre-Yves Droz, John Wawrzynek, Bob Brodersen EECS, UC Berkeley
  • 2. Compute Module Diagram
  • 3. Compute Module 14X17 inch 22 layer PCB
  • 4. Testing methods
    • Diagnostic shell running on the PowerPC of the FPGAs, which controls all test modules
    • Software control of I2C, PLL, Ethernet with Xilinx EDK IPs
    • Xilinx MGT BERT tester IP used for serial link test
    • Xilinx DDR2 memory tester for DRAM
    • This test suite will evolve into the full system on-line diagnostic package
  • 5. Preliminary Testing Results
    • Subsystem verified working:
      • All power regulators
      • All FPGAs
      • System ACE, Compact Flash interface
      • 100Base-T Ethernet
      • System clock distribution, PLL
      • RTC, Voltage monitor
    • Interconnect preliminary speeds
      • Inter-FPGA LVCMOS connections at least 200DDR rate with full global synchronous
      • Selected MGT links @ both 2.5 and 3.125 Gbps
      • Selected DRAM modules @ 390DDR rate
  • 6. MGT links Eye Diagrams
  • 7. Potential Analog Frontends
    • Radio Telescopes (ADC only)
      • SETI: 300 MHz bands
      • ATA32: 400MHz bands
      • CARMA: 500MHz bands
      • VLBI: 1024MHz bands
    • TV-band Cognitive radio (ADC/DAC)
      • 0.5~1GHz bandwidth
    • Ultra-Wide Band radio (ADC/Pulse driver)
      • 1GHz bandwidth
    • Direct digital synthesis of cable TV signals (DAC only)
      • 800MHz bandwidth
  • 8. BEE2 A/D interface overview
    • Use IBOB to fanout the serial Infiniband connections to parallel LVDS/LVPEL signals
    • IBOB can be connected to BEE2 modules or directly to Infiniband swtiches
    • Built-in support to connect to the Mark-V disk array archiver
  • 9. Infiniband Break-Out Board (IBOB)
  • 10. 1 GHz Dual ADC Board
  • 11. ADC LVDS output @ 500MHz
  • 12. Hardware to do list for the next 6 month
    • Full speed characterization of the BEE2 module
      • Inter-FPGA connection with source synchronous
      • 4 channel bonded MGT links
      • DDR2-400 memory 4 bank simultaneously
      • Other peripheral subsystems (USB, DVI, etc)
    • System integration
      • Acquire the Infiniband switch
      • Develop the IB link layer FPGA core
      • 2 node system communication test
    • ADC/IBOB interface testing
  • 13. Hardware to do list for the next 6 month (cont.)
    • Linux OS porting to BEE2 module
      • Remote multi-user access/sharing of the hardware
      • Remote debug environment
      • Hardware-in-the-loop simulation environment
    • 10 node system manufacturing, testing, and integration
    • Continuing collaboration with SETI/RAL/ATA as well as Xilinx
      • Hardware hand-off
      • Software infrustructure
      • Application development and testing
  • 14. Backup slides
  • 15. Atmel Dual 1GHz ADC
    • Interlace mode to provide 2GSPS
    • 3 wire control interface, tons of tweak options
    LQFP144 Package 3.3V, 3.3V, 2.25V Supply voltages LVDS (1:1,1:2) Outputs 0.5V Input Voltage $155 Price (1K) 1.4W Power consumption 42dB SNR 0.5/1.5GHz Input BW (-0.5dB/-3dB) 6.8 ENOB @ Nyquist 8 Bits Dual 1000 MSPS AT84AD001B
  • 16. IBOB PCB layout
  • 17. Z-Dok+ connector
    • High-speed differential signals
      • up to 6.25Gbps per pair
      • 8~72 pairs per connector
    • Built-in PWR/GND utility contacts
      • Each carry 5A current
      • Up to 6 contacts per connector