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Pinewood Derby Timing System Using a Line-Scan Camera
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Pinewood Derby Timing System Using a Line-Scan Camera

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Transcript

  • 1. Pinewood Derby Timing System Using a Line-Scan Camera Rob Ostrye Class of 2006 Prof. Rudko
  • 2. Project Background
    • System is used to determine time and finish order of cars in a pinewood derby car race
    • Accommodates up to 4 lanes
    • Easy to use, low cost, and accurate
    • Operate from a PC via a USB cable
    • Images taken and displayed on the computer
  • 3. Pinewood Derby Setup Starter Lanes Camera Lens
  • 4. Timer Implementation
    • Line-Scan CCD camera lens and sensor capable of monitoring up to 4 lanes
    • Xilinx FPGA for core logic and component interfacing
    • Non-Volatile Memory for start up
    • DRAM for holding data
    • 2 Layer PCB interfacing all components
  • 5. Components Used
    • Xilinx XC3S250E VQ100 FPGA (link)
    • 1.2v Switching Power Supply
    • 2.5v and 3.3v LDO Power Supplies
    • TAOS TSL3301 CCD (link)
    • M12 CCD Lens
    • SPI Flash Memory
    • SDRAM
    • 48 MHz System Clock
    • Transient Voltage Suppressor
    • External Connectors
      • USB
      • Trigger
  • 6. Circuit Board FPGA Power Supplies DRAM 2.5v 1.2v 3.3v 38 5v Image Sensor Flash Memory Clock External Trigger USB
  • 7. Xilinx Spartan 3E FPGA
    • 66 User Input/Outputs accommodates the needs for all of the components chosen
    • 250k system gates allows for a greater range of functionality
    • Small size
    • Availability of software tools and libraries for implementation
  • 8. Power Supplies
    • Switching Supply: 1.2v
      • Low power loss
      • FPGA Core voltage
    • Low Quiescent Current LDO: 3.3v and 2.5v
      • Small footprint
      • Provide enough current for application
  • 9. Image Acquisition
    • CCD:
      • 102x1 Pixels translates to about .17 inches square per pixel when the sensor is placed 13 inches above the trace
      • Serial Interface for easier VHDL implementation
      • Explicit instructions available to control the sensor
      • Fits supply voltage constraints
    • M12 Lens:
      • Focal length of 8.0mm will accommodate about 4 tracks at about 13 inches above the track
      • Fits in an existing part used for the M12 lens
  • 10. System Memory
    • Synchronous DRAM 4x16
      • 64MBit will store high amount of data
      • Control module cores are available
      • Interface easily with the FPGA
    • SPI Flash Memory
      • 4MBit hold enough data for load instructions
      • FPGA has settings for easy implementation
      • Readily available chip due to high consumer demands
  • 11. Programming
    • Interface the sensor with the block RAM within the FPGA
    • Enter data from block RAM into DRAM
    • Take data from the DRAM and read out over USB
    • Use developed cores for:
      • USB interface to the computer
      • SPI Flash interface
      • DRAM reading and writing
  • 12. Cores around the FPGA DRAM Interface SPI Flash Interface USB Interface Trigger Interface Image Sensor Interface FPGA
  • 13. Interface between BRAM and Sensor Image sensor receives data serially into an 8 bit register which provides instructions to the sensor. SClock SD SDin Image Sensor Block RAM Image Sensor Interface
  • 14. ASM for Image Sensor Interface Defaults timer = timer-1 writeEN = 0 SDin = 0 Asynch Reset address = 0 SDin = 0 writeEN = 0 timer = 0 I Reset timer = -32 0 1 timer = 0 0 1 Read BRAM Wait state address = address + 1 SDin = BRAM(address) Write pix = 0x16 0 1 Wait start timer = 0 1 0 1 0 SD address(2:0) = 0 1 0 Write Pixel address = address + 1 writeEN = 1 SDin = 0 timer = 10MHz line rate address = 0 address = 512
  • 15. Line Acquisition Rate The line scan rate is adjustable based on the timer reset value. 1 line / 630  s ≈ 1600 lines/sec 630  s
  • 16. Results
    • Custom designed circuit board with working supply voltages and correct component connections
    • Image sensor interface modeled and proven to work in simulation
    • Adapted to work on a development board
    • Available cores analyzed and chosen
  • 17. Possible Future Development
    • Image acquisition that will read out only the period of time when the cars are under the camera
    • Interface logic cores for integrated operation
    • Set up the external trigger to start device
    • Use SPI flash memory to program the FPGA on startup
    • Develop an algorithm for focusing the lens
  • 18. Resources
    • Birger Engineering, Inc.
      • The project was conducted in conjunction with the company.
      • Provided technical knowledge with respect to hardware and software development
      • Provided software and some of the hardware involved with the project
    • Opencores.org
      • Open source codes and information pertaining to USB, DRAM, SPI flash elements of the project
    • Component Technical Documentation
    • Prof. Rudko

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