NVSL Presentation Template

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NVSL Presentation Template

  1. 1. Characterizing Flash Memory: Beyond the Datasheet Laura M. Grupp*, Adrian M. Caulfield*, Joel Coburn*, Eitan Yaakobi†, Steven Swanson*, Paul H. Siegel† *Non-volatile Systems Laboratory, Department of Computer Science and Engineering †Center for Magnetic Recording Research Jacob’s School of Engineering University of California, San Diego 1
  2. 2. Possible Applications • Flash Translation Layers (FTLs) • Operating System control • Data encodings • Heterogeneous SSD • Data retention time 2
  3. 3. Test Setup • Custom-Built Daughter Board • Xilinx XUP Board • Full-fledge Linux • Kernel module Erase Read Repeat Program 10x Lifetime Read 3
  4. 4. The Test Subjects Chip Manufacturer Capacity Page Size Pages/ Block/ Planes/ Dies Name (GB) (B) Block Plane Die A-SLC2 A 2 2048 64 1024 2 1 A-SLC4 A 4 2048 64 4096 1 1 A-SLC8 A 8 2048 64 4096 2 1 B-SLC2 B 2 2048 64 2048 1 1 B-SLC4 B 4 2048 64 2048 2 1 E-SLC8 E 8 2048 64 4096 1 2 B-MLC8 B 8 2048 128 4096 1 1 B-MLC32 B 32 4096 128 2048 2 2 C-MLC64 C 64 8192 128 4096 1 2 D-MLC32 D 32 4096 128 4096 1 2 E-MLC8 E 8 4096 128 1024 1 2 4
  5. 5. The Tests Quantify known complexities, look for new ones • Performance • Energy Efficiency • Reliability 5
  6. 6. The Tests Quantify known complexities, look for new ones • Performance • Energy Efficiency • Reliability 6
  7. 7. Read Time(µs) 0 100 120 140 20 40 60 80 A-SLC2 A-SLC4 A-SLC8 B-SLC2 B-SLC4 E-SLC8 Program Time(µs) B-MLC8 B-MLC32 C-MLC64 - 500 1,000 1,500 2,000 2,500 D-MLC32 A-SLC2 E-MLC8 A-SLC4 A-SLC8 Operation Latency B-SLC2 B-SLC4 Erase Time(µs) E-SLC8 - 1,000 1,500 2,000 2,500 3,500 4,000 4,500 500 3,000 B-MLC8 B-MLC32 C-MLC64 A-SLC2 D-MLC32 A-SLC4 E-MLC8 A-SLC8 B-SLC2 B-SLC4 E-SLC8 B-MLC8 B-MLC32 C-MLC64 D-MLC32 E-MLC8 7
  8. 8. Program Speed Anomaly 2,500 Fast 50% of Pages 2,000 Program Time (s) Slow 50% of Pages 1,500 1,000 500 - Page #: 0 1 2 3 4 5 6 7 8 9 … 118 119 120 121 122 123 124 125 126 127 … 8
  9. 9. Variation-Aware FTLs • Can now embellish existing FTLs • Page based FTL from MSR [Birrell et. al., 2005] – “High priority” == write to fast page – “Low priority” == any page • Effects of Skipping slow pages – Lower latency when it matters – Increased wear 9
  10. 10. Improving Paging Latency • Paging out Virtual Memory – 5-20% of total accesses – High Priority • Goal: reduce swap latency • Side effect: Increased Wear 10
  11. 11. Results • Swap Writes: 1.5x faster • Wear increased by only 3% 1.4 Baseline Writes Swap Writes 1.2 Normalized Response Time 1 0.8 0.6 0.4 0.2 0 Build DeskDev Financial Average 11
  12. 12. The Tests Quantify known complexities, look for new ones • Performance • Energy Efficiency • Reliability 12
  13. 13. Power Operation SLC MLC Read 15.8 – 54.5 mW 10.6 – 123.5 mW Program 32.8 – 88.5 mW 15.2 – 141.3 mW Erase 18.3 – 50.3 mW 26.7 – 112.3 mW Idle 1.9 – 17.7 mW 8.2 – 27.5 mW 13
  14. 14. Programming Energy Pages have • Similar power • Dissimilar latencies 200 180 Fast 50% of Pages 160 140 Slow 50% of Pages Program Energy (μJ) 120 100 80 60 40 20 0 B-MLC32 B-MLC8 C-MLC64 D-MLC32 E-MLC8 14
  15. 15. The Tests Quantify known complexities, look for new ones • Performance • Energy Efficiency • Reliability 15
  16. 16. Error Rates 4.0E-07 C-MLC64 3.0E-07 D-MLC32 Bit Error Rate (%) B-MLC32 2.0E-07 E-MLC8 B-MLC8 1.0E-07 0.0E+00 0 2000 4000 6000 8000 10000 12000 14000 Program/Erase Cycles 16
  17. 17. Program Disturb - Procedure Procedure: Erase Block 11111111111111111 11111111111111111 11111111111111111 11111111111111111 Repeat: 11111111111111111 11111111111111111 Program Each Page 00000000111111111 00000000111111111 Use 0’s on half of one page 11111111111111111 11111111111111111 11111111111111111 11111111111111111 11111111111111111 11111111111111111 11111111111111111 11111111111111111 17
  18. 18. Program Disturb - Results • SLC: no errors for at least one reprogram • MLC: errors for reprograms of certain pages 0 1 2 3 4 5 6 7 … … 18
  19. 19. Write-Once Memory (WOM) Codes Logical First Second Reprogram Bits Generation Generation Write-Once Memory 00 111 000 01 110 001 1. 01110110 10 101 010 11 011 100 2. 10000111 Program: 01 11 01 10 Reprogram: 10 00 01 11 Physical 110 011 110 101 1st Gen. Physical 010 000 110 100 2nd Gen. 19
  20. 20. WOM Codes and Flash Procedure: Erase, Program, Reprogram, Repeat WOM-safe: use WOM encoding WOM-unsafe: use the same un-encoded data both times …             … 20
  21. 21. Error Rates 4.0E-07 C-MLC64 3.0E-07 D-MLC32 Bit Error Rate (%) Fatal B-MLC32 Error Rate 2.0E-07 E-MLC8 B-MLC8 1.0E-07 0.0E+00 0 2000 4000 6000 8000 10000 12000 14000 Program/Erase Cycles 21
  22. 22. WOM Codes – Lifetime Extension Fatal Error Rate: error rate at quoted lifetime 6 Baseline WOM 5 Logical Bytes Written 4 3 2 1 0 B-MLC8 B-MLC32 C-MLC64 D-MLC32 E-MLC8 22
  23. 23. WOM Codes – Energy Reduction Fewer erases per written bit 3 Required Program Energy (nJ/bit) Baseline WOM 2.5 2 1.5 1 0.5 0 23
  24. 24. Conclusion • Aim: how to make the best use of flash • Wealth of data beyond the data sheet • Tune the interface or application 24
  25. 25. Thank You ??? 25

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