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The pattern count for transition faults may reach 20,000
Scan test ATE Scan input channels Primary outputs Scan output channels Primary inputs
ATE cost Tester cost = b + m p b - base cost (zero pins) m - incremental cost per pin p - number of pins Test cost can be $0.05/second High performance ASIC / MPU DFT tester Low performance Microcontroller 250 - 400 100 - 350 200 - 350 2700 - 6000 150 - 650 1200 - 2500 512 512 - 2500 256 - 1024 b [ K$ ] m [ $ ] p
Volume of scan test data Test cycles = Patterns Scan cells Scan chains ...
Scan test time Test time = Scan cells Scan chains ... Frequency Patterns
Scan test cost More Shift frequency 20 MHz Gate count 10M Scan chains 32 Padding ratio 1.4 Scan patterns 20K Vector memory 64MV Reload penalty 2s Insertions 4 Tester rate 0.05$ Scan cells 500,000 Cells per scan 15,625 Longest scan chain 21,875 Cycles 437.5M Scan test time 21.9s Passes 6 Reload time 12.0s Time pre device 87.5s Cost per device 4.4$