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  • Good afternoon ladies and gentlemen! My name is Janusz Rajski. I work for Mentor Graphics and on behalf of my company I would like to welcome everybody to this special event organized to introduce Embedded Deterministic Test technology. EDT is a new DFT technology designed specifically to provide very high quality, low cost manufacturing test.
  • We have reasons to believe that this breakthrough technology will form a platform for solutions and products to effectively address the problem of rapidly growing cost of test that the semiconductor industry faces today. Although the technology was invented at Mentor a couple of years ago, the adopted product development strategy did not allow us to much details with the professional community until this time. Now that the product has been announced, we felt that it was appropriate to introduce the technology, explain what it is how it works and what benefits it offers. We organized this event as a completely open meeting. We invited everybody who has interest in DFT methodologies for low cost manufacturing test. We thank you all for coming!
  • At the beginning we will focus on the cost of test problem. … In the format of this event we do not envisage Q&A session. We expect that the presentation will take about one hour. After that myself and my staff, we will all be available to answer individual questions.

mukherjee_part1.ppt mukherjee_part1.ppt Presentation Transcript

  • Janusz Rajski Nilanjan Mukherjee Mentor Graphics Corporation for Low-Cost Manufacturing Low-Cost Manufacturing Embedded Test Embedded Test for
  • Presenters and authors Presenters: Janusz Rajski Nilanjan Mukherjee Mentor Graphics Corporation [email_address] Co-a uthor: Jerzy Tyszer Poznan Univ. of Technology
  • Tutorial ground rules
    • Definition: Embedded Test refers to design-for-testability techniques where testing is accomplished entirely or partially through on-chip hardware.
    • Disclaimer:
    • This tutorial is not intended to endorse or discredit any commercial technology or product.
  • Audience
    • Designers of complex integrated circuits
    • IP core providers and integrators
    • Test engineers
    • EDA tools developers
    • EDA tools users
    • Researchers
    • Project managers
    Everybody interested in state-of-the-art embedded test technology, to reduce the cost of manufacturing test In particular:
  • Tutorial objectives
    • To present:
    • Compelling reasons for ET adoption
    • Common barriers for ET adoption
    • State-of-the-art ET fundamentals and practice
    • Architectures for logic and memory BIST
    • Embedded deterministic techniques
    • At-speed ET
      • multiple-clock domain designs
      • multi-frequency designs
    • Tools for BIST synthesis automation
    • Application examples and case studies
  • Outline
    • Introduction
    • Embedded stimuli generators
    • Compactors of test responses
    • Logic BIST
    • Deterministic forms of embedded test
    • Embedded at-speed test
    • Comparison of scan/ATPG, logic BIST and embedded forms of deterministic test
    • BIST schemes for embedded memory arrays
    • Summary of embedded test
  • Introduction Introduction
  • Design characteristics CPU core Memory ASIC ASIC ASIC PLL IP core DSP core Memory IP core Memory Memory Memory ASIC Analog I / 0
  • System on Chip characteristics
    • System architecture
      • Microprocessors, DSP cores
      • Buses, peripherals, memory
      • ASIC portion
    • Structures: Logic, memory, analog
    • Multiple embedded memories: DRAM, Flash, CAM
    • Analog and mixed signal: PLLs, clock recovery
    • Field programmable logic
    • RF cores: wireless receivers
    • IP cores and reusable blocks available from multiple vendors
    • Design efficiency achieved by hierarchical core-based design style
    CPU core Memory ASIC ASIC ASIC PLL IP core DSP core Memory IP core Memor y Memory Memory ASIC Analog I / 0
  • New defects
    • Geometries shrink at 30% every three years
    • Defect sizes do not shrink in proportion
    • Increase of wiring levels from 6 to 9
    • Interconnect delays dominate
    • Gate delays reduced
    • Bridging faults
  • Sematech S-121
    • “ Test Method Evaluation –Key Findings & Conclusions”
    • Objective:
    • Evaluate various test methodologies
      • Large sample size
      • Extensive data collection & analysis
    [Sematech, 1998]
  • Sematech S-121
    • Device 116K equivalent gates
    • 0.45 µm L effective (0.8 µm drawn)
    • 50 MHz operating speed
    • 249 signal I/Os
    • 3 metal levels
    • Full LSSD Scan plus JTAG boundary scan
      • 8 Chains, 5,280 master/slave LSSD latches (10,560 total latches)
    • Sample size 20,000 units
    • Test methods:
      • Stuck-at faults, Functional tests, Transition delay faults & IDDQ
  • Sematech S-121 SAF - 99.5% coverage (8300 patterns) FUNC - 52% SAF coverage (532K cycles) IDDQ - >96% pseudo SAF coverage (195 patterns) Delay - 90% Transition coverage (15232 patterns)
    • Package test results (pre Burn-in)
    IDDQ 1463 FUNC 6 7 8 1 1251 13 SAF 6 0 52 Delay 14 34 36 FUNC IDDQ 1
  • S-121 Conclusions
    • All test methods detected unique defects
    • Near 100% SAF coverage missed many defects
    • Large defect coverage overlap between SAF & Delay
      • SAF are a subset of Transition faults
    • IDDQ threshold setting significantly affects yield
      • 98% of the IDDQ fails survived burn-in
    • Many (bridging) defects detected only by IDDQ
      • But diminishing IDDQ effectiveness in DSM
    • Some Functional tests are still required
    • Opportunity to optimize test coverage levels & capital
  • Process Shrinks vs. Defect Types Defect Pareto 350 nm Al 4-5 Levels Oxide Dielectric W Plugs 350 nm Process 5 million Transistors A Transistor BridgeM1-2 Bridge M2 Bridge M4 Break trans Bridge Poly M2 Bridge M3 Bridge M1-3 Bridge poly M1 Bridge M3-4 Open Poly Open Contact Bridge M1 Unknown Br Break M3 Bridge Poly M2 Break M2 Bridge M3-4 Break M1 Bridge Poly M4 Bridge Poly Unknown Via break
    • Defect distribution change with process
    Process Shrinks vs. Defect Types 100 nm Process -- 250 million transistors A Transistor Cu (8 Levels) Low-K Dielectric Cu Plugs Unknown Defect Pareto 100 nm ?
  • Defects vs. Fault Coverage
    • Wired “AND” & “OR” models are not sufficient
    • Speed limiting defects
    • Frequency of bridging defects is increasing
    • Need to drive ATE & modeling requirements from the defects to be detected
    • Will drive need for more scan vectors
    [M. Rodgers , et. al. DAC 2000] 1 10 100 1000 K-Ohms .18 um .25 um Test chip FA results Bridge Defect Observed Resistance Increasing defect populations causing more V DD , Temp, & freq sensitive device fails
  • Quality requirements Y 1 - Y p 1 - p Faults detected shipment Escapes
  • Quality requirements p Yield = 0.1 Yield = 0.9 Escapes = (1 - Y)(1 - p)
  • Fault models
    • Stuck-at-0 and stuck-at-1
    • Transitions
    • Path delay
    • Multiple detects
  • Very high test quality
    • Very high fault coverage
    • Wide range of fault models
      • stuck-at
      • transition
      • path delay
      • at-speed testing
      • multiple detects
      • bridging
      • defect based
      • cross-talk effects
      • ... fading IDDQ
    Coverage Escapes
  • High-performance MPU/ASIC gate count ITRS Roadmap 2001 Gate count
  • Scan chains
    • The pattern count for transition faults may reach 20,000
  • Scan test ATE Scan input channels Primary outputs Scan output channels Primary inputs
  • ATE cost Tester cost = b +  m p b - base cost (zero pins) m - incremental cost per pin p - number of pins Test cost can be $0.05/second High performance ASIC / MPU DFT tester Low performance Microcontroller 250 - 400 100 - 350 200 - 350 2700 - 6000 150 - 650 1200 - 2500 512 512 - 2500 256 - 1024 b [ K$ ] m [ $ ] p
  • Volume of scan test data Test cycles =  Patterns Scan cells Scan chains ...
  • Scan test time Test time = Scan cells Scan chains  ... Frequency Patterns
  • Scan test cost More Shift frequency 20 MHz Gate count 10M Scan chains 32 Padding ratio 1.4 Scan patterns 20K Vector memory 64MV Reload penalty 2s Insertions 4 Tester rate 0.05$ Scan cells 500,000 Cells per scan 15,625 Longest scan chain 21,875 Cycles 437.5M Scan test time 21.9s Passes 6 Reload time 12.0s Time pre device 87.5s Cost per device 4.4$
  • High-performance MPU/ASIC 32 channels 20,000 patterns Required ATE memory Gigabits/channel
  • High-performance MPU/ASIC 100 MHz scan shift Scan test time seconds
  • ATE accuracy vs. device speed
    • Tester accuracy will improve from 200 ps to 175 ps by 2012
    • Clock period will decrease to 330 ps
    • Margin of error for ATE approaches 50% clock period
    Device period ATE accuracy Accuracy required
  • Requirements for Embedded Test
    • Increasing device complexity, operating speed, and new fault models stress conventional scan based test:
      • Exploding volume of test data
      • Increasing scan test time, and
      • Escalating scan test cost
    • Embedded Test is required to:
      • Generate most of the test data on-chip
      • Compacting test responses on-chip, and
      • Providing on-chip control for at-speed test
  • Very low cost
    • Dramatically reduced volume of test data (10-100X)
    • Dramatically reduced scan test time (10-400X)
    ATE Memory [ Mvectors] Scan test time[s] 2M gates Scan/ATPG 16 scan chains 5k vectors 2s handler/index time 1 test 10MHz scan shift 10 X 10X
  • Long term scalability 100 X increase in 10 years! Volume in conventional DFT years
  • Radical compression is required!
    • Immediate 5-10X compression
    • Compression ahead of volume for 10 years
    Volume in conventional DFT Compression factor years
  • Radical compression is required
    • Compression should be ahead of Moore’s law for 10 years!
    Volume in conventional DFT Compression factor Compressed volume years