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MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
MODULE 5: MAIN MEMORY Type of Main Memory
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MODULE 5: MAIN MEMORY Type of Main Memory

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  • 1. MODULE 5: MAIN MEMORY
  • 2. Type of Main Memory <ul><li>2 main type </li></ul><ul><ul><li>R ead O nly M emory (ROM) </li></ul></ul><ul><ul><ul><li>contents are not lost </li></ul></ul></ul><ul><ul><ul><li>also called non-volatile memory </li></ul></ul></ul><ul><ul><li>R andom A ccess M emory (RAM) </li></ul></ul><ul><ul><ul><li>contents of memory are lost if the machine is switched off </li></ul></ul></ul><ul><ul><ul><li>Also called volatile memory </li></ul></ul></ul>
  • 3. Type of ROM <ul><li>P rogrammable ROM (PROM) </li></ul><ul><ul><li>Programmed after manufacture </li></ul></ul><ul><ul><li>Once they are programmed, cannot be changed ( O ne T ime P rogrammable) </li></ul></ul><ul><li>E rasable P rogrammable ROM (EPROM) </li></ul><ul><ul><li>can be erase by exposing to Ultraviolet (UV) radiation for a few minutes </li></ul></ul><ul><ul><li>can be reprogrammed </li></ul></ul><ul><li>E lectrically E rasable and P rogrammable ROM (EEPROM) </li></ul><ul><ul><li>Erase electrically not UV </li></ul></ul><ul><ul><li> No need to take out the IC to erase </li></ul></ul><ul><li>Flash memory </li></ul><ul><ul><ul><li>Erase whole memory electrically </li></ul></ul></ul>
  • 4. ROM Usage <ul><li>Permanent storage </li></ul><ul><ul><li>Nonvolatile </li></ul></ul><ul><li>Microprogramming (see later) </li></ul><ul><li>Library subroutines </li></ul><ul><li>Systems programs (BIOS) </li></ul><ul><li>Function tables </li></ul>
  • 5. TYPE OF RAM <ul><li>There are 3 basic types of RAM </li></ul><ul><ul><li>D ynamic RAM (DRAM) </li></ul></ul><ul><ul><ul><li>Commonly used as main memory </li></ul></ul></ul><ul><ul><ul><li>Use capacitor to store data, 1- charged, 0 – discharged </li></ul></ul></ul><ul><ul><ul><li>Capacitor will lose it charge with time  need to recharge (refresh) </li></ul></ul></ul><ul><ul><li>S tatic RAM (SRAM) </li></ul></ul><ul><ul><ul><li>Using flip-flop to store data – no need refresh </li></ul></ul></ul><ul><ul><ul><li>Compare to DRAM – faster but more expensive, </li></ul></ul></ul><ul><ul><ul><li>more complex and low capacity </li></ul></ul></ul><ul><ul><li>N on- v olatile RAM (NVRAM) </li></ul></ul><ul><ul><ul><li>RAM that is not volatile </li></ul></ul></ul><ul><ul><ul><li>use internal power source to keep data in RAM during power off </li></ul></ul></ul>
  • 6. Memory: Comparison
  • 7. Dynamic RAM (DRAM) <ul><li>Bits stored as charge in capacitors </li></ul><ul><li>Charges leak </li></ul><ul><li>Need refreshing even when powered </li></ul><ul><li>Simpler construction </li></ul><ul><li>Smaller per bit </li></ul><ul><li>Less expensive </li></ul><ul><li>Need refresh circuits </li></ul><ul><li>Slower </li></ul><ul><li>Main memory </li></ul><ul><li>Essentially analogue </li></ul><ul><ul><li>Level of charge determines value </li></ul></ul>
  • 8. Static RAM (SRAM) <ul><li>Bits stored as on/off switches </li></ul><ul><li>No charges to leak </li></ul><ul><li>No refreshing needed when powered </li></ul><ul><li>More complex construction </li></ul><ul><li>Larger per bit </li></ul><ul><li>More expensive </li></ul><ul><li>Does not need refresh circuits </li></ul><ul><li>Faster </li></ul><ul><li>Cache </li></ul><ul><li>Digital </li></ul><ul><ul><li>Uses flip-flops </li></ul></ul>
  • 9. SRAM v DRAM <ul><li>Both volatile </li></ul><ul><ul><li>Power needed to preserve data </li></ul></ul><ul><li>Dynamic cell </li></ul><ul><ul><li>Simpler to build, smaller </li></ul></ul><ul><ul><li>More dense </li></ul></ul><ul><ul><li>Less expensive </li></ul></ul><ul><ul><li>Needs refresh </li></ul></ul><ul><ul><li>Larger memory units </li></ul></ul><ul><li>Static </li></ul><ul><ul><li>Faster </li></ul></ul><ul><ul><li>Cache </li></ul></ul><ul><ul><li>More expensive </li></ul></ul>
  • 10. Synchronous DRAM (SDRAM) <ul><li>Access is synchronized with an external clock </li></ul><ul><li>Address is presented to RAM </li></ul><ul><li>RAM finds data (CPU waits in conventional DRAM) </li></ul><ul><li>Since SDRAM moves data in time with system clock, CPU knows when data will be ready </li></ul><ul><li>CPU does not have to wait, it can do something else </li></ul><ul><li>Burst mode allows SDRAM to set up stream of data and fire it out in block </li></ul><ul><li>DDR-SDRAM sends data twice per clock cycle (leading & trailing edge) </li></ul>
  • 11. Synchronous DRAM (SDRAM)
  • 12. DDR SDRAM <ul><li>SDRAM can only send data once per clock </li></ul><ul><li>Double-data-rate SDRAM can send data twice per clock cycle </li></ul><ul><ul><li>Rising edge and falling edge </li></ul></ul>
  • 13. Main Memory Capacity <ul><li>Memory locations/words can be grouped into block. </li></ul><ul><li>  Memory capacity usually measured in bits: </li></ul><ul><ul><li>Total no. of memory locations/words * size of memory word </li></ul></ul>
  • 14. Main Memory Capacity Example A <ul><li>Main memory is divided into blocks. </li></ul><ul><li>If a memory word is 8 bit and the size of a block is 8 words. </li></ul>
  • 15. Main Memory Capacity Example A <ul><li>What is the capacity of the main memory, if the total number of blocks in the memory is 128. </li></ul><ul><ul><li>128 blocks * 8 words * 8 bits = 2 7 * 2 3 * 2 3 = 2 13 = 1K * 8 = 8 Kbit </li></ul></ul><ul><li>  How many blocks in the main memory if the memory capacity is 32 Kbit. </li></ul><ul><ul><li>Total number of words = 32 Kbit / 8 bit = 2 15 / 2 3 = 2 12 words </li></ul></ul><ul><ul><li>Total number of blocks = 2 12 word / 8 words = 2 12 / 2 3 = 2 9 = 512 blocks </li></ul></ul>
  • 16. <ul><li>Main memory contains 8K blocks of 512 words each. Each word is 8 bit (1 byte). </li></ul><ul><ul><li>Memory capacity </li></ul></ul><ul><ul><li>= 512 * 8K = 4096 Kbytes (4096 Kwords) </li></ul></ul><ul><ul><li>= 4096 x 8 Kbit = 2 12 X 2 3 X 2 10 bit =2 5 X 2 20 bit = 32 Mbit </li></ul></ul>Main Memory Capacity Example B
  • 17. Memory Interleaving <ul><li>Organize memory chips in modules/banks and issue memory requests to all banks at the same time. </li></ul><ul><li>Hence if you buy memory to upgrade you buy a Memory Module/Bank. </li></ul><ul><li>Access is more efficient when memory is organized into banks of chips with the addresses interleaved across the chips </li></ul><ul><li>Low-order interleaving, the low order bits of the address specify which memory bank contains the address of interest. </li></ul><ul><li>High-order interleaving, the high order address bits specify the memory bank/module. </li></ul>
  • 18. Memory Interleaving <ul><li>Memory Banks/Modules </li></ul><ul><li>Memory usually implemented in module/interleave (SIMM and DIMM) </li></ul><ul><li>SIMM is single in-line memory module while DIMM is dual in-line memory module. A DIMM (dual in-line memory module) is a double SIMM. </li></ul>
  • 19. Low-Order Interleaving (LOI) Address Format n bits word in the bank/module ( n-m ) bits bank/module address m bits Module 0 0 4 8 12 Module 1 1 5 9 13 Module 2 2 6 10 14 Module 3 3 7 11 15
  • 20. Example 1 60 M0 4 0 63 M3 7 3 61 M1 5 1 62 M2 6 2 0001 00 0000 00 1111 00 0001 01 0000 01 1111 01 0001 10 0000 10 0001 11 0000 11 1111 10 1111 11 These bits are same in all 4 modules. Since these are low order bits, therefore its called LOI Memory capacity = 64 or 2 6  no of address bit = 6 Total main module/bank = 4 or 2 2  2 bits to address module/bank No of bits for word in module/bank = 6 – 2 = 4  module/bank capacity = 2 4 = 16
  • 21. Example 2 <ul><li>Given a memory address as 29Ch (10 bits) and there are 4 memory banks/modules. Determine the memory bank/module address and the address of the word in the bank/module. </li></ul><ul><li>Memory address = 29Ch = 1010 0111 00 </li></ul><ul><li>There are 4 memory banks/modules  2 2  2 bit for the banks/modules address. </li></ul>1010 0111 00
  • 22. Example 2 M0 (00) M1 (01) M2 (10) M3 (11) 0 1 2 3 No of bits for word in module/bank = 10-2=8, module/bank capacity is 2 8 = 256 Memory bank/module address = 00 Address of the word in the bank/module = 1010 0111 = A7h 000h 3FFh 0A7h 003h 3FCh 1020 1021 1022 1023 0000 0000 00 b 1111 1111 00 b 1111 1111 11 b 0000 0000 11 b
  • 23. Advantages & Disadvantages (LOI) <ul><li>Advantages </li></ul><ul><ul><li>It produces memory interference. </li></ul></ul><ul><li>Disadvantages </li></ul><ul><ul><li>A failure of any single module would be catastrophic to the whole system. </li></ul></ul>
  • 24. High-Order Interleaving (HOI) Address Format n bits bank/module address m bits word in the bank/module ( n-m ) bits Module 0 0 1 2 3 Module 1 4 5 6 7 Module 2 8 9 10 11 Module 3 12 13 14 15
  • 25. Example 3 15 M0 0 63 M3 48 31 M1 16 47 M2 32 00 0001 00 0000 00 1111 01 0001 01 0000 01 1111 10 0001 10 0000 11 0001 11 0000 10 1111 11 1111 These bits are same in all 4 modules. Since these are high order bits, therefore its called HOI Memory capacity = 64 or 2 6  no of address bit = 6 Total main module/bank = 4 or 2 2  2 bits to address module/bank No of bits for word in module/bank = 6 – 2 = 4  module/bank capacity = 2 4 = 16
  • 26. Example 4 <ul><li>A main memory has 32 Mwords. There are 16 memory banks (modules). Draw the modular memory address format if the system is implemented with high-order interleaving. </li></ul><ul><li>Main memory has 32 Mwords  2 5 * Mwords = 2 5 * 2 20 = 2 25 </li></ul><ul><li>Therefore main memory address size = 25 bits </li></ul><ul><li>16 memory modules/banks  2 4 , module/bank address size = 4 bits </li></ul><ul><li>Word in the module/bank bits = 25 – 4 = 21 bits </li></ul>bank/module address word in the bank/module 4 bits 21 bits
  • 27. Advantages of HOI <ul><li>Easy memory extension by the addition of one or more memory modules to a maximum of M-1. </li></ul><ul><li>Provides better reliability, since a failed module affects only a localized area of the address space. </li></ul><ul><li>This scheme would be used w/o conflict problems in multiprocessors if the modules are partitioned according to disjoint or non-interleaving processes( programs should be disjoint for its success). </li></ul>
  • 28. Disadvantages of HOI <ul><li>Scheme will cause memory conflicts in case of pipelined, vector processors. The sequentiality of instructions and data to be placed in the same module. Since memory cycle time is much greater than pipelined clock time, a previous memory request would not have completed its access before the arrival of next request, thereby resulting in a delay. </li></ul><ul><li>Process interacting and sharing instructions and data in multiprocessor system will encounter considerable conflicts. </li></ul><ul><li>This technique is useful only in one single user system/ single user multitasking system. </li></ul>
  • 29. Error Correction <ul><li>Hard Failure </li></ul><ul><ul><li>Permanent defect </li></ul></ul><ul><li>Soft Error </li></ul><ul><ul><li>Random, non-destructive </li></ul></ul><ul><ul><li>No permanent damage to memory </li></ul></ul><ul><li>Detected using Hamming error correcting code </li></ul>
  • 30. Error Correcting Code Function

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