Memory structure and addressing .


Published on

  • Be the first to comment

No Downloads
Total views
On SlideShare
From Embeds
Number of Embeds
Embeds 0
No embeds

No notes for slide

Memory structure and addressing .

  1. 1. On Memory
  2. 2. A Different View <ul><li>Instead of RAMs and ROMs </li></ul><ul><li>Writability and Data Permanence </li></ul>
  3. 3. Basic Form
  4. 5. ROM & Comb. Function
  5. 6. EPROM (contrasted to OTP ROM)
  6. 7. EEPROM <ul><li>Erased using higher than normal voltage </li></ul><ul><li>Erased in seconds vis a vis minutes for EPROMs </li></ul><ul><li>Can be erased by words and not in entirety </li></ul><ul><li>In circuit programmable e.g. in telephones to store commonly dialed numbers </li></ul><ul><li>Read tens of nanosec – Write tens of micosec. </li></ul>
  7. 8. Flash Memory <ul><li>Uses same floating gate principle </li></ul><ul><li>Large blocks can be written/erased at a time </li></ul><ul><li>Digital camera/Set top boxes/cell phones etc. </li></ul><ul><li>Writing a single word is slower </li></ul>
  8. 9. <ul><li>Search for optimized density, power, fast readability, nonvolatility </li></ul><ul><li>Uses single transistor for a bit </li></ul><ul><ul><li>EEPROM employs two transistors </li></ul></ul><ul><li>Electrical erasability and writability </li></ul><ul><li>A flash memory cell is 30% smaller than a DRAM cell however write time is significantly higher compared to DRAM </li></ul><ul><li>Tunnel Oxide technology Intel ETOX </li></ul>Flash (contd.)
  9. 10. RAM Internals
  10. 11. SRAM and DRAM
  11. 12. Modern RAMs <ul><li>PSRAM (Pseudo Static RAM) </li></ul><ul><ul><li>DRAM with refreshing circuit built in </li></ul></ul><ul><ul><li>A bit slow compared to SRAM but a good optimization </li></ul></ul><ul><li>NVRAM </li></ul><ul><ul><li>Battery backed SRAM (10 yrs) </li></ul></ul><ul><ul><li>Writes done in nanosec. </li></ul></ul><ul><ul><li>More susceptible to bit changes due to noise </li></ul></ul><ul><ul><li>Another form uses Flash/EEPROM to store the contents of SRAM </li></ul></ul>
  12. 13. Composing Memory
  13. 14. Effect of Cache on System Performance
  14. 15. Let us assume that we are designing a small 2 Kbyte cache for our processor. With this cache, we have measured the miss rate to be 15%, meaning 15 out of every 100 accesses to the cache result in a miss on the average. The cost of going to main memory (i.e., the cost of memory access when there is a miss) is 20 cycles. Doubling the cache size improves the hit ratio to 93.5% and additional cycle to access the cache. Doubling further results in 94.4% hit rate. Effect??
  15. 16. Basic DRAM Architecture
  16. 17. Fast Page Mode DRAM (FP DRAM) A row is selected and the col. addresses are sequenced. A row is considered a page, consisting of multiple words. Each word has a sep. col. address. The sense amplifier buffers a page.
  17. 18. EDO DRAM (Extended Data Out DRAM) -- Extra output latch between the sense ampl. and output buffer -- allows overlap bet. Col. Select and previous data out -- saves one cycle over FP DRAM
  18. 19. <ul><li>FPM and EDO RAM controlled asynchronously by the processor or the memory controller. </li></ul><ul><li>A synchronous DRAM interface will eliminate a small amount of time (thus latency) that is needed by the DRAM to detect the ras/cas and rd/wr signals. DRAM latches information to and from the controller on the active edge of the clock signal </li></ul><ul><li>In addition to a lower latency I/O, after a proper page and column setup, an SDRAM may store the starting address internally and output new data on each active edge of the clock signal, as long as the requested data are consecutive memory locations. This is accomplished by adding a column address counter to the base DRAM architecture. This counter is seeded with a starting column address strobed in by the processor (or memory controller) and is thereafter incremented internally by the DRAM on each clock cycle. </li></ul>SDRAM
  19. 20. SDRAM Timing