Lecture Notes on ``Memory'' (PPT Slides)


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  • Lecture Notes on ``Memory'' (PPT Slides)

    1. 1. ENG241 Digital Design Week #11 Memory Systems
    2. 2. Week #11 Topics <ul><li>Random Access Memory </li></ul><ul><ul><li>Static RAM </li></ul></ul><ul><ul><li>Array of RAM ICs </li></ul></ul><ul><ul><li>Dynamic RAM </li></ul></ul><ul><ul><li>Types of Dynamic RAM </li></ul></ul><ul><li>Comparison </li></ul><ul><li>Larger Wider Memories </li></ul>Fall 2009 ENG241/Digital Design
    3. 3. Resources <ul><li>Chapter #9, Mano Sections </li></ul><ul><ul><li>9.1 Memory Definitions </li></ul></ul><ul><ul><li>9.2 Random Access Memory </li></ul></ul><ul><ul><li>9.3 SRAM Integrated Circuits </li></ul></ul><ul><ul><li>9.4 Array of SRAM ICs </li></ul></ul><ul><ul><li>9.5 DRAM ICs </li></ul></ul><ul><ul><li>9.6 DRAM Types </li></ul></ul>Fall 2009 ENG241/Digital Design
    4. 4. Memories in General <ul><li>Computers have two types of memory (i) RAM and (ii) ROM </li></ul><ul><li>RAM stands for Random Access Memory </li></ul><ul><ul><li>Static RAM usually used for Cache </li></ul></ul><ul><ul><li>Dynamic RAM used for Main Memory </li></ul></ul><ul><li>ROM stands for Read Only Memory </li></ul><ul><ul><li>ROM (or equivalent) used to store permanent programs in a computer system (booting) </li></ul></ul>Fall 2009 ENG241/Digital Design
    5. 5. Properties of Memory <ul><li>Volatile: Memory contents disappears if power turned off </li></ul><ul><ul><ul><li>Typical computer RAM </li></ul></ul></ul><ul><ul><ul><li>PDA (Personal Digital Assistant) </li></ul></ul></ul><ul><li>Nonvolatile: Contents of memory remain even if power turned off </li></ul><ul><ul><ul><li>ROM </li></ul></ul></ul><ul><ul><ul><li>PROM, EEPROM </li></ul></ul></ul><ul><ul><ul><li>Flash memories </li></ul></ul></ul><ul><ul><ul><li>Magnetic memories like disk, tape </li></ul></ul></ul>Fall 2009 ENG241/Digital Design
    6. 6. Memory Classifications Fall 2009 ENG241/Digital Design
    7. 7. Memory Hierarchy <ul><li>The design constraints on a computer memory can be summed up by three questions (i) How Much (ii) How Fast (iii) How expensive . </li></ul><ul><li>There is a tradeoff among the three key characteristics </li></ul><ul><li>A variety of technologies are used to implement memory system </li></ul><ul><li>Dilemma facing designer is clear  large capacity, fast, low cost!! </li></ul><ul><li>Solution  Employ memory hierarchy </li></ul>Fall 2009 ENG241/Digital Design registers Cache Main Memory Disk Cache Magnetic Disk Removable Media Cost Capacity Access Time Static Ram Static Ram Dynamic Ram
    8. 8. Fall 2009 ENG241/Digital Design Memory Static RAM Dynamic RAM Registers CPU Cache Controller Cache Memory PCI Controller DRAM EISA/PCI Bridge Controller Hard Drive Controller Video Adaptor PC Card 1 PC Card 2 SCSI Adaptor PC Card 3 Local CPU / Memory Bus Peripheral Component Interconnect Bus EISA PC Bus SCSI Bus Co-processor
    9. 9. RAM versus ROM <ul><li>RAM </li></ul><ul><ul><li>Read/write </li></ul></ul><ul><ul><li>Volatile </li></ul></ul><ul><ul><li>Faster access time </li></ul></ul><ul><ul><li>Variants </li></ul></ul><ul><ul><ul><li>SRAM </li></ul></ul></ul><ul><ul><ul><li>DRAM </li></ul></ul></ul><ul><ul><li>Application </li></ul></ul><ul><ul><ul><li>Variables </li></ul></ul></ul><ul><ul><ul><li>Dynamic memory allocation </li></ul></ul></ul><ul><ul><ul><li>Heaps, stacks </li></ul></ul></ul>Fall 2009 ENG241/Digital Design <ul><li>ROM </li></ul><ul><ul><li>Read only </li></ul></ul><ul><ul><li>Non-Volatile </li></ul></ul><ul><ul><li>Slower </li></ul></ul><ul><ul><li>Variants </li></ul></ul><ul><ul><ul><li>PROM,EPROM </li></ul></ul></ul><ul><ul><ul><li>EEPROM, FLASH </li></ul></ul></ul><ul><ul><li>Application </li></ul></ul><ul><ul><ul><li>Programs </li></ul></ul></ul><ul><ul><ul><li>Constants </li></ul></ul></ul><ul><ul><ul><li>Codes, e.t.c </li></ul></ul></ul>
    10. 10. Random Access Memories <ul><li>So called because it takes the same amount of time to address any particular part </li></ul><ul><li>Types of RAM </li></ul><ul><ul><li>Static RAM (SRAM), Fast, expensive </li></ul></ul><ul><ul><li>Dynamic RAM (DRAM), slow, cheap </li></ul></ul><ul><li>How is memory accessed? </li></ul><ul><ul><li>Address Lines, Data Lines </li></ul></ul><ul><ul><li>Control Signals (R/W, chip select, …) </li></ul></ul>Fall 2009 ENG241/Digital Design
    11. 11. Simple View of RAM <ul><li>Of some word size n=4,8,16 …. </li></ul><ul><li>Some capacity 2 k </li></ul><ul><li>k bits of address line, k=10,11,.. </li></ul><ul><ul><li>Maybe have read line </li></ul></ul><ul><ul><li>Have a write line </li></ul></ul>Fall 2009 ENG241/Digital Design
    12. 12. 1K x 16 memory <ul><li>Variety of sizes </li></ul><ul><ul><li>From 1-bit wide </li></ul></ul><ul><li>Issue is no. of pins </li></ul><ul><li>Memory size specified in bytes </li></ul><ul><ul><li>1K x 16 bit  2KB memory </li></ul></ul><ul><li>10 address lines and 16 data lines </li></ul>Fall 2009 ENG241/Digital Design
    13. 13. Chip Select and R/W Lines <ul><li>R/W Lines enable reading/writing </li></ul><ul><li>Usually a chip select line is used. </li></ul><ul><li>Why? </li></ul><ul><ul><li>To enable RAM chip to be accessed. </li></ul></ul>Fall 2009 ENG241/Digital Design
    14. 14. Memory: Writing <ul><li>Sequence of steps </li></ul><ul><ul><li>Setup address lines </li></ul></ul><ul><ul><li>Setup data lines </li></ul></ul><ul><ul><li>Activate write line (maybe a pos edge) </li></ul></ul><ul><li>The write cycle time is the maximum time from the application of the address to the completion of all internal memory operations required to store a word. </li></ul>Fall 2009 ENG241/Digital Design
    15. 15. Writing: Timing Waveforms <ul><li>CPU operates at 50 MHz (20 ns) </li></ul><ul><li>4 clock cycles to perform a write </li></ul>Fall 2009 ENG241/Digital Design
    16. 16. Memory: Reading <ul><li>Steps </li></ul><ul><ul><li>Setup address lines </li></ul></ul><ul><ul><li>Activate read line </li></ul></ul><ul><ul><li>Data available after specified amount of time </li></ul></ul><ul><li>Read cycle usually is shorter than write cycle. </li></ul>Fall 2009 ENG241/Digital Design
    17. 17. Reading <ul><li>CPU operates at 50 MHz (20 ns) </li></ul><ul><li>65 ns required for a read cycle </li></ul>Fall 2009 ENG241/Digital Design
    18. 18. Static RAM: Internal Structure Fall 2009 ENG241/Digital Design
    19. 19. Simplify Modeling using Latch <ul><li>Storage is modeled by an SR latch. </li></ul><ul><li>Control logic </li></ul><ul><li>One memory cell per bit </li></ul>Fall 2009 ENG241/Digital Design <ul><li>For select = 0, the stored content is held. </li></ul><ul><li>For select = 1, the stored content is determined by values on B and B’ </li></ul><ul><li>The outputs are gated by the select line also. </li></ul>
    20. 20. Bit Slice <ul><li>Cells connected to form 1 bit position </li></ul><ul><li>Word Select gates one latch from address lines </li></ul><ul><li>Note it selects Reads also </li></ul><ul><li>B (and B’) set by R/W, Data In and BitSelect </li></ul><ul><li>When R/W = 0 and BitSelect = 1, then if Data in = 1  the latch will be set (i.e. a 1 is written) </li></ul>Fall 2009 ENG241/Digital Design
    21. 21. Bit Slice can Become Module <ul><li>Basically bit slice is a one Dimensional array of memory </li></ul><ul><li>What type of hardware do we need to access one row at a time? </li></ul>Fall 2009 ENG241/Digital Design
    22. 22. 16 X 1 RAM <ul><li>4 address lines required to access 16 locations. </li></ul><ul><li>A Decoder is added to select the different words (each 1 bit wide). </li></ul><ul><li>For 16 words we need a 4-to-16 line Decoder </li></ul>Fall 2009 ENG241/Digital Design
    23. 23. Row/Column <ul><li>Practical memories contains thousands of words!! </li></ul><ul><li>If RAM gets large, there is a huge decoder </li></ul><ul><li>Also run into chip layout issues </li></ul><ul><li>How can we change the structure of Memory to solve this problem? </li></ul><ul><ul><li>Rearrange the memory into “2D” i.e., matrix layout </li></ul></ul>Fall 2009 ENG241/Digital Design
    24. 24. 16 X 1 as 4 X 4 Array <ul><li>Two decoders </li></ul><ul><ul><li>Row </li></ul></ul><ul><ul><li>Column </li></ul></ul><ul><li>Address just broken up </li></ul><ul><li>Not visible from outside </li></ul>Fall 2009 ENG241/Digital Design
    25. 25. 16 X 1 as 4 X 4 Array <ul><li>Employing 2 decoders instead of 1 row decoder is called coincident selection </li></ul><ul><li>Row Select and Column Select </li></ul><ul><li>A 3 A 2 A 1 A 0 =0000 will attempt to choose RAM cell 0. </li></ul>Fall 2009 ENG241/Digital Design
    26. 26. Change from 16x1 to 8 X 2 RAM <ul><li>Minor change in logic </li></ul><ul><li>Try addressing 011 on board </li></ul><ul><li>Cells 6,7 are chosen for reading or writing. </li></ul>Fall 2009 ENG241/Digital Design
    27. 27. A Single Row Decoder <ul><li>Imagine 32k x 8 = 256K bit memory </li></ul><ul><ul><li>15 address lines are required. </li></ul></ul><ul><li>One column layout would need 15-bit decoder with 32,768 outputs </li></ul><ul><ul><li>For a single decoder that would mean 32,800 gates </li></ul></ul><ul><ul><li>This is not practical! </li></ul></ul><ul><li>How about coincident selection? </li></ul>Fall 2009 ENG241/Digital Design
    28. 28. Coincident Selection <ul><li>A 32K X 8 contains 256 Kbits </li></ul><ul><li>A 15 bit address line is required. </li></ul><ul><li>To make the number of rows and columns equal, we take the square root of 256K, giving 512 = 2 9 </li></ul><ul><ul><li>A 9-to-512 decoder is required for the rows (9 address lines are fed to the Row Decoder). </li></ul></ul><ul><li>For the columns 512/8 = 64 = 2 6 </li></ul><ul><ul><li>A 6-to-64 line decoder is required for the columns (6 address lines are fed to the Column Decoder). </li></ul></ul><ul><li>Total number of gates is 512 + 64 = 608 (i.e. reducing the total gate count by more than 50!) </li></ul>Fall 2009 ENG241/Digital Design
    29. 29. SRAM Performance <ul><li>Current SRAMs have cycle times in low nanoseconds (say 2.5ns) </li></ul><ul><li>Used as cache (typically on-chip or off-chip secondary cache) </li></ul><ul><li>Sizes up to 256 Mbit or so for fast chips </li></ul>Fall 2009 ENG241/Digital Design
    30. 30. Larger/Wider Memories <ul><li>Made up from sets of chips </li></ul><ul><li>Consider a 64K by 8 RAM </li></ul><ul><ul><li>Note new symbols for sets of lines, 8 & 16 bits wide </li></ul></ul>Fall 2009 ENG241/Digital Design
    31. 31. Larger: 256k x 8 <ul><li>Connect all output data lines together (tristate) </li></ul><ul><li>Connect all input data line together </li></ul><ul><li>16 lines of address to fetch a word in any DRAM chip </li></ul><ul><li>How to select the specific DRAM chip? </li></ul>Fall 2009 ENG241/Digital Design
    32. 32. Larger <ul><li>Decoder for high-order 2 bits </li></ul><ul><ul><li>Selects chip </li></ul></ul><ul><ul><li>Look at selection logic </li></ul></ul><ul><ul><li>Address ranges </li></ul></ul>Fall 2009 ENG241/Digital Design
    33. 33. Wider – 64K X 16 Fall 2009 ENG241/Digital Design
    34. 34. Dynamic RAM <ul><li>Capacitor can hold charge </li></ul><ul><li>Transistor acts as gate </li></ul><ul><ul><li>No charge is a 0 </li></ul></ul><ul><ul><li>Can close switch & add charge to store a 1 </li></ul></ul><ul><li>Then open switch (disconnect) </li></ul>Fall 2009 ENG241/Digital Design
    35. 35. DRAM Cell Fall 2009 ENG241/Digital Design
    36. 36. Dynamic RAM (continued) Fall 2009 ENG241/Digital Design (a) (c) (f) (g) Select B T C DRAM cell To Pump (b) (d) (e) Stored 1 Stored 0 Write 1 Write 0 Read 1 Read 0
    37. 37. DRAM Characteristics <ul><li>Destructive Read </li></ul><ul><ul><li>When cell read, charge removed </li></ul></ul><ul><ul><li>Must be restored after a read </li></ul></ul><ul><li>Refresh </li></ul><ul><ul><li>Also, there’s steady leakage </li></ul></ul><ul><ul><li>Charge must be restored periodically </li></ul></ul><ul><li>DRAM are dense (lots of cells) so there are many address lines . </li></ul><ul><ul><li>To reduce the physical size of DRAM we can reduce the number of pins by applying the address lines serially in to parts (Row Address and then Column Address) </li></ul></ul>Fall 2009 ENG241/Digital Design
    38. 38. How DRAM Works Fall 2009 ENG241/Digital Design A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0
    39. 39. DRAM Logical Diagram Fall 2009 ENG241/Digital Design
    40. 40. DRAM Read Signaling <ul><li>Lower pin count by using same pins for row and column addresses </li></ul>Fall 2009 ENG241/Digital Design Delay until data available
    41. 41. DRAM Write Timing Fall 2009 ENG241/Digital Design
    42. 42. DRAM Refresh <ul><li>Many strategies </li></ul><ul><li>Logic on chip </li></ul><ul><li>Refresh counter and Refresh controller </li></ul><ul><li>Refresh counter is used to provide the address of the row of DRAM cell to be refreshed. </li></ul>Fall 2009 ENG241/Digital Design
    43. 43. CAS Before RAS <ul><li>Set column address </li></ul><ul><li>Apply CAS first (opposite of RW) </li></ul><ul><li>Then toggle RAS enough times to cycle through row addresses </li></ul><ul><li>On-board refresh counter applies the row addresses </li></ul>Fall 2009 ENG241/Digital Design CAS RAS Col Add Row Add Row Add Row Add Row Add
    44. 44. <ul><li>DRAM - Dynamic RAM </li></ul><ul><li>FPM RAM - Fast page-mode RAM </li></ul><ul><li>EDO RAM - Extended Data Out RAM </li></ul><ul><li>BEDO RAM - Burst Extended-data-out RAM </li></ul><ul><li>SDRAM - Synchronous Dynamic RAM </li></ul><ul><li>DDRRAM - Double Data Rate RAM </li></ul>DRAM Chip Types ENG3640 Fall 2009
    45. 45. Page Mode DRAM <ul><li>DRAMs made to read & write blocks </li></ul><ul><li>Example </li></ul><ul><ul><li>Assert RAS, leave asserted </li></ul></ul><ul><ul><li>Assert CAS multiple times to read sequence of data </li></ul></ul><ul><li>Similar for writes </li></ul>Fall 2009 ENG241/Digital Design
    46. 46. DRAM Evolution ENG3640 Fall 2009
    47. 47. Synchronous DRAM (SDRAM) ENG3640 Fall 2009 <ul><li>Double Data Rate SDRAM </li></ul><ul><li>Transfers data on both edges of the clock </li></ul>
    48. 48. Memory Technologies <ul><li>DRAM: Dynamic Random Access Memory </li></ul><ul><ul><li>upside : very dense (1 transistor per bit) and inexpensive </li></ul></ul><ul><ul><li>downside : requires refresh and often not the fastest access times </li></ul></ul><ul><ul><li>often used for main memories </li></ul></ul><ul><li>SRAM: Static Random Access Memory </li></ul><ul><ul><li>upside : fast and no refresh required </li></ul></ul><ul><ul><li>downside : not so dense and not so cheap </li></ul></ul><ul><ul><li>often used for caches </li></ul></ul>Fall 2009 ENG241/Digital Design
    49. 49. Summary <ul><li>RAMs with different characteristics </li></ul><ul><ul><li>For different purposes </li></ul></ul><ul><li>Static RAM </li></ul><ul><ul><li>Simple to use, small, expensive </li></ul></ul><ul><ul><li>Fast, used for cache </li></ul></ul><ul><li>Dynamic RAM </li></ul><ul><ul><li>Complex to interface, largest, cheap </li></ul></ul><ul><ul><li>Needs periodic refresh </li></ul></ul>Fall 2009 ENG241/Digital Design
    50. 50. Links <ul><li>Ram Guides (not very technical) </li></ul><ul><ul><li>http:// arstechnica.com/paedia/storage.html </li></ul></ul>Fall 2009 ENG241/Digital Design
    51. 51. Fall 2009 ENG241/Digital Design Extra Slides
    52. 52. Synchronous DRAM (SDRAM) <ul><li>Has a clock </li></ul><ul><li>Common type in PCs late-90s </li></ul><ul><li>Multiple banks </li></ul><ul><li>Pipelined </li></ul><ul><ul><li>Start read in one bank after another </li></ul></ul><ul><ul><li>Come back and read the resulting values one after another </li></ul></ul>Fall 2009 ENG241/Digital Design
    53. 53. Double Data RAM (DDRAM) <ul><li>Double Data Rate SDRAM </li></ul><ul><ul><li>Transfers data on both edges of the clock </li></ul></ul><ul><li>Currently popular </li></ul><ul><li>Attempt to alleviate the pinout problems </li></ul>Fall 2009 ENG241/Digital Design
    54. 54. Timing: 4M x 4 DRAM <ul><li>Say need to refresh every 64ms </li></ul><ul><li>Distributed refresh </li></ul><ul><ul><li>Spread refresh out evenly over 64ms </li></ul></ul><ul><ul><li>On a 4Mx4 DRAM  4096 rows </li></ul></ul><ul><ul><li>Refresh every 64ms/4096=15.6 us </li></ul></ul><ul><ul><li>Total time spent is 0.25ms, but spread </li></ul></ul><ul><li>Burst refresh </li></ul><ul><ul><li>Same 0.25ms, but all at once </li></ul></ul><ul><ul><li>May not be good in a computer system </li></ul></ul><ul><li>Refresh takes low % of total time </li></ul>Fall 2009 ENG241/Digital Design
    55. 55. Hydraulic Analogy Fall 2009 ENG241/Digital Design Storage Full (1) Empty (0) Pump fills tank to 1 value Pump drains tank to 0 value
    56. 56. Reading Fall 2009 ENG241/Digital Design Tank had a 1 value – raises water level Outside water begins at intermediate level (black wavy line) Tank had a 0 value – lowers water level
    57. 57. Static vs. Dynamic RAM <ul><li>SRAM vs. DRAM </li></ul><ul><li>DRAM stores charge in capacitor </li></ul><ul><ul><li>Disappears over short period of time </li></ul></ul><ul><ul><li>Must be refreshed </li></ul></ul><ul><li>SRAM easier to use </li></ul><ul><ul><li>Faster </li></ul></ul><ul><ul><li>More expensive per bit </li></ul></ul><ul><ul><li>Smaller sizes </li></ul></ul>Fall 2009 ENG241/Digital Design
    58. 58. DRAM Performance Specs <ul><li>Important DRAM Performance Considerations </li></ul><ul><ul><li>Random access time : time required to read any random single cell </li></ul></ul><ul><ul><li>Fast Page Cycle time : time required for page mode access ­­ read/write to memory location on the most recently ­ accessed page (no need to repeat RAS in this case) </li></ul></ul><ul><ul><li>Extended Data Out (EDO): allows setup of next address while current data access is maintained </li></ul></ul><ul><ul><li>SDRAM ­ Burst Mode : Synchronous DRAMs use a self ­ incrementing counter and a mode register to determine the column address sequence after the first memory location accessed on a page ­­ effective for applications that usually require streams of data from one or more pages on the DRAM </li></ul></ul><ul><ul><li>Required refresh rate : minimum rate of refreshes </li></ul></ul>Fall 2009 ENG241/Digital Design
    59. 59. RAMBUS DRAM (RDRAM) <ul><li>Another attempt to alleviate pinout limits </li></ul><ul><li>Many (16-32) banks per chip </li></ul><ul><li>Made to be read/written in packets </li></ul><ul><li>Up to 400MHz bus speeds </li></ul><ul><ul><li>But DDR doing very well also </li></ul></ul>Fall 2009 ENG241/Digital Design
    60. 60. Burst Mode <ul><li>During initialization you specify length of data transfer (the burst length ) </li></ul><ul><li>During use, issue RAS, CAS, then you get a burst of data </li></ul><ul><li>Some DRAMs have multiple banks </li></ul><ul><li>Can overlap opening another bank with reading burst from current bank </li></ul>Fall 2009 ENG241/Digital Design
    61. 61. Read with Autoprecharge Fall 2009 ENG241/Digital Design
    62. 62. Bidirectional Lines <ul><li>Many chips have one set of data pins </li></ul><ul><li>Used as input for write </li></ul><ul><li>As output for read </li></ul><ul><li>Tri-state </li></ul><ul><li>Makes sense because don’t need both at once </li></ul>Fall 2009 ENG241/Digital Design