Lecture 3

793 views
706 views

Published on

0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total views
793
On SlideShare
0
From Embeds
0
Number of Embeds
5
Actions
Shares
0
Downloads
11
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide
  • Startup cost -> startup time
  • Lecture 3

    1. 1. DSP Architecture Differences and Examples of Embedded Computers Lecture 3 January 18, 2005 EENG 449b / CPSC 439b Computer Systems Andreas Savvides [email_address] Office: AKW 212 Tel 432-1275 Course Website http://www.eng.yale.edu/enalab/courses/2005s/eeng449b
    2. 2. Recap: 5 Steps of MIPS Datapath Memory Access Write Back Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc L M D MUX Memory Reg File MUX MUX Data Memory MUX Sign Extend Zero? Next SEQ PC Next PC WB Data RD RS1 RS2 Imm ALU 4 Adder Address Inst
    3. 3. How do DSP Processors Differ? <ul><li>Designed for high performance, repetitive numerical intensive tasks </li></ul><ul><li>Distinct features: </li></ul><ul><ul><li>Single cycle multiply accumulated instructions (MAC) </li></ul></ul><ul><ul><ul><li>Useful for digital filters, FFTs, correlation computations </li></ul></ul></ul><ul><ul><li>Several memory accesses in the same cycle </li></ul></ul><ul><ul><li>One or more address generation units </li></ul></ul>
    4. 4. An example DSP processor datapath
    5. 5. Specialized Addressing Modes <ul><li>Register indirect addressing with post increment </li></ul><ul><ul><li>In MIPs we have add R4, (R1) </li></ul></ul><ul><ul><li>How would it be in DSP? </li></ul></ul><ul><li>Modulo addressing </li></ul><ul><li>Bit-reverse addressing => FFT </li></ul><ul><ul><li>FFTs algorithms shuffle their addressing </li></ul></ul><ul><ul><ul><li>Eg 0,1,2,3,4,5 is accessed 0,4,2,6,1,5 </li></ul></ul></ul>
    6. 6. Specialized I/O Handling Mechanisms <ul><li>DSPs need to get a lot of data from outside world </li></ul><ul><ul><li>Cameras, celphones, MP3 Players </li></ul></ul><ul><li>Acquire data w/o processor interruption </li></ul><ul><ul><li>Specialized interrupt schemes </li></ul></ul><ul><ul><li>DMA transfer units, specialized serial and parallel ports </li></ul></ul><ul><ul><li>Mutliport memories and independent memory banks </li></ul></ul><ul><ul><li>Multiple on chip buses </li></ul></ul><ul><li>Tools disadvantages: general purpose processors have more tools available. </li></ul>
    7. 7. DSP Design Choices <ul><li>Arithmetic format </li></ul><ul><ul><li>Fixed Point vs. Floating Point </li></ul></ul><ul><ul><li>Fixed point: numbers are integers or fractions in fixed range </li></ul></ul><ul><ul><li>Floating point: </li></ul></ul><ul><ul><ul><li>Exponent and mantissa </li></ul></ul></ul><ul><ul><ul><li>Mantissa x 2 exponent </li></ul></ul></ul><ul><li>Fixed vs. floating point tradeoffs? </li></ul>
    8. 8. DSP Data Widths & Speed <ul><li>Floating point; mostly 32-bit </li></ul><ul><li>Fixed point: 16-bit </li></ul><ul><li>Speed factor: </li></ul><ul><ul><li>Clock speed does not tell the whole story </li></ul></ul><ul><ul><li>MIPS is the common metric </li></ul></ul><ul><ul><li>Some DSPs use a VLIW architecture </li></ul></ul>
    9. 9. Harvard vs. Von Neumann
    10. 10. Software Development Path
    11. 11. An Example Microcontroller OKI ML67Q5002 (Not a DSP!) <ul><li>OKI ML67Q5002 </li></ul><ul><ul><li>32-bit ARM7TDMI core (16-bit THUMB mode) </li></ul></ul><ul><ul><li>Built-in memory: </li></ul></ul><ul><ul><ul><li>SRAM 32Kbytes </li></ul></ul></ul><ul><ul><ul><li>Boot ROM 4Kbytes </li></ul></ul></ul><ul><ul><ul><li>FLASH memory 256Kbytes </li></ul></ul></ul><ul><ul><li>Provided interfaces: </li></ul></ul><ul><ul><ul><li>4 channels of 10-bit resolution ADC. </li></ul></ul></ul><ul><ul><ul><li>DMA support. </li></ul></ul></ul><ul><ul><ul><li>SPI, SIO, I2C, UART, PWM interfaces </li></ul></ul></ul><ul><ul><ul><li>42 configurable GPIO pins </li></ul></ul></ul><ul><ul><ul><li>Variety of external and internal configurable interrupts </li></ul></ul></ul><ul><ul><ul><li>6 hardware timers </li></ul></ul></ul>
    12. 12. <ul><li>Features </li></ul><ul><li>ARM7TDMI </li></ul><ul><li>ROM-less (ML675001) </li></ul><ul><li>256KB MCP Flash (ML67Q5002) </li></ul><ul><li>512KB MCP Flash (ML67Q5003) </li></ul><ul><li>8KB Unified Cache </li></ul><ul><li>32KB RAM </li></ul><ul><li>Interrupts 25 + 1 FIQ </li></ul><ul><li>I2C (1-ch x master) </li></ul><ul><li>DMA (2-ch) </li></ul><ul><li>Timers (7 x 16-bit) </li></ul><ul><li>WDT (16-bit) </li></ul><ul><li>PWM (2 x 16-bit) </li></ul><ul><li>UART (2-ch)/ SIO (1-ch) </li></ul><ul><li>GPIO (5 x 8-bit) </li></ul><ul><li>ADC (4-ch x 10-bit) </li></ul><ul><li>up to 66MHz </li></ul><ul><li>-40 ~ +85  C </li></ul><ul><li>Package 144 LFBGA </li></ul><ul><li>144 QFP </li></ul>XYZ Computation: The OKI ARM ML675001/67Q5002/67Q5003 [Slide from OKI Semiconductor]
    13. 13. OKI ARM ML675001/67Q5002/67Q5003 ARM7TDMI
    14. 14. What does ARM7TDMI Mean? <ul><li>Based on an ARM7 core </li></ul><ul><ul><li>Von Neuman Architecture </li></ul></ul><ul><ul><ul><li>Same address and data bus </li></ul></ul></ul><ul><ul><li>Approximately 1.9 Clock cycles per instruction </li></ul></ul><ul><ul><li>T – Thumb architecture extension – 2 instruction sets </li></ul></ul><ul><ul><ul><li>ARM 32-bits </li></ul></ul></ul><ul><ul><ul><li>Thumb 16-bits </li></ul></ul></ul><ul><ul><li>D – Core has debug extensions </li></ul></ul><ul><ul><li>M – Core had an enhanced multiplier (32x8) with instructions for 64-bit results </li></ul></ul><ul><ul><li>I – Core has EmbeddedICE Logic Extensions </li></ul></ul>
    15. 15. CPU States <ul><li>CPU can be either in ARM or THUMB states </li></ul><ul><ul><li>User can implicitly change the processor state from ARM to THUMB </li></ul></ul><ul><ul><li>All exception handling happens in ARM mode </li></ul></ul><ul><ul><li>If an exception happens during Thumb mode, the the processor transitions to ARM to execute the instruction and returns to THUMB at the end of the exception handler </li></ul></ul><ul><li>THUMB mode trades-off performance for code density </li></ul><ul><ul><li>Cheaper memory and lower power consumption for embedded systems </li></ul></ul>
    16. 16. FLASH Starts here External SRAM starts here Internal RAM starts here
    17. 17. MCU Basics: What are interrupts? <ul><li>Asynchronous breaks in the program execution </li></ul><ul><ul><li>Press of a button, expiration of a timer, DMA interrupt indicating the completion of a memory transfer </li></ul></ul><ul><li>When an interrupt occurs, the processor will transition to the corresponding interrupt handler to service the interrupt and then resume execution </li></ul><ul><li>The OKI processor has an 8-level interrupt priority mechanism </li></ul><ul><ul><li>Total of 24 types of interrupts that can happen during instruction execution </li></ul></ul><ul><ul><ul><li>1 fast external interrupt </li></ul></ul></ul><ul><ul><ul><li>4 external interrupts </li></ul></ul></ul><ul><ul><ul><li>19 Internal interrupts </li></ul></ul></ul><ul><ul><ul><ul><li>E.g System timer, watchdog timer, DMA interrupts etc </li></ul></ul></ul></ul><ul><li>The chip has mechanisms for dealing with interrupts </li></ul><ul><ul><li>Interrupts are enabled and disabled through registers for each peripheral </li></ul></ul>
    18. 18. Hardware Timers(16-bit) Controls the mode (interval or one-shot) Starts and stops the timer Enables/disables the interrutps for this timer Holds value to compare against Holds the value that initializes the timer at startup
    19. 19. Clock Divider
    20. 20. Steps in Setting up a Hardware Timer <ul><li>Example using hardware TIMER0 </li></ul><ul><li>Stop timer & disable interrupts by writing to control register (TIMECNTL0) </li></ul><ul><li>Write the timer starting value to the base register (TIMEBASE0) </li></ul><ul><li>Write the stop value in the compare register (TIMECOMP0) </li></ul><ul><li>Start the timer by writing to the control register (TIMECNTL0) </li></ul><ul><li>This will start the timer. An interrupt will occur when the counter register reaches the value of the compare register </li></ul><ul><li>Note: After the interrupt is handled, the status register (TIMESTAT0)needs to be cleared to use the timer again. </li></ul>
    21. 21. How to you access peripherals? <ul><li>You can access peripherals and GPIO by reading/writing registers </li></ul><ul><li>Typically one would write device drivers and then use higher level abstractions </li></ul><ul><li>You will need this knowledge to write device drivers for different peripherals and to assess the real-time capabilities of your software </li></ul>
    22. 22. Some platforms & applications <ul><li>Seismic monitoring, personal exploration rover, mobile micro-servers, networked info-mechanical systems, hierarchical wireless sensor networks </li></ul>[NIMS, UCLA] [Robotics, CMU] [Intel + UCLA] [CENS, UCLA] [Intel + UCLA] [Slide from V. Ragunanthan]
    23. 23. A Generic Sensor Node Architecture PROCESSING SUB-SYSTEM COMMUNICATION SUB-SYSTEM SENSING SUB-SYSTEM POWER MGMT. SUB-SYSTEM ACTUATION SUB-SYSTEM
    24. 24. Base Case: The Mica Mote (The most popular sensing platform today) AVR 128, 8-bit MCU DS2401 Unique ID 51-PIN I/O Connector Transmission Power Control Hardware Accelerators Radio Transceiver (CC1000 or CC2420) Power Regulation MAX1678(3V) Co-processor External Flash Digital I/O Analog I/O Programming Lines For more information refer to the TinyOS Website http://www.tinyos.net
    25. 25. What is Stargate? <ul><li>A single board, wireless-equipped computing platform </li></ul><ul><ul><li>Developed at Intel Research </li></ul></ul><ul><li>Leverages advances in computation, communication and storage to facilitate wireless systems research </li></ul>
    26. 26. System architecture
    27. 27. Computation sub-system <ul><li>PXA255 processor based on the XScale microarch. </li></ul><ul><ul><li>Successor to the StrongARM family </li></ul></ul><ul><ul><li>Variable clock (100 - 400 MHz), less than 500 mW power </li></ul></ul><ul><ul><li>Several sleep modes, rich set of peripherals </li></ul></ul>
    28. 28. Wireless DPM: Hierarchical radios <ul><li>Three vastly different wireless radios supported </li></ul><ul><li>Combined to form power-efficient, heterogeneous communication subsystem </li></ul><ul><ul><li>Hierarchical device discovery and connection setup scheme leads to up to 40X savings in discovery power </li></ul></ul>Energy per bit Startup time Idle current 160 mA 22 mA 7 mA Idle Current 802.11 Bluetooth Mote Technology Low 430 nJ/bit 10 mA 76.8 Kbps Medium 149 nJ/bit 45 mA 1 Mbps 90 nJ/bit Energy per bit 300 mA Tx Current High 11 Mbps Startup time Data Rate IEEE 802.11 Bluetooth Mote
    29. 29. Other power management features <ul><li>Wake on wireless: Bluetooth based remote wakeup </li></ul><ul><ul><li>BT module awake, rest of the system is shutdown </li></ul></ul><ul><ul><li>Incoming BT packet causes wakeup </li></ul></ul><ul><ul><li>On-demand power management (event-driven apps) </li></ul></ul><ul><ul><li>BT module in “wake on wireless” mode draws ~ 3mA </li></ul></ul><ul><li>Motion detection for wake up </li></ul><ul><ul><li>Passive small-bead mercury switch connected to GPIO </li></ul></ul><ul><ul><li>Movement causes switch to close and wakeup system </li></ul></ul><ul><ul><li>Can also be used to trigger wireless scanning for APs </li></ul></ul>
    30. 30. UCLA iBadge
    31. 31. iBadge Functional Units <ul><li>Main Processing Unit </li></ul><ul><ul><li>ATMega128L Microcontroller from Atmel </li></ul></ul><ul><ul><li>Responsible for power management, localization, and interfaces different functional units </li></ul></ul><ul><li>Localization Unit: </li></ul><ul><ul><li>Relative and absolute positioning </li></ul></ul><ul><ul><li>responsible for obtaining precise 3D location of iBadge in the classroom </li></ul></ul><ul><ul><li>estimate s its 3D location using an ad-hoc localization process </li></ul></ul><ul><li>Speech Processing Unit: </li></ul><ul><ul><li>Consists of TI DSP and CODEC </li></ul></ul><ul><ul><li>Performs speech codec and front end processing of the real time speech of the children </li></ul></ul><ul><ul><li>Two modes (Simple Coding or Front End Processing) of operation based on power requirements and user request. </li></ul></ul>
    32. 32. iBadge Functional Units (Continued) <ul><li>Power Management/Tracking Unit: </li></ul><ul><ul><li>Battery Monitors ( DS2438) keep track of energy usage of various functional units </li></ul></ul><ul><ul><li>CMOS switches provides control to turn on/off different part of the circuits </li></ul></ul><ul><li>Orientation/Tilt Sensing Unit </li></ul><ul><ul><li>Accelerometer combined with magnetometer provides the orientation of the children with earth’s magnetic field </li></ul></ul><ul><li>Environment Sensing Unit </li></ul><ul><ul><li>Temperature, Humidity, Atmospheric Pressure, and Light Intensity </li></ul></ul>
    33. 33. Telos: New OEP Mote* <ul><li>Single board philosophy </li></ul><ul><ul><li>Robustness, Ease of use, Lower Cost </li></ul></ul><ul><ul><li>Integrated Humidity & Temperature sensor </li></ul></ul><ul><li>First platform to use 802.15.4 </li></ul><ul><ul><li>CC2420 radio, 2.4 GHz, 250 kbps (12x mica2) </li></ul></ul><ul><ul><li>3x RX power consumption of CC1000, 1/3 turn on time </li></ul></ul><ul><ul><li>Same TX power as CC1000 </li></ul></ul><ul><li>Motorola HCS08 processor </li></ul><ul><ul><li>Lower power consumption, 1.8V operation , faster wakeup time </li></ul></ul><ul><ul><li>40 MHz CPU clock, 4K RAM </li></ul></ul><ul><li>Package </li></ul><ul><ul><li>Integrated onboard antenna +3dBi gain </li></ul></ul><ul><ul><li>Removed 51-pin connector </li></ul></ul><ul><ul><li>Everything USB & Ethernet based </li></ul></ul><ul><ul><li>2/3 A or 2 AA batteries </li></ul></ul><ul><ul><li>Weatherproof packaging </li></ul></ul><ul><li>Support in upcoming TinyOS 1.1.3 Release </li></ul><ul><li>Codesigned by UC Berkeley and Intel Research </li></ul><ul><li>Available February from Moteiv (moteiv.com) </li></ul><ul><li>*D. Culler, UC Berkeley </li></ul>
    34. 34. Yale’s XYZ Sensor Node <ul><li>Sensor node created for experimentation </li></ul><ul><ul><li>Low cost, low power, many peripherals </li></ul></ul><ul><ul><li>Integrated accelerometer, light and temperature sensor </li></ul></ul><ul><li>Uses an IEEE 802.15.4 protocol </li></ul><ul><ul><li>Chipcon 2420 radio </li></ul></ul><ul><li>OKI ARM Thumb Processor </li></ul><ul><ul><li>256KB FLASH, 32KB RAM </li></ul></ul><ul><ul><li>Max clock speed 58MHz, scales down to 2MHz </li></ul></ul><ul><ul><li>Multiple power management functions </li></ul></ul><ul><li>Powered with 3AA batteries & has external connectors for attaching peripheral boards </li></ul><ul><li>Designed at Yale Enalab and Cogent computer systems, will be used as the main platform for the course </li></ul>
    35. 35. XYZ ’s Architecture
    36. 36. XYZ : Communication Subsystem <ul><li>Chipcon CC2420 Zigbee RF Transceiver </li></ul><ul><ul><li>2.4 GHz IEEE 802.15.4 @ 250Kbps </li></ul></ul><ul><ul><li>Programmable output power </li></ul></ul><ul><ul><li>RX/TX data buffering </li></ul></ul><ul><ul><li>Digital RSSI support </li></ul></ul><ul><ul><li>DSSS modulation </li></ul></ul><ul><ul><li>Security features </li></ul></ul><ul><ul><ul><li>CTR encryption/decryption </li></ul></ul></ul><ul><ul><ul><li>CBC-MAC authentication </li></ul></ul></ul><ul><ul><ul><li>CCM encryption and authentication </li></ul></ul></ul><ul><ul><ul><li>All security operations are based on AES encryption using 128 bits </li></ul></ul></ul>
    37. 37. XYZ : Supervisor Circuitry & Low Power Sleep 2.5V 3.3V WAKEUP Enable Interrupt (SQW) DS1337 Real Time clock datasheet: http://pdfserv.maxim-ic.com/en/ds/DS1337.pdf <ul><li>Step 1 : The μ C selects the total time that wants to be turned off and programs the DS1337 accordingly, through the 2-wire serial interface. </li></ul><ul><li>Step 2 : The DS1337 turns-off the μ C and uses its own crystal to keep the notion of time. </li></ul><ul><li>Step 3 : The DS1337 wakes up the μ C after the programmed amount of time has elapsed. </li></ul><ul><li>Note that the DS1337 RTC can disable the voltage regulator and completely turn-off the sensor node! </li></ul>OKI μ C RTC DS1337 Voltage Regulator 3 x AA batteries I 2 C
    38. 38. XYZ : On Board Sensors A D C AIN0 AIN1 AIN2 X Y PIOE5(EXINT0) 2-axis accelerometer datasheet (ADXL202E): http://www.rotomotion.com/datasheets/ADXL202E_a.pdf Temperature Sensor datasheet (TMP05): http://www.analog.com/UploadedFiles/Data_Sheets/192632828TMP05_6_prk.pdf Light Sensor datasheet (TSL251R): http://www.goblack.de/desy/digitalt/sensoren/tsl-250/tsl250r.pdf Light Accelerometer Temperature OKI μ C
    39. 39. Current Efforts on XYZ Peripheral Boards <ul><li>Ragobots @ UCLA </li></ul><ul><li>Suspended nodes and camera support @ Yale, ENALAB </li></ul>
    40. 40. Manufacturers of Microcontroller Based Sensor Nodes <ul><li>Millenial Net ( www.millenial.com ) </li></ul><ul><ul><li>iBean sensor nodes </li></ul></ul><ul><li>Ember ( www.ember.com ) </li></ul><ul><ul><li>Integrated IEEE 802.15.4 stack and radio on a single chip </li></ul></ul><ul><li>Crossbow ( www.xbow.com ) </li></ul><ul><ul><li>Mica2 mote, Micaz, Dot mote and Stargate Platform </li></ul></ul><ul><li>Intel Research </li></ul><ul><ul><li>Stargate, iMote </li></ul></ul><ul><li>Dust Inc </li></ul><ul><ul><li>Smart Dust </li></ul></ul><ul><li>Cogent Computer ( www.cogcomp.com ) </li></ul><ul><ul><li>XYZ Node (CSB502) in collaboration with ENALAB@Yale </li></ul></ul><ul><li>Mote iv – Telos Mote </li></ul><ul><li>Sensoria Corporation (www.sensoria.com) </li></ul><ul><ul><li>WINS NG Nodes </li></ul></ul><ul><li>More…. </li></ul>
    41. 41. Other Sensor Node Projects <ul><li>Augmented off-the-shelf systems </li></ul><ul><ul><li>PC104 computers (used in some habitat monitoring applications) </li></ul></ul><ul><ul><li>iPAQ PDAs (used for prototypes @ UCLA/CENS) </li></ul></ul><ul><li>Networked Infomechanical Systems (NIMS) </li></ul><ul><ul><li>www.cens.ucla.edu </li></ul></ul><ul><li>Dedicated embedded sensor nodes and SOCs </li></ul><ul><ul><li>MIT uAMP nodes </li></ul></ul><ul><ul><li>(http://www-mtl.mit.edu/research/icsystems/uamps/) </li></ul></ul><ul><ul><li>Berkeley BWRC picoradio node (http://bwrc.eecs.berkeley.edu/Research/Pico_Radio) </li></ul></ul><ul><ul><li>ISI Pasta node ( http://pasta.east.isi.edu ) </li></ul></ul>
    42. 42. Typical Operating Characteristics for 4 classes of Sensor Nodes Source: J. Hill, M. Horton, R. King and L. Krishnamurthy,”The Platforms Enabling Wireless Sensor Networks”, Communications of the ACM June 2004
    43. 43. Power Perspective Comparison of Energy Sources With aggressive energy management, ENS might live off the environment. Source: UC Berkeley & CENS
    44. 44. Many ways to Optimize Power Consumption <ul><li>Power aware computing </li></ul><ul><ul><li>Ultra-low power microcontrollers </li></ul></ul><ul><ul><li>Dynamic power management HW </li></ul></ul><ul><ul><ul><li>Dynamic voltage scaling (e.g Intel’s PXA, Transmeta’s Crusoe) </li></ul></ul></ul><ul><ul><ul><li>Components that switch off after some idle time </li></ul></ul></ul><ul><li>Energy aware software </li></ul><ul><ul><li>Power aware OS: dim displays, sleep on idle times, power aware scheduling </li></ul></ul><ul><li>Power management of radios </li></ul><ul><ul><li>Sometimes listen overhead larger than transmit overhead </li></ul></ul><ul><li>Energy aware packet forwarding </li></ul><ul><ul><li>Radio automatically forwards packets at a lower level, while the rest of the node is asleep </li></ul></ul><ul><li>Energy aware wireless communication </li></ul><ul><ul><li>Exploit performance energy tradeoffs of the communication subsystem, better neighbor coordination, choice of modulation schemes </li></ul></ul>

    ×