lecture 1 -class outline-rules-year2.ppt


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  • lecture 1 -class outline-rules-year2.ppt

    1. 1. From Leading-Edge Advanced CMOS to Nanotechnology Devices EEL 4329 / EEL 5934 FALL 2006 Instructor Prof. Scott Thompson 535 Engineering Bldg 846-0320 [email_address] Office hours: M, W, F 7 th period (plus email for more) MWF 8 th period / NEB 102
    2. 2. What is Moore’s Law
    3. 3. Moore’s Law <ul><li>According to Moore: </li></ul><ul><li>~ 0.7X linear scale factor </li></ul><ul><li>2X increase in density / 2 years </li></ul><ul><li>Lower cost </li></ul><ul><li>Higher performance (~30% / 2 years) </li></ul><ul><li>At severe competitive disadvantage if don’t have newer technology </li></ul><ul><li>Has been going on for 40 years and will continue “somewhat” for another decade </li></ul>1 st signs of this being no longer valid is some markets
    4. 4. Pentium ® Processors in: 1993 1994 1995 0.8µm 0.6µm 0.35µm 1998 0.25µm 0.35µm 1997 1999 0.18µm
    5. 5. CLASS GOAL <ul><li>This class will expose the student to state of the art technology issues and industrial team problem solving. The class will provide links between the short-term topics, which will certainly be in production during the next 10 years such as nano-scale MOSFET, strained Si, high k gates to far-reaching topics, which are well ahead or off the main stream, offering high Potential . Some of these topics will include carbon nanotubes, molecular electronics and single electron devices for logic applications. </li></ul>
    6. 6. Relevance: <ul><li>At present silicon technology is “IT” however Moore’s Law will slow over the next decade and will have a profound effect on industry and university business and engineering jobs. The slowing should not be viewed as an end just a new phase in the $300B microelectronic industry were the rules of business change. </li></ul>
    7. 7. Relevance:
    8. 8. Gordon Moore on Moore’s Law and the future of Microelectronics <ul><li>Show Moore video </li></ul><ul><ul><li>Interviews by Grove, Barret, Mead </li></ul></ul><ul><li>Discussion of key takeaways </li></ul>
    9. 9. Grading <ul><li>Grading: Homework/team project assignments and team project. </li></ul><ul><li>Exams 85% </li></ul><ul><ul><ul><li>25% Exam 1: Sept 27 </li></ul></ul></ul><ul><ul><ul><li>25% Exam 2: Nov 3 </li></ul></ul></ul><ul><ul><ul><li>35% Final exam (Dec 12 10am – 12) </li></ul></ul></ul><ul><li>15% homework/real world semiconductor team research project </li></ul><ul><ul><ul><li>Class divided into ~ 10 groups </li></ul></ul></ul><ul><ul><ul><li>5 – 10 min group periodic report out </li></ul></ul></ul><ul><ul><ul><li>Final report </li></ul></ul></ul><ul><ul><ul><li>Part peer evaluation </li></ul></ul></ul>
    10. 10. Text book: Nanoelectronics and Information Technology Plus many handouts on CD ROM
    11. 11. Perquisite: <ul><li>Basic knowledge of semiconductor physics and devices (EEL 3396 or eq.). The class will be introductory and targeted towards students with a diverse background from electronics to material science. The class will be designed to introduce CMOS, non classical CMOS, and post CMOS device concepts without a quantum mechanical background. </li></ul>
    12. 12. Course Outline <ul><li>Week 1-2: Moore’s Law and microelectronic industry trends </li></ul><ul><li>Week 3: Logic device: State of the Art for a Si MOSFET </li></ul><ul><li>Week 4: Requirements for a logic device replacement </li></ul><ul><li>Week 5-6: CMOS devices limits: quantum-statistical </li></ul><ul><li>Week 7-11 Post CMOS logic device </li></ul><ul><li>- Multi-Gate CMOS </li></ul><ul><li>- Carbon nanotubes </li></ul><ul><li>- High level overview of Quantum Transport Devices </li></ul><ul><li>- Single electron devices for Logic applications </li></ul><ul><li>- Spintronics </li></ul><ul><li>Midterm exam: Oct 20th </li></ul><ul><li>Week 12-14 Memory devices </li></ul><ul><li>DRAM, ferroelectric, magneto resistive, and phase change RAM </li></ul><ul><li>Week 16: December 8th and 10th </li></ul><ul><li>Final exam: when scheduled by college </li></ul>
    13. 13. Course Material <ul><li>Week 1-6 </li></ul><ul><li>1.1: Introduction class / Video </li></ul><ul><ul><li>1.2: short 300mm fab vide: Moore on Moore’s law </li></ul></ul><ul><ul><li>1.3: Intel’s view on nanotechnology </li></ul></ul><ul><ul><li>2.1: IBM view on nanotechnology </li></ul></ul><ul><ul><li>2.2 Taur/Isaac papers </li></ul></ul><ul><ul><li>2.3 State of the art: MOSFET </li></ul></ul><ul><ul><li>3.1: Holiday </li></ul></ul><ul><ul><li>3.2: How work report out </li></ul></ul><ul><ul><li>3.3: How strain works / band structure and strain </li></ul></ul><ul><ul><li>4-6: Requirements and limits of devices </li></ul></ul>High level overview to put the material in perspective Equations and mathematics
    14. 14. CLASS / Team Project (assigned Mid Year) <ul><li>Compare post CMOS replacement device options to the MOSFET (most successful device technology) </li></ul><ul><li>Which if any post CMOS device options should the microelectronics focus on as a MOSFET replacement? </li></ul><ul><li>Recommendation should be based </li></ul><ul><ul><li>Historical and projected future MOSFET trends. </li></ul></ul><ul><ul><li>On quantum, statistical mechanics, and device limits. </li></ul></ul><ul><ul><li>Potential advantage of post CMOS device option. </li></ul></ul><ul><ul><li>Class homework will help shape project </li></ul></ul><ul><ul><li>Suggestions: Start with a good literature search. Use excellent free service of electronic journals on-line. Use Mathlab for calculations and graphs. </li></ul></ul><ul><li>Group divided into 10 Teams </li></ul>
    15. 15. Homework 1: <ul><li>Why has GaAs or 3-5 devices not “taken off” </li></ul><ul><li>Include </li></ul><ul><ul><li>Early history of GaAs—find interesting quotes (see who can find the best quotes) on GaAs potential </li></ul></ul><ul><ul><li>What markets is GaAs used today </li></ul></ul><ul><ul><li>What is it not replaceing CMOS </li></ul></ul><ul><li>Expectation </li></ul><ul><ul><li>Present 6-7 ppt slides for a “professional” presentation to class </li></ul></ul><ul><ul><li>~1 page report with references </li></ul></ul><ul><ul><li>Due Sep 11 th </li></ul></ul><ul><li>Can pick your own groups ~4-6 people/group </li></ul>n+ Source L GATE T OX Drain W
    16. 16. Course Material (papers provided on CD) <ul><li>Week 1: </li></ul><ul><li>Silicon MOSFET – Novel materials and Alternative concepts Ch-13 text book pages 361-385 </li></ul><ul><ul><li>(Skip operation of MOS capacitor / High K deposition </li></ul></ul><ul><li>Isaac paper: The Future of CMOS </li></ul><ul><li>Taur CMOS design near the limit of scaling </li></ul><ul><li>EEtimes nano technology article </li></ul><ul><li>Week 2: </li></ul><ul><li>Denard: Design of ion implanted MOSFET </li></ul><ul><li>Sustaining Moore’s Law and the US Economy </li></ul><ul><li>Week 3: </li></ul><ul><li>Intel 90nm Strained silicon </li></ul>
    17. 17. Course Material (papers on CD) <ul><li>Week 4-6: </li></ul><ul><li>Miendl- low power microelectronics </li></ul><ul><li>Limits to a binary switch </li></ul><ul><li>Book pages 323-357 (skip biological system) </li></ul><ul><li>Week 7-11: </li></ul><ul><li>Book chapters 19, 16 </li></ul><ul><li>Single electron devices and their application </li></ul><ul><li>Spintronics: a spin based electronics vision for the future </li></ul><ul><li>Week 12-16: </li></ul><ul><li>Book chapters 21-23 </li></ul><ul><li>Introduction to flash memory </li></ul>
    18. 18. Other <ul><li>Class attendance required. Class attendance/participation used to decide “close” grades (i.e. A or B+?) </li></ul><ul><li>No make-up exam/homework unless very good reason. See me. Will be handled on case by case basis </li></ul><ul><li>Student with disability: Students requesting classroom accommodation must first register with the Dean of Student Office. The Dean of Students Office will provide documentation to the student who must then provide this documentation to the instructor when requesting accommodations. </li></ul><ul><li>Expect on time to class. No cell phones </li></ul><ul><li>University honesty policy </li></ul>