LatticeMico32 Tutorial

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LatticeMico32 Tutorial

  1. 1. LatticeMico32 Tutorial Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro, OR 97124 (503) 268-8000 August 2007
  2. 2. Copyright Copyright © 2007 Lattice Semiconductor Corporation. This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine- readable form without prior written consent from Lattice Semiconductor Corporation. Trademarks Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L (stylized), L (design), Lattice (design), LSC, E2CMOS, Extreme Performance, FlashBAK, flexiFlash, flexiMAC, flexiPCS, FreedomChip, GAL, GDX, Generic Array Logic, HDL Explorer, IPexpress, ISP, ispATE, ispClock, ispDOWNLOAD, ispGAL, ispGDS, ispGDX, ispGDXV, ispGDX2, ispGENERATOR, ispJTAG, ispLEVER, ispLeverCORE, ispLSI, ispMACH, ispPAC, ispTRACY, ispTURBO, ispVIRTUAL MACHINE, ispVM, ispXP, ispXPGA, ispXPLD, LatticeEC, LatticeECP, LatticeECP-DSP, LatticeECP2, LatticeECP2M, LatticeMico8, LatticeMico32, LatticeSC, LatticeSCM, LatticeXP, LatticeXP2, MACH, MachXO, MACO, ORCA, PAC, PAC-Designer, PAL, Performance Analyst, PURESPEED, Reveal, Silicon Forest, Speedlocked, Speed Locking, SuperBIG, SuperCOOL, SuperFAST, SuperWIDE, sysCLOCK, sysCONFIG, sysDSP, sysHSI, sysI/O, sysMEM, The Simple Machine for Complex Design, TransFR, UltraMOS, and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. ISP, Bringing the Best Together, and More of the Best are service marks of Lattice Semiconductor Corporation. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium in the U.S. and other jurisdictions. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. LatticeMico32 Tutorial ii
  3. 3. Type Conventions Used in This Document Convention Meaning or Use Bold Items in the user interface that you select or click. Text that you type into the user interface. <Italic> Variables in commands, code syntax, and path names. Ctrl+L Press the two keys at the same time. Courier Code examples. Messages, reports, and prompts from the software. ... Omitted material in a line of code. . Omitted lines in code and report examples. . . [ ] Optional items in syntax descriptions. In bus specifications, the brackets are required. ( ) Grouped items in syntax descriptions. { } Repeatable items in syntax descriptions. | A choice between items in syntax descriptions. LatticeMico32 Tutorial iii
  4. 4. LatticeMico32 Tutorial iv
  5. 5. Contents LatticeMico32 Tutorial 1 Introduction 1 Learning Objectives 2 Time to Complete This Tutorial 2 System Requirements 2 Accessing Online Help 3 About the Tutorial Design 3 About the Tutorial Data Flow 3 LatticeMico32/DSP Development Board 6 Task 1: Creating a New ispLEVER Project 7 Task 2: Creating the Microprocessor Platform 9 Creating a New MSB Platform 9 Selecting the Microprocessor Core 14 Adding the Off-Chip Memory 16 Adding the Peripheral Components 18 Specifying the Connections Between Master and Slave Ports 20 Assigning Component Addresses 22 Assigning Interrupt Request Priorities 25 Performing a Design Rule Check 25 Generating the Microprocessor Platform 25 Task 3: Generating the Microprocessor Bitstream 29 Importing the Verilog File 29 Connecting the Microprocessor to the FPGA Pins 30 Performing Functional Simulation 31 Performing Timing Simulation 31 Generating the Bitstream 31 Task 4: Downloading the Hardware Bitstream to the FPGA 32 Task 5: Creating the Software Application Code 35 Creating a New C/C++ SPE Project 37 Selecting Linker Memory Settings 39 Compiling the Project 41 LatticeMico32 Tutorial v
  6. 6. Contents Task 6: Debugging and Executing the Software Application Code on the Development Board 45 Software Application Code Execution Flow 45 Debugging the Software Application Code on the Board 47 Inserting Breakpoints 54 Executing the Software Application Code 55 Modifying and Re-Executing the Software Application Code 58 Task 7: Deploying the Software Application Code to the Parallel Flash Memory 59 Parallel Flash Memory Deployment Flow 59 Creating a CFI Flash Programmer Application 62 Preparing LEDTest for Flash Deployment 64 Task 8: Deploying the Microprocessor Bitstream to SPI Flash Memory 71 Summary 73 Glossary 74 Recommended References 77 LatticeMico32 Tutorial vi
  7. 7. LatticeMico32 Tutorial Introduction This tutorial steps you through the basic process involved in using the LatticeMico32 System software to implement a soft microprocessor and attached components in a Lattice Semiconductor device for the LatticeMico32/DSP development board. LatticeMico32 System encompasses three tools: the Mico System Builder (MSB), the C/C++ Software Project Environment (C/C++ SPE), and the Debugger. Together, they enable you to build an embedded microprocessor system on a single FPGA device and to write and debug the software that drives it. Such a microprocessor lowers cost by saving board space and increases performance by reducing the number of external wires. The LatticeMico32 System interface is based on the Eclipse environment, which is an open-source development and application framework for building software. Although you can install LatticeMico32 System as a stand-alone tool, this tutorial assumes that you have installed ispLEVER before installing LatticeMico32 System. Once you create a project in ispLEVER, the tutorial shows you how to use MSB to choose a Lattice Semiconductor 32-bit microprocessor, attach components to it, and generate a top-level design, including the microprocessor and the chosen components. Next you will use ispLEVER to synthesize, map, place, and route the design and generate a bitstream for it. You then download this bitstream to the FPGA on the board. The tutorial continues by demonstrating how to use C/C++ SPE to write and compile the software application code that exercises the microprocessor and components. Finally, you learn how to download and debug the code on the board and deploy it in the parallel flash chips on the LatticeMico32/DSP development board. LatticeMico32 Tutorial 1
  8. 8. LatticeMico32 Tutorial Introduction This tutorial is intended for a new or infrequent user of the LatticeMico32 System software and covers only the basic aspects of it. The tutorial assumes that you have reviewed the LatticeMico32 Development Kit User’s Guide to familiarize yourself with the product and to set up your board correctly. For more detailed information on the LatticeMico32 System software, see the sources listed in “Recommended References” on page 77. Learning Objectives When you have completed this tutorial, you should be able to do the following: Use MSB to configure a Lattice Semiconductor 32-bit microprocessor for your design, select the desired components, and connect the selected components to the microprocessor. Import the Verilog file generated by MSB and an .lpf file containing the pinout. Synthesize, map, place, and route the design. Generate a bitstream of the microprocessor and download it to an FPGA on the board. Use C/C++ SPE to create the software application code that drives the microprocessor and components. Compile, download, and debug the software application code on the LatticeMico32/DSP development board. Program the Common Flash Interface (CFI) parallel flash memory with the software application code. Debug the hardware and software on the board. Time to Complete This Tutorial The time to complete this tutorial is about one hour. System Requirements Your PC system must meet the following minimum system requirements: Pentium II PC running at 400 MHz or faster Microsoft Windows 2000 or Windows XP Professional USB port for use with the LatticeMico32/DSP development board The following software is required to complete the tutorial: ispLEVER software with device support for the device used with your build of the LatticeMico32/DSP development board LatticeMico32 System evaluation tool chain for LatticeMico32, version 1.0 ispVM System software, which is included in the ispLEVER software This tutorial requires the following hardware: A LatticeMico32/DSP development board LatticeMico32 Tutorial 2
  9. 9. LatticeMico32 Tutorial Introduction USB cable AC adapter cord Accessing Online Help You can access the online Help for MSB, C/C++ SPE, the Debugger, or Eclipse Workbench by choosing Help > Help Contents in the LatticeMico32 System graphical user interface. About the Tutorial Design This tutorial uses a LatticeECP device. The tutorial design consists of the LatticeMico32 embedded microprocessor, a memory, a GPIO, a parallel flash memory, and a UART. After you add these components, you will specify the connections between the master and slave ports on these components, as shown in Figure 1. Figure 1: Desired Connections Between Master and Slave Ports SRAM slave device (memory for code and data) GPIO slave device (for controlling LEDs) Instruction LM32 CPU port Parallel flash (master ports) Data port memory (for deploying the application code) UART slave device (for host comunication) The instruction port (I) and the data port (D) of the CPU are the master ports. All other ports are slave ports. The instruction port will access the LatticeMico32 asynchronous SRAM controller and the LatticeMico32 parallel flash memory. The data port will access the LatticeMico32 asynchronous SRAM controller, the LatticeMico32 GPIO, the LatticeMico32 parallel flash memory, and the LatticeMico32 UART. About the Tutorial Data Flow You will perform the following major steps to create an embedded microprocessor system: 1. Create a new project in the ispLEVER Project Navigator. LatticeMico32 Tutorial 3
  10. 10. LatticeMico32 Tutorial Introduction 2. Create a microprocessor platform for the LatticeMico32 microprocessor in MSB. 3. Generate a bitstream of the microprocessor platform in ispLEVER and download it to the board with ispVM. 4. Download the hardware bitstream to the FPGA. 5. Write the software application code for the microprocessor platform in C/C++ SPE. 6. Debug and execute the software application code on the board. 7. Deploy the software application code in the parallel flash memory. 8. Deploy the microprocessor bitstream. Note This tutorial does not show you how to debug your software application code on the instruction set simulator, but it does show you how to debug the design by downloading the bitstream and the application code to the board. The design flow involved in using LatticeMico32 System to create an embedded microprocessor and the software code for it is shown in Figure 2. LatticeMico32 Tutorial 4
  11. 11. LatticeMico32 Tutorial Introduction Figure 2: LatticeMico32 System Design Flow MSB C/C++ SPE Create Configura- Create microprocessor tion (.msb) application code platform with MSB file with C/C++ SPE Top-level Test fixture simulation & (.v) file synthesis System .elf file Linker definition RTL (.v) files script (header) file ispLEVER Perform functional simulation in ispLEVER (optional) Synthesize, map, place, and route in ispLEVER Run/debug software C/C++ SPE Perform timing with instruction set Debugger simulation in simulator (ISS) (for ispLEVER (optional) software) (optional) Generate bitstream in Download .elf file ispLEVER to parallel flash memory or PROM Download bitstream to .bit file board with ispVM ispTRACY Run/debug (for hardware and SPE JTAG port Debugger hardware) software on board or UART (for software) Improve hardware and software LatticeMico32 Tutorial 5
  12. 12. LatticeMico32 Tutorial LatticeMico32/DSP Development Board LatticeMico32/DSP Development Board Figure 3 shows where some of the components mentioned in this tutorial reside on the LatticeMico32/DSP development board. Figure 3: The LatticeMico32/DSP Development Board LatticeMico32 Tutorial 6
  13. 13. LatticeMico32 Tutorial Task 1: Creating a New ispLEVER Project Task 1: Creating a New ispLEVER Project As a first step, you will create a new project in ispLEVER. To create a new ispLEVER project: 1. In the following directory, create a folder called lm32_tutor: <ispLEVER_install_path>examplesTutorial 2. On your PC desktop, choose Start > Programs > Lattice Semiconductor > ispLEVER Project Navigator. 3. In the Project Navigator, select File > New Project to open the Project Wizard dialog box. 4. In the Project Wizard dialog box, shown in Figure 4, select or specify the following: a. In the Project Name box, enter platform1. b. In the Location box, enter the following directory: <ispLEVER_install_path>examplesTutoriallm32_tutor c. In the Design Entry Type box, select Verilog HDL. d. In the Synthesis Tools box, select Synplify. e. In the Simulator Tools box, select ModelSim. f. Click Next. Note If you want to preserve the original tutorial design files, save the lm32_tutor directory to another location on your computer before proceeding. Figure 4: Project Wizard Dialog Box LatticeMico32 Tutorial 7
  14. 14. LatticeMico32 Tutorial Task 1: Creating a New ispLEVER Project 5. In the Project Wizard - Select Device dialog box, shown in Figure 5, do the following: a. In the Family box, choose LatticeECP. b. In the Device box, choose LFECP33E. c. In the Speed grade box, choose -4. d. In the Package Type box, choose FPBGA484. e. In the Operating Conditions box, choose Commercial. f. Click Next to open the Project Wizard - Add Source dialog box. Figure 5: Project Wizard - Select a Device Dialog Box 6. In the Project Wizard - Add Source dialog box, click Next. 7. In the Project Wizard - Project Information box, click Finish. The Project Navigator looks like the illustration shown in Figure 6. Note Click on the part name, LFECP33E-4F484C, in the Sources in Project pane to see the contents of the Processes for Current Source pane. LatticeMico32 Tutorial 8
  15. 15. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform Figure 6: Project Navigator Task 2: Creating the Microprocessor Platform You use MSB to create the microprocessor platform, which is the embedded microprocessor in a system-on-a-chip (SoC) design and the attached components, buses, component properties, and their connectivity. The microprocessor platform also specifies the parameters that customize the microprocessor and the attached components. Creating a New MSB Platform Now you will create a new platform in MSB. To create a new platform: 1. Select Tools > LatticeMico32 System from the Project Navigator or click . LatticeMico32 Tutorial 9
  16. 16. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform The Workspace Launcher dialog box now appears, as shown in Figure 7. Figure 7: Workspace Launcher The LatticeMico32 System interface that you are about to open stores in a workspace folder the preferences and options that you set in its interface tabs. In the Select Workspace dialog box, you must specify the name and location of this folder. Each instance of the interface has its own workspace folder. If you already have one or more LatticeMico32 System applications open and want to open another one, you must specify in the Select Workspace dialog box a workspace folder different from that of the previous interface instances. The workspace directory is not the same directory in which you store the files generated by the tutorial. 2. In the Workspace box, specify the location of the workspace directory. 3. If you want the directory that you just specified to be the default, select the Use this as the default and do not ask again box. 4. Click OK. LatticeMico32 Tutorial 10
  17. 17. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform The LatticeMico32 System interface now appears, as shown in Figure 8. Figure 8: LatticeMico32 System Interface 5. In the upper left-hand corner of the graphical user interface, select MSB, if it is not already selected, to open the MSB perspective. 6. Choose File > New Platform. 7. In the New Platform Wizard dialog box, do the following: a. In the Platform Name box, enter platform1. b. In the Directory box, browse to the following directory and click OK: <ispLEVER_install_path>examplesTutoriallm32_tutor c. In the Device Family box, select ECP from the pull-down menu. d. In the Platform Templates box, select blank. Templates are pre-created platforms that facilitate rapid development. They target the LatticeMico32/DSP development board. Each platform also has an associated constraint file that you can import into ispLEVER to avoid the effort of creating a constraints file. MSB gives you the flexibility of creating and adding your own custom templates and associated constraints files for the LatticeMico32/DSP LatticeMico32 Tutorial 11
  18. 18. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform development board or a custom board, in addition to using the templates provided as part of the installation package. The New Platform Wizard dialog box should look like the illustration in Figure 9. Figure 9: New Platform Wizard Dialog Box e. Click Finish. LatticeMico32 Tutorial 12
  19. 19. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform The MSB perspective now appears, as shown in Figure 10. Figure 10: MSB Perspective Available Editor Components view view Console view Component or Component Attributes Help view view The MSB perspective consists of the following views: Available Components view, which displays all the available components that you can use to create the design: A list of hardware components: microprocessors, memories, components, and bus interfaces. Bus interfaces can be masters or slaves (see “Specifying the Connections Between Master and Slave Ports” on page 20 for more information on masters and slaves). The component list shown in Figure 10 is the standard list that is given for each new platform. A list of preconfigured systems: demonstrations and pre-verified configurations for a given development board or a configuration that you previously built You can double-click on a component to open a dialog box that enables you to customize the component before it is added to the design. The component is then shown in the Editor view. Editor view, which is a table that displays the components that you have chosen in the Available Components view. It includes the following columns: Name, which displays the names of the chosen components and their ports Connection, which displays the connectivity between master and slave ports Base, which displays the start addresses for components with slave ports. This field is editable. LatticeMico32 Tutorial 13
  20. 20. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform End, which displays the end addresses for components with slave ports. This field is not editable. The value of the end address is equivalent to the value of the base address plus the value of the size. Size, which displays the number of addresses available for component access. This field is editable for the LatticeMico32 on-chip memory (EBR) and the LatticeMico32 asynchronous SRAM controller components only. Lock, which indicates whether addresses are locked from any assignments. If you lock a component, its address will not change if you select Platform Tools > Generate Address. IRQ, which displays the interrupt priorities of all components that have interrupt lines connected to the LatticeMico32 microprocessor. The LatticeMico32 microprocessor can accept up to 32 external interrupt lines. Disable, which indicates whether components are temporarily excluded from the design Component Help view, which displays information about the component that you selected in the Available Components view. It displays the name of the component, for example, “LatticeMico32 Timer” or “LatticeMico32 UART”; a brief description of the function of the component; and a list and explanation of the parameters in the dialog box that appears when you double-click on the component. If you click on the icon next to the component name, you can view a complete description of the component in a PDF file. Console view, which displays informational and error messages output by MSB Component Attributes view, which displays the name, parameters, and values of the component selected in the Available Components view or the Editor view. This view is read-only. Selecting the Microprocessor Core The first step in building the platform is to add the microprocessor core. In this release, only the LatticeMico32 microprocessor is available. You will be using the default cache setting for this task. Refer to the LatticeMico32 System online Help for information on non-cache settings. To add the microprocessor core: 1. Under CPU in the Available Components view, click on LatticeMico32 to view the information available about the LatticeMico32 microprocessor. Information about the LatticeMico32 microprocessor, including the parameters that you can set for it, now appears in the Component Help, or LatticeMico32, view and in the Component Attributes view in the lower third of the screen. If you click on the icon in the Component Help view, you can view a complete description of this component in a PDF file. Similarly, if you click on this icon for a memory or a peripheral component, you can view information about that component. LatticeMico32 Tutorial 14
  21. 21. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform 2. Double-click on LatticeMico32 to add the microprocessor to the design. Alternatively, you can click on LatticeMico32, then click on the Add Component to Platform button ( ) to add the microprocessor. The Add LatticeMico32 dialog box appears, as shown in Figure 11. The parameters in this dialog box correspond to those shown in the table in the Component Help view. The software application developed in this tutorial will be deployed in the parallel flash memory. The goal is to have LatticeMico32 execute the code in the parallel flash memory when configuration of the FPGA is completed. To achieve this goal, the reset address used by LatticeMico32 must point to the flash address. At this point, you have not selected the flash device (and therefore the address), so you will reserve 0x02000000 for the flash. 3. In the Add LatticeMico32 dialog box, do the following: a. To set the LatticeMico32 reset vector to the flash address, type 0x02000000 in the Location of Exception Handlers box. This step sets the reset exception address, which is the address from where the microprocessor will begin fetching instructions at power-up. b. Click OK to accept the default settings for the rest of the options. Figure 11: Add LatticeMico32 Dialog Box Information about the microprocessor now appears in the Name, Connection, Base, End, and Size columns of the table in the Editor view. LatticeMico32 Tutorial 15
  22. 22. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform Adding the Off-Chip Memory Next you will add the LatticeMico32 asynchronous SRAM controller and the parallel flash memory. Adding the Asynchronous SRAM Controller The LatticeMico32 asynchronous SRAM controller is required to download and execute the software application code. The LatticeMico32/DSP development board has two 4-megabit asynchronous SRAM modules organized as 256K x 32, giving a total of 1 megabyte of asynchronous SRAM memory. This SRAM shares the data and address buses with the on-board parallel flash memory chips that are organized as 8M x 32. The wen and oen common control signals are also shared, although each memory type (SRAM, parallel flash memory) has its own chip select. To add the asynchronous SRAM memory to the platform: 1. Under Memory in the Available Components view, double-click on Async SRAM to add the memory. Alternatively, you can click on Async SRAM, then click on to add the memory. The Add Async SRAM dialog box appears, as shown in Figure 12. The SRAM size is 1 megabyte. However, it shares the address bus with the flash device pair. The address bus size will be adjusted to the correct width when the flash memory peripheral is configured later in the tutorial. Figure 12: Add Async SRAM Dialog Box Note You can delete a component from the Editor view by right-clicking on the component in the Editor view and selecting Remove Component from the pop-up menu. If you cannot remove a component, this command will be unavailable on the menu. 2. Accept the default settings in the dialog box, and click OK. LatticeMico32 Tutorial 16
  23. 23. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform Adding the Parallel Flash Memory The LatticeMico32/DSP development board has two 16-bit-wide, 16- megabyte Common Flash Interface (CFI) parallel flash components. These two flash devices together appear as a 8M x 32 flash component. This flash pair will be used for software deployment. To add the parallel flash component to the platform: 1. Under Memory in the Available Components view, double-click on Parallel Flash. Alternatively, you can click on Parallel Flash, then click on to add the component. 2. In the Add Parallel Flash dialog box, shown in Figure 13, do the following: a. In the Base Address box, change the address to 0x02000000 to match the LatticeMico32 microprocessor’s Exception Handler address (shown in Figure 11 on page 15) so that on power-up the microprocessor obtains instructions from this flash component. b. In the Size box, change the size to 33554432, as shown in Figure 13. Figure 13: Add Parallel Flash Dialog Box c. Click OK to accept the default settings for the rest of the options. The flash address bus is shared with the SRAM address bus. The flash is addressed as 8Mx32, but the address width must be wide enough to address 32Mx8, so 25 address bits are required. Make sure the FLASH Address Width option is set to 25 bits wide to ensure that there are enough address bits to access the 1Mx8 SRAM block and the 32Mx8 flash memory block. LatticeMico32 Tutorial 17
  24. 24. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform Adding the Peripheral Components Now you will add the peripheral components to the platform. Adding the GPIO The first component that you will add is the LatticeMico32 GPIO component, which provides a memory-mapped interface between a WISHBONE port and general-purpose I/O ports. The I/O ports connect either to on-chip user logic or to I/O pins that connect to devices external to the FPGA. To add the GPIO to the platform: 1. Under IO in the Available Components view, double-click on GPIO. Alternatively, you can click on GPIO, then click on to add the peripheral. 2. In the Add GPIO dialog box, shown in Figure 14, do the following: a. In the Instance Name box, change the name of the GPIO to LED. For this tutorial, the GPIO block must be named LED. Failure to name the GPIO block LED will cause mismatches in the FPGA I/O pin names. The example C source code uses the instance name to access the GPIO registers. b. Change the setting of the Data Width option to 10. Figure 14: Add GPIO Dialog Box c. Click OK to accept the default settings for the rest of the options. LatticeMico32 Tutorial 18
  25. 25. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform Adding the UART The final component that you will add is a LatticeMico32 universal asynchronous receiver-transmitter (UART), a core that contains a receiver and a transmitter. The receiver performs serial-to-parallel conversion of the aysnchronous data frame received at its serial data input pin. The transmitter performs parallel-to-serial conversion on the 8-bit data received from the CPU. To add the UART to the platform: 1. Under IO in the Available Components view, double-click on UART. Alternatively, you can click on UART, then click on to add the component. 2. In the Add UART dialog box, shown in Figure 15, click OK to accept the default settings. Figure 15: Add UART Dialog Box LatticeMico32 Tutorial 19
  26. 26. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform The MSB perspective now resembles the illustration in Figure 16. Figure 16: MSB Perspective After Addition of All Components Specifying the Connections Between Master and Slave Ports The connections that you will make between the master and slave ports in the Editor view will reflect the access scheme shown in Figure 1 on page 3. The following information applies to master and slave ports in the Editor view: There are two types of ports: master ports and slave ports. A master port can initiate read and write transactions. A slave port cannot initiate transactions but can respond to transactions initiated by a master port if it determines that it is the targeted component for the initiated transaction. A master port can be connected to one or more slave ports. A component can have one or more master ports, one or more slave ports, or both. Horizontal lines with outbound arrows emanating from a component port indicate a master port. LatticeMico32 Tutorial 20
  27. 27. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform Horizontal lines with inbound arrows targeting a component port indicate a slave port. The vertical lines are associated with horizontal lines with outbound arrows (that is, master ports) to facilitate "connectivity" from a master port to a slave port. A circle represents the intersection of the vertical line and a horizontal line associated with a slave port. A filled circle indicates a connection between the master port represented by the vertical line and the slave port represented by the horizontal line associated with the filled circle. A hollow circle indicates an absence of connection between the master port represented by the vertical line and the slave port represented by the horizontal line associated with the hollow circle. The numbers next to the lines representing the master ports are the priorities in which the master ports can access the slave ports. You can change the priority of these connections by following the instructions in the online Help for LatticeMico32 System. To specify the connections between master and slave ports: 1. Connect the instruction and data ports to the LatticeMico32 asynchronous SRAM controller slave port by clicking on both circles in the Connection column in the ASRAM Port row. 2. Connect the data port to the LatticeMico32 GPIO slave port by clicking on the circle in the Connection column in the GP I/O Port row. 3. Connect the instruction and data ports to the LatticeMico32 parallel flash slave port by clicking on both circles in the Connection column in the Data Port row. 4. Connect the data port to the LatticeMico32 UART slave port by clicking on the circle in the Connection column in the UART Port row. Figure 17 shows the resulting connections in the Editor view. The master ports are represented by black lines, and the slave ports are represented by blue lines. Both the instruction and data ports connect to the LatticeMico32 asynchronous SRAM controller and the parallel flash controller, but only the data port connects to the LatticeMico32 GPIO, the LatticeMico32 parallel flash controller, and the LatticeMico32 UART. Figure 17: Connecting the Instruction and Data Ports to the Slave Ports Master ports Slave ports LatticeMico32 Tutorial 21
  28. 28. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform Figure 18 shows the connections generated by MSB. MSB automatically generates the arbiter when it generates the microprocessor platform to allow multiple master ports access to multiple slave ports over a single shared bus. In the diagram, the instruction port accesses the LatticeMico32 Asynchronous SRAM controller and the flash controller. The data port accesses the LatticeMico32 asynchronous SRAM controller, the LatticeMico32 GPIO, the LatticeMico32 parallel flash controller, and the LatticeMico32 UART. Figure 18: Connections Generated by MSB SRAM slave device (memory for code and data) Instruction GPIO slave port device (for Instruction port controlling LEDs) Shared Bus LM32 CPU Arbiter (master ports) Data port Parallel flash Data port memory (for deploying the application code) UART slave device (for host communication) Assigning Component Addresses The next step is for MSB to generate an address for each component with slave ports. Addresses are specified in hexadecimal notation. Components with master ports are not assigned addresses. Note You can only edit the addresses in the Base column. You cannot edit the addresses in the End column. The value of the end address is equivalent to the value of the base address plus the value of the size. In this case, you will not assign individual addresses. You will perform the address generation procedure solely as a prerequisite for generating the microprocessor platform. Since you have explicitly assigned an address to the parallel flash component, you will lock this address so that MSB will not automatically assign it a new address. You do not want the flash address to change, because that is where the final software application code will reside. It is also LatticeMico32 Tutorial 22
  29. 29. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform the address for the microprocessor reset exception (that is, the power-up address) as configured when the microprocessor component is added. To lock the addresses: In the Lock column, select the box for the parallel flash (flash). To automatically assign component addresses: Choose Platform Tools > Generate Address, or click the Generate Base Address button ( ), or right-click in the Editor view and choose Generate Address from the pop-up menu. The addresses now appear in the Base and End columns in the Editor view, in hexadecimal notation. Slave components that are not memories must reside within the 0x80000000-0xFFFFFFFF memory range. The Generate Address command sets A31-A28 of each of these slave components to 0x8. Note Address and size values that appear in italic font in the Editor view cannot be changed. LatticeMico32 Tutorial 23
  30. 30. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform Your MSB perspective should now resemble the example shown in Figure 19. The base addresses that you see in your Editor view may be different from those shown in Figure 19. Figure 19: MSB Perspective After Assignment of Addresses LatticeMico32 Tutorial 24
  31. 31. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform Assigning Interrupt Request Priorities The interrupt request priority is the order in which hardware components request computing time from the CPU. Now you will assign an interrupt request priority (IRQ) to all components that feature a dash in the IRQ column of the Editor view. You cannot assign interrupt priorities to components lacking this dash in the IRQ column, such as memories and CPUs. To assign interrupt priorities for all components other than memories: Choose Platform Tools > Generate IRQ, or click the Generate IRQ button ( ), or right-click in the Editor view and choose Generate IRQ from the pop-up menu. Note To reassign an interrupt priority for a specific component, go to the IRQ column in the row for the component, click on the current interrupt priority number, and choose the new priority number from the drop-down menu. Explicitly assigned interrupt priorities will not be overridden by the generator. Checking the Lock box does not lock the automatically assigned interrupt priority. If you accidentally assign duplicate priorities, MSB will issue an error message in the Console view when you select Platform Tools > Generate IRQ. Performing a Design Rule Check You will want to perform a design rule check to verify the addressing. To perform a design rule check: Choose Platform Tools > Run DRC, or click the Run DRC button ( ), or right-click in the Editor view and choose Run DRC from the pop-up menu. In the Console view, MSB shows that there are no errors in the platform. Generating the Microprocessor Platform You are now ready to generate the microprocessor platform. During the generation process, MSB creates the following files: A platform1.v (Verilog) file, which is the top-level simulation and synthesis RTL file passed to ispLEVER. It includes the .v files for each component in the design. They are used to synthesize and generate a bitstream to be downloaded to the FPGA. The .v files for each component reside under the top-level platform1.v file. A platform1.msb file, which is a configuration file in XML format that contains the configurable parameters and bus interface information for the components. It is passed to C/C++ SPE. In addition, the generation process saves the design and makes these files available to ispLEVER. LatticeMico32 Tutorial 25
  32. 32. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform To generate the microprocessor platform: Click anywhere in the Editor view and choose Platform Tools > Run Generator, or click the Run Generator button ( ), or right-click and choose Run Generator from the pop-up menu. The Console view displays the output as MSB processes the design. MSB now generates the platform1.msb and top-level platform1.v files. You will see Finish Generator in the Console view when the generator is finished. If you edit the .msb file after it has been generated, save it by choosing File > Save As. An asterisk (*) preceding platform1.msb above the Editor view indicates that the platform1.msb file has been edited. The MSB perspective now looks like the illustration in Figure 20. The assigned addresses for the components other than the parallel flash may differ. Figure 20: MSB Perspective After Building the Microprocessor Platform LatticeMico32 Tutorial 26
  33. 33. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform Figure 21 shows the structure of the directory that MSB generates in the background. The contents of this directory are dynamically generated, and any changes to them are overwritten from build to build. Note Only the relevant files are shown in Figure 21, along with a sample of the component directories. LatticeMico32 Tutorial 27
  34. 34. LatticeMico32 Tutorial Task 2: Creating the Microprocessor Platform Figure 21: MSB Directory Structure <install_path> examples Tutorial lm32_tutor platform1 Platform project directory components Components repository asram_top uart_core gpio lm32_top rtl Hardware implementation verilog lm32_top.v and other *.v files drivers Software implementation peripheral.mk file device *.c, *.h files LatticeMico32-specific make files for gnu managed-make software builds Platform definition/implementation soc directory platform1.msb Platform definition (also for software flow) platform1.v Platform implementation (for ispLEVER) platform1_inst.v Platform implementation (for ispLEVER) LatticeMico32 Tutorial 28
  35. 35. LatticeMico32 Tutorial Task 3: Generating the Microprocessor Bitstream As shown in Figure 21, MSB generates a platform1_inst.v file, which contains the Verilog instantiation template to use in a design where the platform is not the top-level module. Figure 22 gives this template for the platform1 platform. Figure 22: Verilog Template platform1 platform1_u ( .clk_i(clk_i), .reset_n(reset_n) , .sramsram_csn(sramsram_csn) // , .sramsram_be(sramsram_be) // [3:0] , .flashsram_csn(flashsram_csn) // , .flashsram_be(flashsram_be) // [3:0] , .flashsram_byten(flashsram_byten) // , .flashsram_wpn(flashsram_wpn) // , .flashsram_rstn(flashsram_rstn) // , .LEDPIO_OUT(LEDPIO_OUT) // [10-1:0] , .uartSIN(uartSIN) // , .uartSOUT(uartSOUT) // , .sramflashOEN(sramflashOEN) , .sramflashWEN(sramflashWEN) , .sramflashADDR(sramflashADDR)// [24:0] , .sramflashDATA(sramflashDATA)// [31:0] ); Task 3: Generating the Microprocessor Bitstream Now you will return to ispLEVER to import the Verilog file generated by MSB and to specify the connections from the microprocessor to the chip pins by importing an .lpf file. You can optionally perform functional simulation and timing simulation. Finally, you will build the database; map, place, and route the design; and generate the bitstream to download to the chip on the board. Importing the Verilog File First, you must import the platform1.v Verilog file output by MSB. To import the Verilog file output by MSB: 1. In the ispLEVER Project Navigator, choose Options > Environment. 2. Click on the General tab. LatticeMico32 Tutorial 29
  36. 36. LatticeMico32 Tutorial Task 3: Generating the Microprocessor Bitstream 3. If the Copy source file to project directory for Source-Import command is selected, turn it off, as shown in Figure 23, and click OK. Figure 23: Environment Options 4. Choose Source > Import. 5. In the Import File dialog box, browse to the following location, select the platform1.v file for the File Name box, and click Open. <ispLEVER_install_path>examplesTutoriallm32_tutorplatform1soc platform1.v 6. In the Import Source Type dialog box, select Verilog Module and click OK. 7. In the Choose Top Module dialog box, select platform1 from the drop- down menu and click OK. Connecting the Microprocessor to the FPGA Pins You have two options for connecting the microprocessor to the FPGA pins: Manually create the pin constraints and import them into ispLEVER. Import a pre-created constraints file that is part of the platform templates into ispLEVER. For brevity, this tutorial allows you to import into ispLEVER the pin constraints specified for the PlatformE template platform, since you will be using PlatformE. MSB copies the .lpf file associated with a platform template, if it exists, into the soc directory. To import the .lpf file: 1. In the Project Navigator, right-click on Build Database and select Properties. LatticeMico32 Tutorial 30
  37. 37. LatticeMico32 Tutorial Task 3: Generating the Microprocessor Bitstream 2. In the Properties dialog box, set Consistent Bus Name Conversion to true. 3. Click Close. 4. In the Project Navigator, choose Source > Import Constraint/ Preference File. 5. In the Import Preference File dialog box, browse to the following directory, select the PlatformE.lpf file for the File Name box, and click Open. <ispLEVER_install_path>micosystemplatformsPlatformE ECPHPE_MINI.lpf 6. In the prompt box that features a line similar to The current constraint file is saved as c:isptoolsexamplestutoriallm32_tutor platform1.lpf.bak, click OK. 7. In the prompt box that says Do you want to reset the project update status?, click Yes. Performing Functional Simulation You can optionally simulate the functionality of the output top-level platform1.v module by using ModelSim in ispLEVER. See the ModelSim Lattice User’s Manual for more information on this procedure. Performing Timing Simulation You can optionally validate the timing of your design by performing timing simulation. Because timing simulation is a complex topic, it is not addressed in this tutorial. For information on timing simulation, see the Achieving Timing Closure in FPGA Designs Tutorial, the “Design Verification” topic in the online flow Help, or the “Strategies for Timing Closure” chapter of the FPGA Design Guide. The timing simulation process automatically builds a database and maps, places, and routes the design. Generating the Bitstream Now you will generate a bitstream to download the microprocessor platform to the FPGA. If you did not perform timing simulation, the bitstream generation process automatically synthesizes, maps, places, and routes the design before it generates the bitstream. To generate a bitstream (.bit) file: 1. In the Sources in Project pane of the Project Navigator, highlight the part name, LFECP33E-4F484C. 2. Double-click Generate Bitstream Data. IspLEVER now generates a bitstream data file, platform1.bit, that is ready to be downloaded into the device. This process takes several minutes. The LatticeMico32 Tutorial 31
  38. 38. LatticeMico32 Tutorial Task 4: Downloading the Hardware Bitstream to the FPGA Project Navigator shows the completion of each process, as shown in Figure 24. Figure 24: Project Navigator After Bitstream Generation Task 4: Downloading the Hardware Bitstream to the FPGA The bitstream file generated in the previous section contains all the information required to program the LatticeECP FPGA. Lattice Semiconductor provides a program, ispVM System, that sends the programming bitstream to the FPGA over a parallel port or USB port communications link. Now you will use ispVM System to download the hardware bitstream that you generated in the previous section to the FPGA on the board. For instructions on connecting the USB cable to the board, refer to the LatticeMico32 Development Kit User’s Guide. To download the bitstream to the FPGA on the board: 1. Remove any Lattice USB ispProgramming cables from your system. 2. Connect a USB cable from your computer to the LatticeMico32/DSP development board. The USB cable must be connected to the USB target LatticeMico32 Tutorial 32
  39. 39. LatticeMico32 Tutorial Task 4: Downloading the Hardware Bitstream to the FPGA connector adjacent to the keypad. Give the computer a few seconds to detect the USB device on the LatticeMico32/DSP development board before moving to step 3. Note A USB cable is included with the board. 3. In the Project Navigator or in the MSB perspective, choose Tools > ispVM System or click on . Alternatively, you can choose Start > Programs > Lattice Semiconductor > Accessories > ispVM System. Note If ispVM is not installed on your system, go to the Lattice Semiconductor Web site to download it. 4. Choose Options > Cable and I/O Port Setup to set up your cable. 5. In the Cable and I/O Port Setup dialog box, shown in Figure 25, do the following: a. In the Cable Type box, select USB. b. In the Port Setting box, choose the only setting available in the drop- down menu, EzUSB-0. c. Click OK. Figure 25: Cable and I/O Port Setup Dialog Box 6. In ispVM, choose ispTools > Scan Chain or click the Scan button. The New Scan Configuration Setup window appears with LFEC/ECP33E in the Device list. 7. Double-click the FileName/IR-Length field next to LFEC/ECP33E. LatticeMico32 Tutorial 33
  40. 40. LatticeMico32 Tutorial Task 4: Downloading the Hardware Bitstream to the FPGA 8. In the Multi Match Device’s ID List, select LFECP33E. The Device Information dialog box now comes up. 9. In the Device Information dialog box, do the following: a. In the Data File box, browse to the platform1.bit file in the following directory, and click Open. <install_path>examplesTutoriallm32_tutorplatform1.bit b. In the Operation box, select Fast Program. c. In the Device Access Options box, select JTAG 1532 Mode from the pull-down menu. The Device Information dialog box should resemble the illustration shown in Figure 26. Figure 26: Device Information Dialog Box d. Click OK. 10. Click the Go button in the ispVM toolbar to initiate the download. A processing status bar shows you the progress of the download. LatticeMico32 Tutorial 34
  41. 41. LatticeMico32 Tutorial Task 5: Creating the Software Application Code 11. Check the New Scan Configuration Setup window to see if the download passed, as shown in Figure 27. Figure 27: New Scan Configuration Setup Window After the Downloading of the Bitstream At the end of this process, the FPGA is loaded with the microprocessor hardware configuration. Note If you want to save this programming configuration for future use, you can save it in an .xcf file. Choose File > Save, and in the Save As .XCF File dialog box, browse to the location where you want to save the .xcf file, type the name of the .xcf file in the File Name box, and click Save. Task 5: Creating the Software Application Code In this task, you create the software application by using C/C++ SPE in LatticeMico32 System. The software application is the code that runs on the LatticeMico32 microprocessor to control the components, the bus, and the memories. The application is written in C/C++. C/C++ SPE is based on the Eclipse environment and provides an integrated development environment for developing, debugging, and deploying C/C++ applications. The C/C++ SPE tool chain uses the GNU C/C++ tool chain (compiler, assembler, linker, debugger, and other necessary utilities) customized for the LatticeMico32 microprocessor. C/C++ SPE uses the same LatticeMico32 System interface as MSB, but it uses a different perspective called the C/C++ perspective. To activate the C/C++ perspective: In the upper left-hand corner of MSB graphical user interface, select C/C++. LatticeMico32 Tutorial 35
  42. 42. LatticeMico32 Tutorial Task 5: Creating the Software Application Code The C/C++ perspective is shown in Figure 28. Figure 28: C/C++ Perspective C/C++ Projects view or Outline Navigator view view Editor view Problems view, Console view, Properties view, Tasks view, or Search view The C/C++ perspective consists of the following views: C/C++ Projects view, which lists C/C++ SPE projects that have been created Navigator view, which shows all of the file system's files under the workspace directory Editor view, which is identical to the Editor view in the MSB perspective Outline view, which displays the structure of the file currently open in the Editor view Problems view, which displays any error, warning, or informational messages output by C/C++ SPE Console view, which displays informational messages output by the C/C++ SPE build process Properties view, which displays the attributes of the item currently selected in the Projects view. This view is read-only. Search view, which displays the results of a search when you choose Search > Search Tasks, which shows the tasks running concurrently in the background Make Targets, which is not used LatticeMico32 Tutorial 36
  43. 43. LatticeMico32 Tutorial Task 5: Creating the Software Application Code Creating a New C/C++ SPE Project You will create a new project in C/C++ SPE, import the platform1.msb file into the project, select the application code template to use so you do not have to write the code yourself, and compile the code. To create a new C/C++ SPE project: 1. In the C/C++ perspective, choose File > New > Mico32 Managed Make C Project. 2. In the New Project dialog box, do the following: a. In the Project Name box, enter LEDTest. b. In the MSB System box, browse to the following location, select the platform1.msb file, and click Open. <ispLEVER_install_path>examplesTutoriallm32_tutorplatform1 socplatform1.msb c. In the Select Project Templates box, select LEDTest as the template for the application code. Note Templates are packaged software application files that are copied to the new project and provide a starting point for building an application. Some templates have specific requirements, as described in the description pane. If these hardware and software requirements are not met, the application built may not function correctly and may require you to debug the application by using the C/ C++ SPE debug interface. C/C++ SPE enables you to create templates in addition to those included with the installation. LatticeMico32 Tutorial 37
  44. 44. LatticeMico32 Tutorial Task 5: Creating the Software Application Code The New Project dialog box should resemble the figure shown in Figure 29. Figure 29: New Project Dialog Box Note The directory shown in the Location box in the Project Contents field is where the software project directory will be created. Your user files will be placed in this directory. d. Click Finish. LatticeMico32 Tutorial 38
  45. 45. LatticeMico32 Tutorial Task 5: Creating the Software Application Code Now you see the source code in the middle pane of the C/C++ perspective, as shown in Figure 30. Figure 30: Source Code in C/C++ Perspective Selecting Linker Memory Settings An application image contains sections called linker sections. Some of these sections, such as the software application code (that is, instructions for the microprocessor) and unmodifiable constants, are not modified by the application. These sections can reside in either a read-only memory region, such as the flash at run time, or a read/write memory region, such as asynchronous memory. Other sections, such as uninitialized variables and the stack required by the application, must reside in read/write memory. C/C++ SPE provides you with an easy-to-use feature for selecting memories for such regions. Your platform contains two memory components: a parallel flash memory and an asynchronous SRAM memory. You will build the LEDTest application to run from the asynchronous SRAM memory; that is, the final executable will store all its linker sections in the SRAM memory region. To select linker sections: 1. Choose Project > Properties. LatticeMico32 Tutorial 39
  46. 46. LatticeMico32 Tutorial Task 5: Creating the Software Application Code The Properties for LEDTest dialog box now appears, as shown in Figure 31. Figure 31: Properties for LEDTest Dialog Box In the left-hand pane, you can open one of the following panes: The Info pane provides basic project location information. The Builders pane provides information on the builder system used for this managed build project. It is preconfigured to use the LatticeMico32 builder system. It should not be modified. C/C++ Build pane enables you to select and manage the compiler, assembler, and linker settings. The Platform pane provides information on the platform used by this project, in addition to other information such as the linker section setting. The Project References pane enables you to manage other projects referenced by the current project. It is not used for the C/C++ SPE LatticeMico32 managed build environment. 2. Select the Platform pane. LatticeMico32 Tutorial 40
  47. 47. LatticeMico32 Tutorial Task 5: Creating the Software Application Code The Properties for LEDTest dialog box now changes to the screen shown in Figure 32. Figure 32: Platform Pane of the Properties for LEDTest Dialog Box The Target Hardware Platform box shows the currently referenced MSB platform. You can change the hardware platform used by the software application, but you must rebuild the software application once you change it. The options in the Linker Script section enable you to select your own linker script. However, for this tutorial you will use the default linker script. For the auto-generated linker script, you can specify the memories that will be used for the linker sections. The C/C++ SPE managed build process inspects the MSB platform specified to determine the available memory regions. As a default, the C/C++ SPE managed build process selects the largest read/write memory available to contain all the sections. For this tutorial, C/C++ SPE will select an SRAM for all the linker sections, because it is the largest read/write memory. 3. Click OK to return to the C/C++ perspective. Compiling the Project The next step is to build the project, in which C/C++ SPE compiles, assembles, and links your application code, as well as the system library code provided by C/C++ SPE. To compile the project: 1. Click on LEDTest to select it in the C/C++ Projects view (left-hand pane). LatticeMico32 Tutorial 41
  48. 48. LatticeMico32 Tutorial Task 5: Creating the Software Application Code 2. Choose Project > Build Project. Do not click on any of the buttons in the Build Project dialog box. This step generates the following files, among others: A C header file, DDStructs.h, that describes the device-driver structures for the applicable devices, in addition to the relevant platform settings, such as the microprocessor clock frequency A C source file, DDStructs.c, that describes the component instance parameters required by the device drivers in appropriate structures A C source file, DDInit.c, that invokes specified device initialization routines for putting the relevant instantiated components in a known state A linker script, linker.ld, that contains the location and size of the memory components and the rules for generating an executable file image, as required by the GNU linker. C/C++ SPE uses this information to ensure that the program code and data are located at the correct addresses. Although this tutorial does not include advanced topics, LatticeMico32 C/C++ SPE enables you to easily specify a custom linker script to be used in lieu of the generated script for the managed build. A LatticeMico32 software executable file with an .elf extension. The .elf file contains the Mico32 instructions, debug information, and information about the pre-initialized data. This tutorial generates a file called platform1.elf. These files are included in the directory that C/C++ SPE generates in the background. The structure of this directory is shown in Figure 33. The contents of this directory are dynamically generated, and any changes to them are overwritten from build to build. LatticeMico32 Tutorial 42
  49. 49. LatticeMico32 Tutorial Task 5: Creating the Software Application Code Note Only the most important files are shown in Figure 33. Figure 33: C/C++ SPE Directory Structure LEDTest Project directory debug Build configuration project output directory *.elf Application executable *.o User-source object files makefile Application makefile Makefile defining peripheral include/ drivers.mk source paths for application debug Output directory for platform sources compiled by application makefile Library source object files compiled by *.o application makefile Platform library file containing platform- libplatform1.a specific drivers platform1 Platform library directory The platform1 library directory shown in Figure 33 contains platform-specific information for the building of an application. Figure 34 shows the automatically generated files in this directory that are required to build an LatticeMico32 Tutorial 43
  50. 50. LatticeMico32 Tutorial Task 5: Creating the Software Application Code application. The contents of this directory are generated dynamically, and any changes to them are not preserved from build to build. Note Only the most important files are shown in Figure 34. Figure 34: Platform Library Directory Structure platform1 Platform library directory Build-configuration platform library output debug directory Makefile that identifies peripheral drivers.mk makefiles for library build Build settings inherited from application inherited_settings. mk build settings linker.ld Default linker script for this platform linker_settings.mk Makefile identifying linker script to use makefile Makefile for building platform library Platform build variables inherited from platform_rules.mk application settings settings.xml Pklatform library build-settings file *.c/*.s Platform-specific driver sources *.h Platform-specific driver header files ddinit.c Driver initialization source file Peripheral instance-specific data ddstructs.c structures ddstructs.h Peripheral-specific data structures LatticeMico32 boot/startup assembly crtoram.s source file system_conf.h System configuration manifest header file LatticeMico32 Tutorial 44

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