LatticeMico32 SPI Flash ROM

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LatticeMico32 SPI Flash ROM

  1. 1. LatticeMico32 SPI Flash ROM The LatticeMico32 serial peripheral interface (SPI) flash ROM controller is a slave device for the WISHBONE architecture. It provides an industry-standard interface between a LatticeMico32 microprocessor and off-chip SPI flash memory device. Version This document describes the 3.1 version (formerly the 7.1 version) of the LatticeMico32 SPI flash ROM controller. Features The LatticeMico32 SPI flash ROM controller includes the following features: WISHBONE B.3 interface Configurable address bus width up to 24 bits Configurable serial clock (SCLK) frequency Configurable fast-read mode Support for SPI flash memory read, write, and sector program operation. The main purpose of this core is the SPI flash memory read. For the random flash write, the whole sector to the internal FIFO must be read first, the full flash sector must be erased, and the whole sector with the particular byte updated must be refreshed. For additional details about the WISHBONE bus, refer to the LatticeMico32 Processor Reference Manual. LatticeMico32 System Components 1
  2. 2. LatticeMico32 SPI Flash ROM Functional Description Functional Description The SPI flash memory controller translates the synchronous WISHBONE bus signals into control strobes used to access an SPI flash memory. The controller decodes the WISHBONE cycle type and generates asynchronous chip selects, byte enables, read enables, and write enables, as required. The controller interacts with the WISHBONE master port, using classic-mode registered-feedback bus cycle control strobes. For further information on the WISHBONE registered feedback bus cycle, refer to the WISHBONE Specifications, Version B3, Chapter 4. The memory controller has a configurable address bus width. The address bus can be up to 24 bits long. You can instantiate multiple SPI flash controllers to permit access to memories of varying address bus sizes. When in operation, the controller monitors the address bus, STB_I, and CYC_I to determine when a memory transaction is in progress. The address, STB_I, and CYC_I control signals are asserted or deasserted at the rising edge of CLK_I. CLK_I may be transitioning at a rate much too high for the SPI flash device to accept, so the memory controller must control and hold off the ACK_O control signal that indicates that the WISHBONE bus transaction is complete. Since SPI flash devices do not have a cycle acknowledge signal, the memory controller provides one. The ACK_O signal is controlled with a fixed read latency value. The read latency depends on the read mode: For normal mode, it takes 64 SCLK cycles to finish the 32-bit read, and for fast-read mode, it takes 72 SCLK cycles. The controller counts CLK_I cycles until the read latency value has been reached. When the latency period expires, ACK_O is asserted, and the WISHBONE cycle is terminated. This SPI flash memory controller is mainly intended to support the SPI flash random-read function. The random-write function is available in the code, but you may need to update the flash data. For most of the SPI flash device, the selected byte must be in the erased state (FFH) when initiating a write, or program, operation, and the SPI flash only supports sector, block, and full- chip erase. If you want to write a single byte, you must first erase the full sector, which contains this byte. To preserve the other data in the sector without corrupting it, you must read it out first to the internal EBR memory, then update the particular byte in the EBR with new data. Finally, you must write or program the full sector back to the SPI flash. Because this process is complex and timing-consuming, it is not recommended that you use the SPI flash memory controller for memory write. In most cases, you will use the SPI flash memory as a ROM. LatticeMico32 System Components 2
  3. 3. LatticeMico32 SPI Flash ROM Functional Description Figure 1 shows how an application uses the SPI flash memory controller. Figure 1: SPI Flash Used by Application CEJ DAT_O SCK SI WISHBONE bus Control signal SPI flash SPI flash memory WPJ memory controller HOLDJ DAT_I SO Figure 2 shows how the SPI flash peripheral behaves when the WISHBONE master requests data from the SPI flash memory controller. Figure 2: States of the SPI Flash Peripheral ST_IDL ST_CMD ST_DAT ST_ADR ST_IDL: The state machine enters the idle state (ST_IDL) after system reset and data transmission. It then enters the command (ST_CMD) state. ST_CMD: The state machine enters the command (ST_CMD) state to read data from the SPI flash. It transmits a read command or a high-speed read command in this state. It enters the address (ST_ADR) state after it transmits the command. ST_ADR: The state machine is in the address (ST_ADR) state as it transmits an address to the SPI flash, then it enters the data (ST_DAT) state. LatticeMico32 System Components 3
  4. 4. LatticeMico32 SPI Flash ROM Configuration ST_DAT: The state machine receives readback data from the SO port and sends S_DAT_O to the WISHBONE master, then enters the idle (ST_IDL) state. Configuration The following sections describe the graphical user interface (UI) parameters, the hardware description language (HDL) parameters, and the I/O ports that you can use to configure and operate the LatticeMico32 SPI flash memory controller. UI Parameters Table 1 shows the UI parameters available for configuring the LatticeMico32 SPI flash ROM through the Mico System Builder (MSB) interface. Table 1: LatticeMico32 SPI Flash ROM UI Parameters Dialog Box Option Description Allowable Values Default Value Instance Name Specifies the name of the SPI flash ROM Alphanumeric and underscores SPIFlash instance. Base Address Specifies the base address for the device. 0X00000000–0XFFFFFFFF 0X00000000 The minimum boundary alignment is 0X4. Size Specifies the size of the SPI flash ROM 16777216 instance, in bytes. SPI Flash Address Specifies the address width, in bits. 1 – 24 24 Width Erase Command Specifies the SPI flash memory controller's Refer to the SPI flash data 216 (0xD8) erase command, in decimal values. sheet. Erase Width Specifies the block size for one bulk erase. Refer to the SPI flash data 16 Sizes are 2Erase_Width, in kilobytes. For sheet. example, if the value is 16, For example, if the value is 16, 216, or 64 kilobytes, will be erased for each erase. LatticeMico32 System Components 4
  5. 5. LatticeMico32 SPI Flash ROM Configuration Table 1: LatticeMico32 SPI Flash ROM UI Parameters (Continued) Dialog Box Option Description Allowable Values Default Value SCLK Rate Specifies the factor for deriving SCLK from 0 – 15 0 the component input clock (processor clock, CLK_I). SCLK is derived from the following equation: CLK_I SCLK = ------------------------------------------------------- - 2 × ( SCLK_Rate + 1 ) For example: For SCLK_Rate = 0: CLK_I SCLK = --------------- - 2 For SCLK_Rate = 1: CLK_I SCLK = --------------- - 4 Note: The SCLK Rate value is used as the CLOCK_SEL parameter in the HDL. Fast Read Determines whether the Fast Read 0|1 (master/slave) 1 (master/ command is enabled. When this option is slave) set to 1, the Fast Read command is enabled. When this option is set to 0, the Fast Read command is disabled. HDL Parameters Table 2 lists the parameters that appear in the HDL. Table 2: LatticeMico32 SPI Flash HDL Parameters Parameter Name Description Allowable Values SPI_ADDR_WIDTH Defines the width of the address 1 – 24 FAST_READ Enable fast read command 0|1 CLOCK_SEL Specifies the factor for deriving SCLK from the component input 0 – 15 clock (processor clock, CLK_I). I/O Ports Table 3 describes the input and output ports of the LatticeMico32 SPI flash. Table 3: LatticeMico32 SPI Flash I/O Port Descriptions I/O Port Active Direction Initial State Description WISHBONE Side Signals CLK_I – I 0 System clock signal LatticeMico32 System Components 5
  6. 6. LatticeMico32 SPI Flash ROM Configuration Table 3: LatticeMico32 SPI Flash I/O Port Descriptions (Continued) I/O Port Active Direction Initial State Description RST_I HIGH I 0 System reset signal CTI_I – I 0 Cycle-type identifier signal. Only “000” is allowed. BTE_I – I 0 Burst-type extension signal, reserved ADR_I [31:0] – I 0 WISHBONE address bus signal DAT_I [31:0] – I 0 WISHBONE data bus input signal SEL_I [3:0] HIGH I 0 Select output array signal, one bit for every byte WE_I HIGH I 0 Write enable signal STB_I HIGH I 0 Strobe signal indicating a valid data transfer CYC_I HIGH I 0 Signal indicating a valid bus cycle in progress ACK_O HIGH O 0 Signal indicating the normal termination DAT_O – O 0 WISHBONE data bus output SPI Interface CEJ XX I X Chip enable (low active) to SPI flash SCK XX I X Serial clock output to SPI flash SI HIGH I X Serial data output to SPI flash SO HIGH I X Serial data input from SPI flash WPJ HIGH I X Write protect (always tie high) HOLDJ HIGH I X Hold (always tie high) LatticeMico32 System Components 6
  7. 7. LatticeMico32 SPI Flash ROM Timing Diagrams Timing Diagrams The timing diagrams featured in Figure 3 and Figure 4 show the timing of the SPI flash memory controller’s WISHBONE and external signals. Figure 3: SPI Flash Read LatticeMico32 System Components 7
  8. 8. LatticeMico32 SPI Flash ROM EBR Resource Utilization SPI Flash Fast Read Logic The SPI flash fast read is similar to the normal flash read, except that the maximum allowable SCLK rate is higher than the normal mode (normal mode is usually 20 MHz, and fast mode can go up to 33 MHz), and there is a dummy byte after the 24-bit address cycle. Figure 4: SPI Flash Fast Read EBR Resource Utilization The SPI flash ROM uses no EBRs. Software Support The LatticeMico32 SPI flash memory controller does not require associated software support. It can access a memory's location by treating it as a general-purpose read/write memory. LatticeMico32 System Components 8

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