Lattice Mico32
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Lattice Mico32

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    Lattice Mico32 Lattice Mico32 Presentation Transcript

    • Technical Seminar Tour 2007 LATTICE‘S PROGRAMMABLE LOWCOST SOLUTIONS LatticeMico32
    • LatticeMico32
      • Agenda
      • Architecture and Peripherals
      • Development tools
      • Software Deployment
      • Tool Flow
      • Demo
    • Introducing the LatticeMico32
      • Flexible, High Performance 32-Bit Microprocessor
      • Optimized For Lattice Leading-Edge Families
        • LatticeEC/P
        • LatticeECP2/M
        • LatticeSC
        • LatticeXP
      • Targeted Towards Wide Variety of Applications
        • Consumer
        • Computation
        • Communications
        • Medical
        • Industrial
        • Automotive
    • Performance Enhanced Feature Set
      • RISC architecture
      • 32-bit data path and 32-bit instructions
      • 32 general purpose register
      • Handles up to 32 external interrupts
      • Optional instruction and data caches
      • Dual Wishbone memory interfaces (Instruction and Data)
    • Architecture
    • Architecture and Pipeline Stages
    • Peripheral Components
      • Enable Design of Complete Embedded Systems
      • Connect via a WISHBONE Bus Interface
        • Royalty-free
        • Public domain specification controlled by OpenCores.org
    • Peripheral Components
      • Broad Selection
        • Coming from Lattice
          • Asynchronous SRAM Controller
          • On-Chip Memory Controller
          • 32-bit Timer
          • DMA Controller
          • GPIO
          • I 2 C Master Controller
          • SPI
          • UART
          • DDR ($)
        • OpenCores.org
          • There is a real documentation coming from Lattice how to create and add wishbone-compatible components to the LatticeMico32 development system!!!!
      Connectivity With a Click Using Design Tools
    • Complete Embedded System Flash/ RAM LatticeMico32 Processor Core On-Chip Memory UART Flash Memory Controller GPIO 32-bit Timer SRAM Controller WISHBONE Interrupt Lines FPGA User Logic Embedded RAM FPGA Config
    • Support Timetable By Device Family
      • Schedule for Family Support:
        • LatticeEC/ECP/ECP2/M Now
        • LatticeSC November 2006
        • LatticeXP January 2007
    • Resource Utilization & Performance
      • Full
      • Multiplier
      • 3 Cycle Shifter
      • 8K I-Cache, 8K D-Cache
      • Standard
      • Multiplier
      • 3 Cycle Shifter
      • 8K I-Cache, No D-Cache
      • BASIC
      • No Multiplier
      • 1 Cycle Shifter
      • No Cache
      Configuration 92 MHz 2230 LatticeEC/ECP 116 MHz 2158 LatticeECP2/M 89 MHz 2040 LatticeEC/ECP 116 MHz 1816 LatticeECP2/M 98 MHz 81 MHz Maximum Clock Frequency 1571 LatticeECP2/M 1830 LUTs LatticeEC/ECP Family
    • Open IP Core Licensing
      • Innovative Open IP Core License
        • Visibility, Reliability, Scalability
      • Free of Charge
      • Generated LatticeMico32 core and Peripherals based on HDL
    • Development Tool
      • LatticeMico32 System
      • to implement HW-IP (uP and Peripherals) and SW
      • Based on Eclipse C/C++ Dev. Tools (CDT)
      • Free of charge, via Internet
      • Combined with ispLEVER
    • Development Tool
      • LatticeMico32 System
      • Mico System Builder (MSB)
        • Generate uP platform and HDL
        • Choose peripherals
        • Specify connectivity between peripherlas
      • C/C++ SW Projekt Environment (SPE) and Debugger
        • Eclipse development environment
        • GNU-based compiler, linker, assembler, debugger
    • RTOS Support
      • Micrium’s uC/OS-II RTOS
      • Included in LatticeMico32 System
      • Open source
      • free of charge for eval and non-commercial use
      • For commercial-use obtain a license directly from Micrium
    • Software Deployment
      • Deploying to
      • External Parallel Flash
      • On-Chip (Embedded Block RAM EBR)
    • Software Deployment: External #1
      • Load app.design to FPGA config flash
      • FPGA configuration via SPI
      ELF FPGA Config Flash LatticeMico32 System FPGA JTAG UART OnChip Mem (EBR) User Logic Parallel Flash SRAM / DDR PC (Debugger, ispVM) BIT BIT SPI
    • Software Deployment: External #2
      • multiple Load app.code to RAM
      • Run app.code from RAM
      • debugging
      ELF FPGA Config Flash LatticeMico32 System FPGA JTAG UART OnChip Mem (EBR) User Logic Parallel Flash SRAM / DDR PC (Debugger, ispVM) BIT BIT SPI ELF
    • Software Deployment: External #3
      • Load FlashProgrammer to RAM
      • Run FlashProgrammer from RAM
      ELF FPGA Config Flash LatticeMico32 System FPGA JTAG UART OnChip Mem (EBR) User Logic Parallel Flash SRAM / DDR PC (Debugger, ispVM) BIT BIT SPI Flash Programmer Flash Programmer
    • Software Deployment: External #4
      • FlashProgrammer copies app.code to ParallelFlash
      ELF FPGA Config Flash LatticeMico32 System FPGA JTAG UART OnChip Mem (EBR) User Logic Parallel Flash SRAM / DDR PC (Debugger, ispVM) BIT BIT SPI ELF Flash Programmer Flash Programmer
    • Software Deployment: External #5
      • Copy app.code to RAM
      • Run app.code from RAM
      FPGA Config Flash Parallel Flash SRAM / DDR SPI LatticeMico32 System FPGA JTAG UART OnChip Mem (EBR) User Logic BIT ELF ELF
    • Software Deployment: OnChip #1
      • Load app.design to FPGA config flash
      • FPGA configuration via SPI
      ELF FPGA Config Flash LatticeMico32 System FPGA JTAG UART OnChip Mem (EBR) User Logic PC (Debugger, ispVM) BIT BIT SPI
    • Software Deployment: OnChip #2
      • multiple Load app.code to EBR
      • Run app.code from EBR
      • debugging
      ELF FPGA Config Flash LatticeMico32 System FPGA JTAG UART OnChip Mem (EBR) User Logic PC (Debugger, ispVM) BIT BIT SPI ELF
    • Software Deployment: OnChip #3
      • Resynthesize FPGA bitstream
      • Load app.design to FPGA config flash
      • FPGA configuration via SPI
      ELF FPGA Config Flash LatticeMico32 System FPGA JTAG UART OnChip Mem (EBR) User Logic PC (Debugger, ispVM) BIT BIT SPI
    • Software Deployment:
      • This are just very simplified descriptions
      • Please have a look to:
      • LatticeMico32 Tutorial (based on the Lattice32 Development Board)
      • SW Developers UserGuide
    • ECP Development
      • Development Board
        • LatticeECP 33 + SPI
        • DDR SODIMM socket
        • 2x128 Mbit Flash + 2x4 Mbit SRAM
        • USB 2.0 Connector for programming
        • Flywire Connector for programming
        • 9-pin RS232 serial port
        • 15-pin VGA connector for 64 colors
        • Ethernet 10/100 M full/half duplex
        • Multiple USB connectors
        • Sigma Delta D/A converter
        • Audio interface (line-in and line-out)
        • LCD connector for character displays
        • 25 MHz oscillator
        • Two-character 7-segment display
      • Power Supply, USB Cable
      • 595 $
    • Software Deployment
      • Deploying to
      • External Parallel Flash Memory
      • Embedded Block RAM (EBR)
      • Alternatives:
      • External Parallel Flash Memory = ConfigFlash (needs a small CPLD)
      • External SPI Flash (coming soon)
    • System Development Flow Mico System Builder (MSB) Platform Development Software Development FPGA Design Implementation Generator Instruction Set Simulator HW Platform Rest of User Design in HDL ELF HDL .h Debug Target Board Debug Program ispVM ™ C/C++ Software Project Environment (SPE) and Debugger
    • System Development Flow
      • Restriction:
      • (not really ;-)
      • MSB delivers Verilog
        • But ispLEVER does not support mixed language designs
        • Do you speak Verilog ??
      • -> use NGO-Flow
      • How?? Ask your AVM-FAE
    • LatticeMico32 Tool Flow
      • Create New project,
        • Verilog HDL,
        • part type ECP33-3F484C if Mico32 dev board is used
    • Tool Flow
      • Invoke Mico32 from IspLever
    • Tool Flow
      • Create a Platform:
        • Platform is processor + peripherals
        • Pre-defined Platforms or create your own
        • Platforms A-E match the LatticeMico32 development board
    • Tool Flow
      • Configure Platform
        • Configurations (e.g. Peripheral name, Wishbone connections, Memory location, size, interrupts, etc) are specified here
    • Tool Flow
      • Configure processor or peripheral:
        • Double click instance name, and configuration options appear
    • Tool Flow
      • Generate Platform
        • Addresses, Irq, DRC, Generate HDL
    • LatticeMico32 Tool Flow
      • Importing an LM32 Project
        • <path>/<project>/soc/<project>.v
    • Tool Flow
      • Importing Development board constraints
        • “ Source” “import constraint/preference file”
        • <isptools6.1>/micosystem/platforms/platformxy
        • Pinouts for SRAM, LED’s, etc.
    • Tool Flow
      • Change Perspective from ‘MSB’ to “C/C++”
    • Tool Flow
      • Using the SPE Environment
        • ‘New “Mico32 New Managed C project”
    • Tool Flow
      • Using the SPE Environment
        • Select a template
    • Tool Flow
      • Using the SPE Environment
        • Compile C Code
        • Make utility will compile source
        • Check for errors
    • Tool Flow
      • Using the SPE Environment
        • Execute C Code
        • Select ‘Run’ ‘debug – mico32 hardware’
        • The demo board can now be executed
    • LatticeMico32 Website http://www.latticesemi.com/products/intellectualproperty/ipcores/latticemico32.cfm
    • Detailed LatticeMico32 Documentation
      • LatticeMico32 Processor Reference Manual
      • LatticeMico32 Software Developer User's Guide
      • LatticeMico32 Development Kit User's Guide
      • LatticeMico32 Tutorial
      • Online Help
        • Workbench
        • MSB
        • C++ Debug
      • Sparkle Sheet
      • LatticeMico32 System Installation Guide
      • Creating Components in the LatticeMico32 System
      • Peripheral Component Data Sheets and Help Panels
        • DMA Controller
        • GPIO
        • I2C Master from OpenCores
        • On-Chip Memory Controller
        • SPI
        • Asynchronous SRAM Controller
        • Parallel Flash Controller
        • 32-bit Timer
        • UART
    • Recommendation: LatticeMico32 Tutorial
      • ~ 3 Hours for completion
      • Based on LatticeMico32 Dev. Board
    • Development Board
      • Development Board
        • LatticeECP 33 + SPI
        • DDR SODIMM socket
        • 2x128 Mbit Flash + 2x4 Mbit SRAM
        • USB 2.0 Connector for programming
        • Flywire Connector for programming
        • 9-pin RS232 serial port
        • 15-pin VGA connector for 64 colors
        • Ethernet 10/100 M full/half duplex
        • Multiple USB connectors
        • Sigma Delta D/A converter
        • Audio interface (line-in and line-out)
        • LCD connector for character displays
        • 25 MHz oscillator
        • Two-character 7-segment display
      • Power Supply
      • USB Cable
      • 595$