K9F8G08UXM

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K9F8G08UXM

  1. 1. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY K9F8G08UXM INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. 1
  2. 2. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY Document Title 1G x 8 Bit/ 2G x 8 Bit NAND Flash Memory Revision History Revision No History Draft Date Remark 0.0 1. Initial issue Sep.26th 2006 Advance 0.1 1. tCSD timing is added (min.10ns) Dec. 8th 2006 Advance 0.2 1. Add random data output after Read for copy Feb. 15nd 2007 Preliminary 2. Add read for copy-back with data output timing guide 3. Modify 2-plane copy-back program operation 4. Modify 2KB program operation timing guide 5. Wafer level capacitance is added. 1.0 1. MONO/DDP LGA package is added. Mar. 31st 2007 Final 2. tCSD is changed.(10ns -> 0ns) The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office. 2
  3. 3. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY 1G x 8 Bit/ 2G x 8 Bit NAND Flash Memory PRODUCT LIST Part Number Vcc Range Organization PKG Type K9F8G08B0M-P 2.5V ~ 2.9V TSOP1 K9F8G08U0M-P x8 K9F8G08U0M-I 2.7V ~ 3.6V 52ULGA K9KAG08U1M-I FEATURES • Fast Write Cycle Time • Voltage Supply - Page Program time : 200µs(Typ.) - 2.7V Device(K9F8G08B0M) : 2.5V ~ 2.9V - Block Erase Time : 1.5ms(Typ.) - 3.3V Device(K9F8G08U0M) : 2.7V ~ 3.6V • Command/Address/Data Multiplexed I/O Port • Organization • Hardware Data Protection - Memory Cell Array : (1G + 32M) x 8bit - Program/Erase Lockout During Power Transitions - Data Register : (4K + 128) x 8bit • Reliable CMOS Floating-Gate Technology • Automatic Program and Erase -Endurance : 100K Program/Erase Cycles(with 1bit/512Byte - Page Program : (4K + 128)Byte ECC) - Block Erase : (256K + 8K)Byte - Data Retention : 10 Years • Page Read Operation • Command Driven Operation - Page Size : (4K + 128)Byte • Intelligent Copy-Back with internal 1bit/528Byte EDC - Random Read : 25µs(Max.) • Unique ID for Copyright Protection - Serial Access : 25ns(Min.) • Package : - K9F8G08B0M-PCB0/PIB0 48 - Pin TSOP1 (12 x 20 / 0.5 mm pitch) - K9F8G08U0M-PCB0/PIB0 48 - Pin TSOP1 (12 x 20 / 0.5 mm pitch) - K9F8G08U0M-ICB0/IIB0 52 - Pin ULGA (12 x 17 / 1.00 mm pitch) - K9KAG08U1M-ICB0/IIB0 52 - Pin ULGA (12 x 17 / 1.00 mm pitch) GENERAL DESCRIPTION Offered in 1Gx8bit, the K9F8G08X0M is a 8G-bit NAND Flash Memory with spare 256M-bit. The device is offered in 2.7V and 3.3V Vcc. Its NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be per- formed in typical 200µs on the (4K+128)Byte page and an erase operation can be performed in typical 1.5ms on a (256K+8K)Byte block. Data in the data register can be read out at 25ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repe- tition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F8G08X0M′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping- out algorithm. The K9F8G08X0M is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. 3
  4. 4. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY PIN CONFIGURATION (TSOP1) K9F8G08X0M-PCB0/PIB0 N.C 1 48 N.C N.C 2 47 N.C N.C 3 46 N.C N.C 4 45 N.C N.C 5 44 I/O7 N.C 6 43 I/O6 R/B 7 42 I/O5 RE 8 41 I/O4 CE 9 40 N.C N.C 10 39 N.C N.C 11 48-pin TSOP1 38 N.C Vcc 12 37 Vcc Vss 13 Standard Type 36 Vss N.C 14 35 N.C N.C 15 12mm x 20mm 34 N.C CLE 16 33 N.C ALE 17 32 I/O3 WE 18 31 I/O2 WP 19 30 I/O1 N.C 20 29 I/O0 N.C 21 28 N.C N.C 22 27 N.C N.C 23 26 N.C N.C 24 25 N.C PACKAGE DIMENSIONS 48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP1 - 1220F Unit :mm/Inch MAX 20.00±0.20 0.004 0.10 0.787±0.008 +0.003 0.008-0.001 #1 +0.07 #48 0.20 -0.03 ( 0.25 ) 0.010 0.488 MAX 12.00 0.472 12.40 0.0197 0.50 #24 #25 1.00±0.05 0.05 0.039±0.002 0.002 MIN 1.20 0.010 TYP 18.40±0.10 0.047MAX +0.075 0.125 0.035 +0.003 0.005-0.001 0.724±0.004 0.25 0~8° 0.45~0.75 0.018~0.030 ( 0.50 ) 0.020 4
  5. 5. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY PIN CONFIGURATION (ULGA) K9F8G08U0M-ICB0/IIB0 A B C D E F G H J K L M N NC NC NC NC NC NC 7 NC /RE NC NC NC NC NC 6 Vcc NC Vss IO7 IO5 Vcc 5 /CE NC R/B NC IO6 IO4 NC 4 3 NC /WE IO0 IO2 Vss NC CLE 2 Vss NC /WP IO1 IO3 Vss 1 NC ALE NC NC NC NC NC NC NC NC NC NC NC PACKAGE DIMENSIONS 52-ULGA (measured in millimeters) Top View Bottom View 12.00±0.10 A 10.00 2.00 1.00 1.00 12.00±0.10 7 6 5 4 3 2 1 B 1.00 1.00 1.30 (Datum A) #A1 A B C D (Datum B) E 1.00 2.50 17.00±0.10 17.00±0.10 F 12.00 G 2.50 H 1.00 1.00 J K 2.00 L 0.50 M N 12-∅1.00±0.05 41-∅0.70±0.05 ∅0.1 M C AB ∅0.1 M C AB Side View 0.65(Max.) 17.00±0.10 0.10 C 5
  6. 6. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY K9KAG08U1M-ICB0/IIB0 A B C D E F G H J K L M N NC NC NC NC NC NC 7 NC /RE1 R/B2 IO7-2 IO6-2 IO5-2 NC 6 Vcc /RE2 Vss IO7-1 IO5-1 Vcc 5 /CE1 /CE2 R/B1 /WP2 IO6-1 IO4-1 IO4-2 4 3 CLE2 /WE1 IO0-1 IO2-1 Vss IO3-2 CLE1 2 Vss ALE2 /WP1 IO1-1 IO3-1 Vss 1 NC ALE1 /WE2 IO0-2 IO1-2 IO2-2 NC NC NC NC NC NC NC PACKAGE DIMENSIONS 52-ULGA (measured in millimeters) Top View Bottom View 12.00±0.10 A 10.00 2.00 1.00 1.00 12.00±0.10 7 6 5 4 3 2 1 B 1.00 1.00 1.30 (Datum A) #A1 A B C D (Datum B) E 1.00 2.50 17.00±0.10 17.00±0.10 F 12.00 G 2.50 H 1.00 1.00 J K 2.00 L 0.50 M N 12-∅1.00±0.05 41-∅0.70±0.05 ∅0.1 M C AB ∅0.1 M C AB Side View 0.65(Max.) 17.00±0.10 0.10 C 6
  7. 7. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY PIN DESCRIPTION Pin Name Pin Function DATA INPUTS/OUTPUTS I/O0 ~ I/O7 The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE CLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. ADDRESS LATCH ENABLE ALE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. CHIP ENABLE CE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation. READ ENABLE RE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WRITE ENABLE WE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. WRITE PROTECT WP The WP pin provides inadvertent program/erase protection during power transitions. The internal high volt- age generator is reset when the WP pin is active low. READY/BUSY OUTPUT The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or R/B random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. POWER Vcc VCC is the power supply for device. Vss GROUND NO CONNECTION N.C Lead is not internally connected. NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected. 7
  8. 8. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY Figure 1. K9F8G08X0M Functional Block Diagram VCC VSS X-Buffers 8,192M + 256M Bit A13 - A30 NAND Flash Latches & Decoders ARRAY Y-Buffers (4,096 + 128)Byte x 262,144 A0 - A12 Latches & Decoders Data Register & S/A Y-Gating Command Command Register I/O Buffers & Latches VCC VSS CE Control Logic RE & High Voltage I/0 0 WE Generator Global Buffers Output Driver I/0 7 CLE ALE WP Figure 2. K9F8G08X0M Array Organization 1 Block = 64 Pages (256K + 8K) Bytes 1 Page = (4K + 128)Bytes 1 Block = (4K + 128)B x 64 Pages 256K Pages = (256K + 8K) Bytes (=4,096 Blocks) 1 Device = (4K + 128)B x 64 Pages x 4,096 Blocks = 8,448 Mbits 8 bit 4K Bytes 128 Bytes I/O 0 ~ I/O 7 Page Register 4K Bytes 128 Bytes I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 Column Address 2nd Cycle A8 A9 A10 A11 A12 *L *L *L Column Address 3rd Cycle A13 A14 A15 A16 A17 A18 A19 A20 Row Address 4th Cycle A21 A22 A23 A24 A25 A26 A27 A28 Row Address 5th Cycle A29 A30 *L *L *L *L *L *L Row Address NOTE : Column Address : Starting Address of the Register. * L must be set to "Low". * The device ignores any additional input of address cycles than required. 8
  9. 9. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY Product Introduction The K9F8G08X0M is a 8,448Mbit(8,858,370,048 bit) memory organized as 262,114 rows(pages) by 4,224x8 columns. Spare 128x8 columns are located from column address of 4,096~4,223. A 4,224-byte data register is connected to memory cell arrays accommo- dating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 2,162,688 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array con- sists of 4,096 separately erasable 256K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F8G08X0M. The K9F8G08X0M has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 1056M byte physical space requires 31 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper- ation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F8G08X0M. In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased. Table 1. Command Sets Function 1st Set 2nd Set Acceptable Command during Busy Read 00h 30h Read for Copy Back 00h 35h Read ID 90h - Reset FFh - O Page Program 80h 10h Copy-Back Program 85h 10h Block Erase 60h D0h Random Data Input (1) 85h - Random Data Output(1) 05h E0h Read Status 70h O Read EDC Status (4) 7Bh O Read Status 2 F1h O Two-Plane Read (3) 60h----60h 30h Two-Plane Read for Copy-Back 60h----60h 35h Two-Plane Random Data Output (1) (3) 00h----05h E0h Two-Plane Page Program(2) 80h----11h 81h----10h Two-Plane Copy-Back Program (2) 85h----11h 81h----10h Two-Plane Block Erase 60h----60h D0h Page Program with 2KB Data (2) 80h----11h 80h----10h Copy-Back Program with 2KB Data (2) 85h----11h 85h----10h NOTE : 1. Random Data Input/Output can be executed in a page. 2. Any command between 11h and 80h/81h/85h is prohibited except 70h/F1h and FFh. 3. Two-Plane Random Data Output must be used after Two-Plane Read operation 4. Read EDC Status is only available on Copy Back operation. Caution : Any undefined command inputs are prohibited except for above command set of Table 1. 9
  10. 10. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY ABSOLUTE MAXIMUM RATINGS Rating Parameter Symbol Unit 2.7V / 3.3V Device VCC -0.6 to + 4.6 Voltage on any pin relative to VSS VIN -0.6 to + 4.6 V VI/O -0.6 to Vcc + 0.3 (< 4.6V) K9XXG08XXM-XCB0 -10 to +125 Temperature Under Bias TBIAS °C K9XXG08XXM-XIB0 -40 to +125 K9XXG08XXM-XCB0 Storage Temperature TSTG -65 to +150 °C K9XXG08XXM-XIB0 Short Circuit Current IOS 5 mA NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND, K9XXG08XXM-XCB0 :TA=0 to 70°C, K9XXG08XXM-XIB0:TA=-40 to 85°C) K9F8G08B0M(2.7V) K9XXG08UXM(3.3V) Parameter Symbol Unit Min Typ. Max Min Typ. Max Supply Voltage VCC 2.5 2.7 2.9 2.7 3.3 3.6 V Supply Voltage VSS 0 0 0 0 0 0 V DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.) K9F8G08X0M Parameter Symbol Test Conditions 2.7V 3.3V Unit Min Typ Max Min Typ Max Page Read with tRC=25ns ICC1 Operating Serial Access CE=VIL, IOUT=0mA - 15 30 - 15 30 Current Program ICC2 - mA Erase ICC3 - Stand-by Current(TTL) ISB1 CE=VIH, WP=0V/VCC - - 1 - - 1 Stand-by Current(CMOS) ISB2 CE=VCC-0.2, WP=0V/VCC - 10 50 - 10 50 Input Leakage Current ILI VIN=0 to Vcc(max) - - ±10 - - ±10 µA Output Leakage Current ILO VOUT=0 to Vcc(max) - - ±10 - - ±10 0.8 Vcc 0.8 Vcc Input High Voltage VIH(1) - - - xVcc +0.3 xVcc +0.3 0.2 0.2 Input Low Voltage, All inputs VIL(1) - -0.3 - -0.3 - xVcc xVcc V K9F8G08B0M :IOH=-100µA VCC Output High Voltage Level VOH - - 2.4 - - K9XXG08UXM :IOH=-400µA -0.4 K9F8G08B0M :IOL=100uA Output Low Voltage Level VOL - - 0.4 - - 0.4 K9XXG08UXM :IOL=2.1mA K9F8G08B0M :VOL=0.1V Output Low Current(R/B) IOL(R/B) 3 4 - 8 10 - mA K9XXG08UXM :VOL=0.4V NOTE : 1. VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less. 2. Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested. 3. The typical value of the K9KAG08U1M’s ISB2 is 20µA and the maximum value is 100µA. 10
  11. 11. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY VALID BLOCK Parameter Symbol Min Typ. Max Unit K9F8G08X0M NVB 4,016 - 4,096 Blocks K9K8G08U1M NVB 8,032* - 8,192* Blocks NOTE : 1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits which cause status fail- ure during program and erase operation. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC. 3. The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane operations. * : Each K9F8G08U0M chip in the K9KAG08U1M has Maximun 80 invalid blocks. AC TEST CONDITION (K9XXG08X0M-XCB0 :TA=0 to 70°C, K9XXG08XXM-XIB0:TA=-40 to 85°C, K9F8G08B0M: Vcc=2.5V ~ 2.9V, K9XXG08UXM: Vcc=2.7V ~ 3.3V,unless otherwise noted) Parameter K9F8G08B0M K9XXG08UXM Input Pulse Levels 0V to Vcc 0V to Vcc Input Rise and Fall Times 5ns 5ns Input and Output Timing Levels Vcc/2 Vcc/2 Output Load 1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF CAPACITANCE(TA=25°C, VCC=2.7V/3.3V, f=1.0MHz) Item Symbol Test Condition Min Max Unit CI/O VIL=0V - 5 pF Input/Output Capacitance CI/O(W)* VIL=0V - 5 pF CIN VIN=0V - 5 pF Input Capacitance CIN(W)* VIN=0V - 5 pF NOTE : 1. Capacitance is periodically sampled and not 100% tested. 2. CI/O(W)* and CIN(W)* are tested at wafer level. MODE SELECTION CLE ALE CE WE RE WP Mode H L L H X Read Command Input Mode L H L H X Address Input(5clock) H L L H H Write Command Input L H L H H Mode Address Input(5clock) L L L H H Data Input L L L H X Data Output X X X X H X During Read(Busy) X X X X X H During Program(Busy) X X X X X H During Erase(Busy) X X(1) X X X L Write Protect X X H X X 0V/V CC(2) Stand-by NOTE : 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby. 11
  12. 12. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY Program / Erase Characteristics Parameter Symbol Min Typ Max Unit Program Time tPROG - 200 700 µs Dummy Busy Time for Two-Plane Page Program tDBSY - 0.5 1 µs Number of Partial Program Cycles Nop - - 4 cycles Block Erase Time tBERS - 1.5 2 ms NOTE : 1. Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested. 2. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25°C temperature. AC Timing Characteristics for Command / Address / Data Input Min Max Parameter Symbol Unit 3.3V(2.7V) 3.3V(2.7V) CLE Setup Time tCLS(1) 12 - ns CLE Hold Time tCLH 5 - ns CE Setup Time t CS(1) 20 - ns CE Hold Time tCH 5 - ns WE Pulse Width tWP 12 - ns ALE Setup Time t ALS(1) 12 - ns ALE Hold Time tALH 5 - ns Data Setup Time t DS(1) 12 - ns Data Hold Time tDH 5 - ns Write Cycle Time tWC 25 - ns WE High Hold Time tWH 10 - ns Address to Data Loading Time t ADL(2) 100 - ns NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low 2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle 12
  13. 13. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY AC Characteristics for Operation Min Max Parameter Symbol Unit 3.3V(2.7V) 3.3V(2.7V) Data Transfer from Cell to Register tR - 25 µs ALE to RE Delay tAR 10 - ns CLE to RE Delay tCLR 10 - ns Ready to RE Low tRR 20 - ns RE Pulse Width tRP 12 - ns WE High to Busy tWB - 100 ns Read Cycle Time tRC 25 - ns RE Access Time tREA - 20 ns CE Access Time tCEA - 25 ns RE High to Output Hi-Z tRHZ - 100 ns CE High to Output Hi-Z tCHZ - 30 ns CE High to ALE or CLE Don’t Care tCSD 0 - ns RE High to Output Hold tRHOH 15 - ns RE Low to Output Hold tRLOH 5 - ns CE High to Output Hold tCOH 15 - ns RE High Hold Time tREH 10 - ns Output Hi-Z to RE Low tIR 0 - ns RE High to WE Low tRHW 100 - ns WE High to RE Low tWHR 60 - ns Device Resetting Time(Read/Program/Erase) tRST - 5/10/500 (1) µs WP High to WE Low tWW 100 - ns NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5µs. 13
  14. 14. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select tran- sistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC. Identifying Initial Invalid Block(s) All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The ini- tial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 4,096. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited. Start Set Block Address = 0 Increment Block Address Check "FFh" at the column address 4,096 * of the 1st and 2nd page in the block Create (or update) No Check "FFh" Initial Invalid Block(s) Table Yes No Last Block ? Yes End Figure 3. Flow chart to create initial invalid block table 14
  15. 15. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks. Failure Mode Detection and Countermeasure sequence Erase Failure Status Read after Erase --> Block Replacement Write Program Failure Status Read after Program --> Block Replacement Read Single Bit Failure Verify ECC -> ECC Correction ECC : Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection Program Flow Chart Start Write 80h Write Address Write Data Write 10h Read Status Register I/O 6 = 1 ? No or R/B = 1 ? Yes * No Program Error I/O 0 = 0 ? Yes Program Completed * : If program operation results in an error, map out the block including the page in error and copy the target data to another block. 15
  16. 16. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY NAND Flash Technical Notes (Continued) Erase Flow Chart Read Flow Chart Start Start Write 60h Write 00h Write Block Address Write Address Write D0h Write 30h Read Status Register Read Data ECC Generation I/O 6 = 1 ? No or R/B = 1 ? No Yes Reclaim the Error Verify ECC * No Erase Error I/O 0 = 0 ? Yes Page Read Completed Yes Erase Completed * : If erase operation results in an error, map out the failing block and replace it with another block. Block Replacement Block A 1st { ∼ (n-1)th 1 nth an error occurs. (page) Buffer memory of the controller. Block B 1st { 2 ∼ (n-1)th nth (page) * Step1 When an error happens in the nth page of the Block ’A’ during erase or program operation. * Step2 Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’) * Step3 Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’. * Step4 Do not erase or program Block ’A’ by creating an ’invalid block’ table or other appropriate scheme. 16
  17. 17. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY NAND Flash Technical Notes (Continued) Copy-Back Operation with EDC & Sector Definition for EDC Generally, copy-back program is very powerful to move data stored in a page without utilizing any external memory. But, if the source page has one bit error due to charge loss or charge gain, then without EDC, the copy-back program operation could also accumulate bit errors. K9F8G08X0M supports copy-back with EDC to prevent cumulative bit errors. To make EDC valid, the page program operation should be performed on either whole page(4224byte) or sector(528byte). Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial modification smaller than a sector corrupts the on-chip EDC codes. A 4,224-byte page is composed of 8 sectors of 528-byte and each 528-byte sector is composed of 512-byte main area and 16-byte spare area. Main Field (4,096 Byte) Spare Field (128 Byte) "A" area "B" area "C" area "D" area "E" area "F" area "G" area "H" area "I" "J" "K" "L" "M" "N" "O" "P" (1’st sector) (2’nd sector)(3’rd sector) (4’th sector)(5’th sector) (6’th sector) (7’th sector) (8’th sector) (1’st ) (2’nd ) (3’rd ) (4’th ) (5’th ) (6’tht ) (7’th ) (8’th ) 16 16 16 16 16 16 16 16 512 Byte 512 Byte 512 Byte 512 Byte 512 Byte 512 Byte 512 Byte 512 Byte Byte Byte Byte Byte Byte Byte Byte Byte Table 2. Definition of the 528-Byte Sector Main Field (Column 0~4,095) Spare Field (Column 4,096~4,223) Sector Area Name Column Address Area Name Column Address 1’st 528-Byte Sector "A" 0 ~ 511 "I" 4,096 ~ 4,111 2’nd 528-Byte Sector "B" 512 ~ 1,023 "J" 4,112 ~ 4,127 3’rd 528-Byte Sector "C" 1,024 ~ 1,535 "K" 4,128 ~ 4,143 4’th 528-Byte Sector "D" 1,536 ~ 2,047 "L" 4,114 ~ 4,159 5’th 528-Byte Sector "E" 2,048 ~ 2,559 "M" 4,160 ~ 4,175 6’th 528-Byte Sector "F" 2,560 ~ 3,071 "N" 4,176 ~ 4,191 7’th 528-Byte Sector "G" 3,072 ~ 3,583 "O" 4,192 ~ 4,207 8’th 528-Byte Sector "H" 3,584 ~ 4,095 "P" 4,208 ~ 4,223 17
  18. 18. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig- nificant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB doesn’t need to be page 0. Page 63 (64) Page 63 (64) : : Page 31 (32) Page 31 (1) : : Page 2 (3) Page 2 (3) Page 1 (2) Page 1 (32) Page 0 (1) Page 0 (2) Data register Data register From the LSB page to MSB page Ex.) Random page program (Prohibition) DATA IN: Data (1) Data (64) DATA IN: Data (1) Data (64) 18
  19. 19. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 4,224byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of µ-seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption. Figure 4. Program Operation with CE don’t-care. CLE ≈ ≈ ≈ CE don’t-care CE ≈ ≈ ≈ ≈ ≈ WE ≈≈ ALE ≈ ≈ I/Ox 80h Address(5Cycles) Data Input Data Input 10h tCS tCH tCEA CE CE tREA tWP RE WE I/O0~7 out Figure 5. Read Operation with CE don’t-care. CLE ≈ ≈ CE don’t-care CE ≈ ≈ ≈ ≈ ≈ RE ALE ≈≈ ≈ R/B tR ≈ WE ≈ I/Ox 00h Address(5Cycle) 30h Data Output(serial access) 19
  20. 20. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY NOTE I/O DATA ADDRESS Device I/Ox Data In/Out Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 K9F8G08X0M I/O 0 ~ I/O 7 4,114byte A0~A7 A8~A12 A13~A20 A21~A28 A29~A30 Command Latch Cycle CLE tCLS tCLH tCS tCH CE tWP WE tALS tALH ALE tDS tDH I/Ox Command Address Latch Cycle tCLS CLE tCS tWC tWC tWC tWC CE tWP tWP tWP tWP WE tWH tWH tWH tWH tALH tALS tALH tALS tALH tALS tALH tALS tALH tALS ALE tDH tDH tDH tDH tDH tDS tDS tDS tDS tDS I/Ox Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 20
  21. 21. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY Input Data Latch Cycle tCLH CLE ≈ tCH CE ≈ tWC ALE ≈ tALS tWP tWP tWP ≈ WE tWH tDH tDH tDH tDS tDS tDS ≈ I/Ox DIN 0 DIN 1 DIN final ≈ * Serial Access Cycle after Read(CLE=L, WE=H, ALE=L) CE tRC ≈ tCHZ tREH tREA tREA tREA tCOH ≈ RE tRHZ tRHZ tRHOH I/Ox Dout Dout Dout ≈ tRR ≈ R/B NOTES : 1.Transition is measured at ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 2. tRLOH is valid when frequency is higher than 33MHz. tRHOH starts to be valid when frequency is lower than 33MHz. 21
  22. 22. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L) CE ≈ tRC tCHZ tRP tREH tCOH ≈ RE tRHZ tREA tREA tRLOH tRHOH tCEA ≈ I/Ox Dout Dout ≈ tRR ≈ R/B NOTES : 1. Transition is measured at ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 2. tRLOH is valid when frequency is higher than 33MHz. tRHOH starts to be valid when frequency is lower than 33MHz. Status Read Cycle & EDC Status Read Cycle tCLR CLE tCLS tCLH tCS CE tCH tWP WE tCEA tCHZ tWHR tCOH RE tDH tREA tRHZ tDS tIR tRHOH I/Ox 70h/7Bh Status Output 22
  23. 23. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY Read Operation tCLR CLE CE tWC WE tCSD tWB tAR ALE tRHZ tR tRC RE ≈ tRR ≈ ≈ I/Ox 00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 30h Dout N Dout N+1 Dout M Column Address Row Address R/B Busy Read Operation(Intercepted by CE) tCLR CLE CE tCSD WE tCHZ tWB tAR tCOH ALE tR tRC RE tRR I/Ox 00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 30h Dout N Dout N+1 Dout N+2 Column Address Row Address R/B Busy 23
  24. 24. Random Data Output In a Page K9KAG08U1M CLE tCLR K9F8G08U0M K9F8G08B0M CE WE tWB tRHW tWHR tAR 24 ALE tR tRC tREA RE tRR I/Ox 00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 30h/35h Dout N Dout N+1 05h Col Add1 Col Add2 E0h Dout M Dout M+1 Column Address Row Address Column Address R/B Busy FLASH MEMORY
  25. 25. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY Page Program Operation CLE CE tWC tWC tWC ≈ WE tADL tWB tPROG tWHR ALE RE ≈ ≈ Din Din I/Ox 80h Co.l Add1 Col. Add2 Row Add1 Row Add2 Row Add3 N M 10h 70h I/O0 SerialData 1 up to m Byte Program Read Status Column Address Row Address Input Command Serial Input Command Command R/B ≈ I/O0=0 Successful Program I/O0=1 Error in Program NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 25
  26. 26. Page Program Operation with Random Data Input K9KAG08U1M CLE CE tWC tWC tWC ≈ WE ≈ K9F8G08U0M K9F8G08B0M tADL tADL tWB tPROG tWHR ALE RE 26 Din Din Din Din 80h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 85h Col. Add1 Col. Add2 10h 70h I/O0 I/Ox N M J K ≈ ≈ ≈ ≈ Serial Data Program Read Status Column Address Row Address Serial Input Random Data Column Address Serial Input Input Command Input Command Command Command R/B I/O0=0 Successful Program ≈ I/O0=1 Error in Program NOTES : 1. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 2. For EDC operation, only one time random data input is possible at the same address. FLASH MEMORY
  27. 27. Copy-Back Program Operation With Random Data Input K9KAG08U1M CLE CE tWC WE K9F8G08U0M K9F8G08B0M tWB tPROG tWB tWHR ALE tR RE tADL 27 I/Ox 00h Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 35h 85h Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 Data 1 Data N 10h 70h/7Bh I/Ox ≈ ≈ Column Address Row Address Column Address Row Address Read EDC Status or Read Status Command R/B ≈ ≈ Busy Busy I/O0=0 Successful Program Copy-Back Data I/O0=1 Error in Program Input Command I/O1 ~ I/O2 : EDC Status (7Bh only) NOTES : 1. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 2. For EDC operation, only one time random data input is possible at the same address. FLASH MEMORY
  28. 28. K9KAG08U1M K9F8G08U0M K9F8G08B0M FLASH MEMORY Block Erase Operation CLE CE tWC WE tWB tBERS tWHR ALE RE I/Ox 60h Row Add1 Row Add2 Row Add3 D0h 70h I/O 0 Row Address R/B Busy ≈ Auto Block Erase Erase Command I/O0=0 Successful Erase Setup Command Read Status I/O0=1 Error in Erase Command 28

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