Introduction to the


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Introduction to the

  1. 1. Introduction to the Atmel Atmega32 Assembler CS-280 Dr. Mark L. Hornick
  2. 2. Inside an IC package CS-280 Dr. Mark L. Hornick
  3. 3. Inside an IC package CS-280 Dr. Mark L. Hornick
  4. 4. CS-280 Dr. Mark L. Hornick Atmel Atmega32 <ul><li>Central Processing Unit </li></ul><ul><ul><li>Arithmetic Logic Unit (ALU) performs the actual arithmetic, logical, and bit-functions </li></ul></ul><ul><li>Memory – SRAM, EEPROM, Flash </li></ul><ul><li>Clock circuit – internal/external </li></ul><ul><li>I/O – Input/Output; video, serial, parallel, USB, SCSI, etc. </li></ul>
  5. 5. CS-280 Dr. Mark L. Hornick Programs are stored here Temporary data is stored here Permanent data is stored here
  6. 6. 3 Separate on-chip memories <ul><li>2KB SRAM </li></ul><ul><ul><li>For temporary data storage </li></ul></ul><ul><ul><li>Memory is lost when power is shut off (volatile) </li></ul></ul><ul><ul><li>Fast read and write </li></ul></ul><ul><li>1KB EEPROM </li></ul><ul><ul><li>For persistent data storage </li></ul></ul><ul><ul><li>Memory contents are retained when power is off (non-volatile) </li></ul></ul><ul><ul><li>Fast read; slow write </li></ul></ul><ul><ul><li>Can write individual bytes </li></ul></ul><ul><li>32KB Flash Program Memory </li></ul><ul><ul><li>Used to store program code </li></ul></ul><ul><ul><li>Memory contents retained when power is off (non-volatile) </li></ul></ul><ul><ul><li>Fast to read; slow to write </li></ul></ul><ul><ul><li>Can only write entire “blocks” of memory at a time </li></ul></ul><ul><ul><li>organized in 16-bit words (16KWords) </li></ul></ul>CS-280 Dr. Mark L. Hornick
  7. 7. Flash Program Memory layout CS-280 Dr. Mark L. Hornick <ul><li>There are 32KB of program memory (Flash memory) </li></ul><ul><ul><li>Organized as 16K 2-byte words </li></ul></ul><ul><ul><li>Because program instructions are either 2 or 4 bytes long </li></ul></ul><ul><li>Each word (not byte) in memory has a unique address </li></ul><ul><ul><li>Beginning address $0000 </li></ul></ul><ul><ul><li>Ending address $3FFF </li></ul></ul><ul><li>Some memory is reserved or protected </li></ul><ul><ul><li>First 42 words (reserved) </li></ul></ul><ul><ul><li>Last 1024 words (protected) </li></ul></ul>$3C00 1024 words (2048 bytes) Reset and interrupt vector section 42 words (84 bytes) $002A
  8. 8. Registers are special-purpose memory <ul><li>There are relatively few registers </li></ul><ul><li>Directly accessed by the CPU/ALU (very fast R/W) </li></ul><ul><li>Registers are used to contain: </li></ul><ul><ul><li>address of the next instruction to fetch from program memory </li></ul></ul><ul><ul><li>machine instruction to be executed </li></ul></ul><ul><ul><li>“ input” data to be operated upon by the ALU </li></ul></ul><ul><ul><li>“ output” data resulting from an ALU operation </li></ul></ul>CS-280 Dr. Mark L. Hornick
  9. 9. General Purpose Registers <ul><li>There are 32 8-bit GP registers R0-R31 </li></ul><ul><ul><li>Used as accumulators – for most math and logic </li></ul></ul><ul><li>X, Y, Z are 16-bit registers that overlap R26-R31 </li></ul><ul><ul><li>Used as address pointers </li></ul></ul><ul><ul><li>Or to contain larger values (>255) </li></ul></ul>CS-280 Dr. Mark L. Hornick
  10. 10. Special-purpose Registers <ul><li>Stack pointer (SP, 16-bit) </li></ul><ul><ul><li>Stores return address of subroutine/interrupt calls </li></ul></ul><ul><ul><li>Storing temporary data and local variables </li></ul></ul><ul><li>Program counter (PC, 16-bit) </li></ul><ul><ul><li>Holds address of next program instruction to be executed </li></ul></ul><ul><ul><li>Automatically incremented when the ALU executes an instruction </li></ul></ul><ul><li>Status Register (SREG, 8-bit) </li></ul><ul><ul><li>Contains information of result of most recent ALU operation </li></ul></ul><ul><li>… and many more </li></ul>CS-280 Dr. Mark L. Hornick
  11. 11. An Assembler converts human-readable instructions into machine-executable opcodes that are stored in Program Memory <ul><li>Consider the assembly language instruction add rD, rS </li></ul><ul><ul><li>add is a reserved assembly language instruction mnemonic </li></ul></ul><ul><ul><li>rS and rD are operands that refer to source and destination registers </li></ul></ul><ul><ul><li>This instruction adds the contents of register rS to register rD </li></ul></ul><ul><ul><ul><li>Example: Substitute any actual register (R0-R31) for rS and rD : add r20, r5 </li></ul></ul></ul><ul><ul><ul><li>case is not important; the instruction can also be written as ADD R20, R5 </li></ul></ul></ul>CS-280 Dr. Mark L. Hornick
  12. 12. Let’s consider the case of how one particular instruction is represented as a machine-executable instruction <ul><li>Example: ADD R20, R5 </li></ul><ul><li>A 16-bit machine instruction is generated for this particular case </li></ul><ul><ul><li>Machine instructions consist of an numeric opcode and operands </li></ul></ul><ul><ul><li>The opcode in this case is 000011 (3) </li></ul></ul><ul><ul><li>Each register operand is represented by 5 bits </li></ul></ul><ul><ul><ul><li>5 bits are required to represent all possible register values from 0-31 </li></ul></ul></ul><ul><ul><ul><li>ddddd represent the 5 bits that represent the destination register value (20) </li></ul></ul></ul><ul><ul><ul><li>rrrrr represent the 5 bits that represent the source register value (5) </li></ul></ul></ul>CS-280 Dr. Mark L. Hornick 0000 11 r d dddd rrrr 0000 11 0 1 0100 0101 add r20, r5 is assembled to: Note: The bits ddddd and rrrrr are “split” in this instruction This 16-bit binary word is expressed in hexadecimal as 0x0d45
  13. 13. The machine-instruction is executed by the central processing unit <ul><li>The instruction indicated by the Program Counter is fetched from program memory and placed in the Instruction Register </li></ul><ul><li>The opcode and operands within the instruction are extracted by the Instruction Decoder </li></ul><ul><li>The control lines from the I.D. activate the particular circuitry within the ALU that is capable of processing that particular opcode </li></ul>CS-280 Dr. Mark L. Hornick
  14. 14. Instruction execution sequence CS-280 Dr. Mark L. Hornick