Implementation and Challenging
     Issues of Flash-Memory Storage
                  Systems

                      Tei-We...
Introduction – Why Flash Memory
   Diversified Application Domains
         Portable Storage Devices
         Consumer Ele...
Introduction – Trends in Storage Technology
                                                                              ...
The Ultimate Limit on Mechanical Devices

uA Microdrive Example


    Fly          2,000,000 Miles Per Hour
     By
    Ni...
Introduction – Single-Level Cell
(SLC)
Each Word Line is connected to
control gates.
Each Bit Line is connected to the
dra...
Comparison of SLC and MLC
      1-bit/Cell SLC NAND Flash
             100,000 Program/Erase cycles (with ECC)[1]
        ...
Bandwidth Requirements – Video




       ˇ

       ˇ



                Electronic Engineering Times, July 2005
3/29/2007...
Introduction – Challenges in Flash-
Memory Storage Designs
    Requirements in Good Performance
    Limited Cost per Unit
...
Management Issues – System
Architectures
               AP            AP                 AP                     AP


     ...
Management Issues – Flash-Memory
Characteristics
         Write-Once
             No writing on the same page unless its r...
Management Issues – Flash-Memory
Characteristics
  Example 1: Out-place Update


            A   B   C    D            A  ...
Management Issues – Flash-Memory
Characteristics
  Example 2: Garbage Collection


   D D D D D D D D                     ...
Management Issues – Flash-Memory
 Characteristics
        Example 3: Wear-Leveling

                                      ...
Agenda
     Introduction
     Management Issues
     Performance vs Overheads – FTL vs
     NFTL
     Other Challenging Is...
Management Issues – Flash-
Memory Characteristics




       *FTL: Flash Translation Layer, MTD: Memory Technology Device
...
Policies – NFTL (Type 1)
   A logical address under NFTL is divided into a virtual
   block address and a block offset.
  ...
Policies – NFTL
        NFTL is proposed for the large-scale NAND
        flash storage systems because NFTL adopts
      ...
Address Translation Time - NFTL
 The address translation performance of read
 and write requests can be deteriorated, due ...
Space Utilization - NFTL




            3 free pages are wasted.

3/29/2007    Embedded Systems and Wireless Networking L...
Motivation
   An adaptive two-level management design of a
   flash translation layer, called AFTL.
        Exploit the ad...
AFTL – Fine-to-Coarse Switching
   The number of the fine-grained slots is limited.
            Some least recently used m...
The Advantages of AFTL
Improve the address translation
performance.
   It is because the moving of their mapping
   inform...
Performance Evaluation
Performance Setup
      The characteristics of the experiment trace was over a 20GB
      disk.
CPU...
Memory Space Requirements
                                             1200                                  AFTL         ...
Garbage Collection Overhead
                                         550000           ST=64                               ...
Summary
                                                                                                                  ...
Challenging Issues – Reliability
Each Word Line is connected to
control gates.
Each Bit Line is connected to the
drain.   ...
Challenging Issues – Reliability
  Over-Erasing Problems
        Fast Erasing Bits à All of the cells connected to the sam...
Wear Leveling versus Product Lifetime
Settings
     File system: FAT16 file system with 8KB cluster size
     Flash memory...
Wear Leveling versus Product Lifetime
Static Wear Leveling – Block-Level Mapping
 Use a counter for each block
 The garbag...
Conclusion
     What Is Happening?
           Solid-State Storage Devices
           New Designs in the Memory Hierarchy
 ...
Q&A




      32
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Implementation and Challenging Issues of Flash-Memory Storage ...

  1. 1. Implementation and Challenging Issues of Flash-Memory Storage Systems Tei-Wei Kuo Department of Computer Science & Information Engineering National Taiwan University Agenda Introduction Management Issues Performance vs Overheads Other Challenging Issues Conclusion 3/29/2007 Embedded Systems and Wireless Networking Lab. 2 1
  2. 2. Introduction – Why Flash Memory Diversified Application Domains Portable Storage Devices Consumer Electronics Industrial Applications SoC and Hybrid Devices Critical System Components 3/29/2007 Embedded Systems and Wireless Networking Lab. 3 Trends in VLSI Technology Source: www.icknowledge.com 3/29/2007 Embedded Systems and Wireless Networking Lab. 4 * This slide was from the ASP-DAC’06 talk delivered by Prof. Sang L. Min from the Seoul National University. 2
  3. 3. Introduction – Trends in Storage Technology September 2006 Samsung 2GB USB 2.0 Flash Drive Price: $49.99 Less Rebate: - $25.00 Final Price: $24.99* T-One 2GB Microdrive/3600RPM $144.99 Source: Using multilevel cell NAND flash technology in consumer applications, Electronic Engineering Times, July ,2005 3/29/2007 Embedded Systems and Wireless Networking Lab. 5 Introduction – Trends in Storage Technology March 2007 Transcend 8GB CompactFlash Card Price: $84.85 ScanDisk 4GB CompactFlash Card Price: $55.99 Microdrive 4GB Compact Flash Type II Source: Using multilevel cell NAND flash technology in consumer applications, Price: $116 Electronic Engineering Times, July ,2005. Amazon.com 3/29/2007 Embedded Systems and Wireless Networking Lab. 6 3
  4. 4. The Ultimate Limit on Mechanical Devices uA Microdrive Example Fly 2,000,000 Miles Per Hour By Night Boeing 747 1/100” Flying Height Source: Richard Lary, The New Storage Landscape: Forces Source: shaping the storage economy, 2003. http://www.hitachigst.com/ 3/29/2007 Embedded Systems and Wireless Networking Lab. 7 * This slide was from the ASP-DAC’06 talk delivered by Prof. Sang L. Min from the Seoul National University. Introduction – The Characteristics of Storage Media Access time Media Read Write Erase DRAM 60ns (2B) 60ns (2B) - 2.56us (512B) 2.56us (512B) NOR FLASH 150ns (1B) 211us (1B) 1.2s (16KB) 15X 14.4us (512B) 3.52ms (512B) 100X NAND 10.2us (1B) 201us (1B) 2ms (16KB) FLASH 35.9us (512B) 226us (512B) 50X DISK 400X 12.4ms (512B) 12.4 ms(512B) - (average) (average) [Reference] DRAM:2-2-2 PC100 SDRAM. NOR FLASH: Intel 28F128J3A-150. NAND FLASH: Samsung K9F5608U0M. Disk: Segate Barracuda ATA II.1 1. J. Kim, J. M. Kim, S. H. Noh, S. L. Min, and Y. Cho. A space-efficient flash translation layer for compact-flash systems. IEEE Transactions on Consumer Electronics, 48(2):366–375, May 2002. 3/29/2007 Embedded Systems and Wireless Networking Lab. 8 4
  5. 5. Introduction – Single-Level Cell (SLC) Each Word Line is connected to control gates. Each Bit Line is connected to the drain. Control Gate Drain Source Cell IDS Selected cell 3/29/2007 Embedded Systems and Wireless Networking Lab. 9 Introduction – Multi-Level Cell (MLC) vs SLC 3/29/2007 Embedded Systems and Wireless Networking Lab. 10 5
  6. 6. Comparison of SLC and MLC 1-bit/Cell SLC NAND Flash 100,000 Program/Erase cycles (with ECC)[1] 10 years Data Retention[1] 2-bits/Cell MLC NAND Flash 10,000 Program/Erase cycles (with ECC) [2] 10 years Data Retention[2] 4-bits/Cell MLC NAND FLASH Developers (2006) M-systems, Intel, Samsung, and Toshiba [1] ST Micro-electronics NAND SLC large page datasheet (NAND08GW3B2A) [2] ST Micro-electronics NAND MLC large page datasheet (NAND04GW3C2A) * USD34.65 per GB for NOR, USD6.79 per GB for NAND 3/29/2007 Embedded Systems and Wireless Networking Lab. 11 Introduction – Consumer Applications 3/29/2007 Electronic Engineering Wireless Networking Lab. Embedded Systems and Times, July 2005 12 6
  7. 7. Bandwidth Requirements – Video ˇ ˇ Electronic Engineering Times, July 2005 3/29/2007 Embedded Systems and Wireless Networking Lab. 13 Bandwidth Requirements – Audio ˇ ˇ Electronic Engineering Times, July 2005 3/29/2007 Embedded Systems and Wireless Networking Lab. 14 7
  8. 8. Introduction – Challenges in Flash- Memory Storage Designs Requirements in Good Performance Limited Cost per Unit Strong Demands in Reliability Increasing in Access Frequencies Tight Coupling with Other Components Low Compatibility among Vendors 3/29/2007 Embedded Systems and Wireless Networking Lab. 15 Agenda Introduction Management Issues Performance vs Overheads Other Challenging Issues Conclusion 3/29/2007 Embedded Systems and Wireless Networking Lab. 16 8
  9. 9. Management Issues – System Architectures AP AP AP AP File-System Layer Block Device Layer (FTL emulation) MTD drivers Flash Memory 3/29/2007 Embedded Systems and Wireless Networking Lab. 17 Management Issues – Flash-Memory Characteristics Write one 1 Page = 512B page 1 Block = 32 pages(16KB) Block 0 Block 1 Block 2 Block 3 Erase …… …… one block 3/29/2007 Embedded Systems and Wireless Networking Lab. 18 9
  10. 10. Management Issues – Flash-Memory Characteristics Write-Once No writing on the same page unless its residing block is erased! Pages are classified into valid, invalid, and free pages. Bulk-Erasing Pages are erased in a block unit to recycle used but invalid pages. Wear-Leveling Each block has a limited lifetime in erasing counts. 3/29/2007 Embedded Systems and Wireless Networking Lab. 19 Management Issues – Flash-Memory Characteristics Example 1: Out-place Update A B C D Live pages Free pages Suppose that we want to update data A and B… 3/29/2007 Embedded Systems and Wireless Networking Lab. 20 10
  11. 11. Management Issues – Flash-Memory Characteristics Example 1: Out-place Update A B C D A B Dead pages 3/29/2007 Embedded Systems and Wireless Networking Lab. 21 Management Issues – Flash-Memory Characteristics Example 2: Garbage Collection L D D L D D L D This block is to be recycled. L L D L L L F D (3 live pages and 5 dead pages) L F L L L L D F A live page F L L F L L F D A dead page A free page 3/29/2007 Embedded Systems and Wireless Networking Lab. 22 11
  12. 12. Management Issues – Flash-Memory Characteristics Example 2: Garbage Collection D D D D D D D D Live data are copied to somewhere else. L L D L L L L D L F L L L L D L A live page L L L F L L F D A dead page A free page 3/29/2007 Embedded Systems and Wireless Networking Lab. 23 Management Issues – Flash-Memory Characteristics Example 2: Garbage Collection F F F F F F F F The block is then erased. L L D L L L L D Overheads: •live data copying L F L L L L D L •block erasing. A live page L L L F L L F D A dead page A free page 3/29/2007 Embedded Systems and Wireless Networking Lab. 24 12
  13. 13. Management Issues – Flash-Memory Characteristics Example 3: Wear-Leveling Wear-leveling might 100 L D D L D D L D A interfere with the 10 decisions of the block- L L D L L L F D B recycling policy. 20 L F L L L L D F C A live page 15 A dead page F L L F L L F D D A free page Erase cycle counts 3/29/2007 Embedded Systems and Wireless Networking Lab. 25 Management Issues – Challenges The write throughput drops significantly after garbage collection starts! The capacity of flash-memory storage systems increases very quickly such that memory space requirements grows quickly. Reliability becomes more and more critical when the manufacturing capacity increases! The significant increment of flash-memory access rates seriously exaggerates the Read/Program Disturb Problems! 3/29/2007 Embedded Systems and Wireless Networking Lab. 26 13
  14. 14. Agenda Introduction Management Issues Performance vs Overheads – FTL vs NFTL Other Challenging Issues Conclusion 3/29/2007 Embedded Systems and Wireless Networking Lab. 27 System Architecture fwrite(file,data) process process process process Applications File system (FAT, EXT2, NTFS......) File Systems Block write (LBA,size) FTL/NFTL Garbage Address Layer Collection Translation Flash I/O Requests Flash-Memory Storage System Device Driver Control signals Physical Devices (Flash Memory Banks) 3/29/2007 Embedded Systems and Wireless Networking Lab. 28 14
  15. 15. Management Issues – Flash- Memory Characteristics *FTL: Flash Translation Layer, MTD: Memory Technology Device 3/29/2007 Embedded Systems and Wireless Networking Lab. 29 Policies – FTL FTL adopts a page-level address translation mechanism. The main problem of FTL is on large memory space requirements for storing the address translation information. 3/29/2007 Embedded Systems and Wireless Networking Lab. 30 15
  16. 16. Policies – NFTL (Type 1) A logical address under NFTL is divided into a virtual block address and a block offset. e.g., LBA=1011 => virtual block address (VBA) = 1011 / 8 = 126 and block offset = 1011 % 8 = 3 NFTL A Chain Block A Chain Block A Chain Block Address Translation Table Address = 9 Address = 23 Address = 50 Write data to (in main-memory) LBA=1011 Free Free Free Free Free Free . . Free Free Free . Used Used Free Free (9) Free Free Free . WriteIfto the Write to the the page has . Block Free with blockFree page been used with block page Free . Offset=3 VBA=126 Freeoffset=3 Freeoffset=3 Free 3/29/2007 Embedded Systems and Wireless Networking Lab. Free Free Free 31 Policies – NFTL (Type 2) A logical address under NFTL is divided into a virtual block address and a block offset. e.g., LBA=1011 => virtual block address (VBA) = 1011 / 8 = 126 and block offset = 1011 % 8 = 3 NFTL A Primary Block A Replacement Block Address Translation Table Address = 9 Address = 23 (in main-memory) Write data to Free Used LBA=1011 Free Used . . Free Used . Used Free (9,23) Free Free . If the page has been . Block Write to the used Free Free . Offset=3 first free page VBA=126 Free Free 3/29/2007 Free Embedded Systems and Wireless Networking Lab. Free 32 16
  17. 17. Policies – NFTL NFTL is proposed for the large-scale NAND flash storage systems because NFTL adopts a block-level address translation. However, the address translation performance of read and write requests might deteriorate, due to linear searches of address translation information in primary and replacement blocks. 3/29/2007 Embedded Systems and Wireless Networking Lab. 33 Policies – FTL or NFTL FTL NFTL Memory Space Requirements Large Small Address Translation Time Short Long Garbage Collection Overhead Less More Space Utilization High Low The Memory Space Requirements for one 1GB NAND (512B/Page, 4B/Table Entry, 32 Pages/Block) FTL: 8,192KB (= 4*(1024*1024*1024)/512) NFTL: 256KB (= 4*(1024*1024*1024)/(512*32)) Remark: Each page of small-block(/large-block) SLC NAND can store 512B(/2KB) data, and there are 32(/64) pages per block. Each page of MLCx2 NAND can store 2KB, and there are 128 pages per block. 3/29/2007 Embedded Systems and Wireless Networking Lab. 34 17
  18. 18. Address Translation Time - NFTL The address translation performance of read and write requests can be deteriorated, due to linear searches of physical addresses. 1. Assume that each block contains 8 pages. 2. Let LBA A, B, C, D, and E be written for 5, 5, 1, 1, and 1 times, respectively. Their data distribution could be like to what in the left figure. 3. For example, it might need to scan 9 spare areas for LBA B. 3/29/2007 Embedded Systems and Wireless Networking Lab. 35 Garbage Collection Overhead - NFTL 1. Copy the most-recent content to the new primary block. 2. Erase the old primary block and the replacement block. 3. Overhead is 2 block erases and 5 page writes. 3/29/2007 Embedded Systems and Wireless Networking Lab. 36 18
  19. 19. Space Utilization - NFTL 3 free pages are wasted. 3/29/2007 Embedded Systems and Wireless Networking Lab. 37 Agenda Introduction Management Issues Performance vs Overheads – An Adaptive Two-Level Mapping Mechanism Other Challenging Issues Conclusion 3/29/2007 Embedded Systems and Wireless Networking Lab. 38 19
  20. 20. Motivation An adaptive two-level management design of a flash translation layer, called AFTL. Exploit the advantages of the fine-grained address mechanism and the coarse-grained address mechanism. FTL NFTL AFTL Memory Space Large Small A little larger than Requirements NFTL Address Translation Short Long Much Better than Time NFTL Garbage Collection Less More Much Better than Overhead NFTL Space Utilization High Low Much Better than NFTL 3/29/2007 Embedded Systems and Wireless Networking Lab. 39 AFTL – Coarse-to-Fine Switching 1. AFTL doesn’t erase the two blocks immediately. 2. AFTL moves the RPBA + 5 mapping information of RPBA + 7 the replacement block to the fine-grained hash table by adding fine- PPBA RPBA grained slots. 3. The RPBA field of the (VBA, PPBA −1) (VBA, PPBA, ,RPBA) corresponding mapping information is nullified. Chin-Hsien Wu and Tei-Wei Kuo, 2006, “An Adaptive Two-Level Management for the Flash Translation Layer in Embedded Systems,” IEEE/ACM 2006 International Conference on Computer-Aided Design (ICCAD), November 5-9, 2006. 3/29/2007 Embedded Systems and Wireless Networking Lab. 40 20
  21. 21. AFTL – Fine-to-Coarse Switching The number of the fine-grained slots is limited. Some least recently used mapping information of fine-grained slots should be moved to the coarse-grained hash table. 1. Assume that this fine-grained slot is to be replaced. 2. Data stored in the page with the (F, RPBA + 5 PBAE) given (physical) address are RPBA + 7 copied to the primary or PPBA RPBA replacement block of the corresponding coarse-grained slot, as defined by NFTL. (VBA, PPBA, RPBA) 3. If there dose not exist any corresponding coarse-grained slot, a new one is created. 3/29/2007 Embedded Systems and Wireless Networking Lab. 41 AFTL – Fine-to-Coarse Switching Coarse-to-fine switches would introduce fine-to- coarse switches and overhead in valid page copying. It is because the number of the fine-grained slots is limited. Stop any coarse-to-fine switch when some frequency bound in coarse-to-fine switches is reached. We set a parameter in the experiments to control the frequency of switches to explore the behavior of the proposed mechanism. 3/29/2007 Embedded Systems and Wireless Networking Lab. 42 21
  22. 22. The Advantages of AFTL Improve the address translation performance. It is because the moving of their mapping information to the fine-grained hash table. Improve the garbage collection δcg. RPBA + 5 δcg. RPBA + 7 overhead. The delayed recycling of any replacement block δ cg.PPBA δ cg.RPBA reduces the potential number of valid data copyings and blocks erased. (δ cg.VBA, δ cg PPBA, δ cgRPBA) Improve the space utilization. The delayed recycling of any primary block lets free pages of a primary block be likely used in the future. Chin-Hsien Wu and Tei-Wei Kuo, 2006, “An Adaptive Two-Level Management for the Flash Translation Layer in Embedded Systems,” IEEE/ACM 2006 International Conference on Computer-Aided Design (ICCAD), November 5-9, 2006. 3/29/2007 Embedded Systems and Wireless Networking Lab. 43 Agenda Introduction Management Issues Performance vs Overheads – Performance Evaluation Other Challenging Issues Conclusion 3/29/2007 Embedded Systems and Wireless Networking Lab. 44 22
  23. 23. Performance Evaluation Performance Setup The characteristics of the experiment trace was over a 20GB disk. CPU Intel Celeron 750MHz RAM 320 MB OS Windows XP File Systems NTFS Applications Web Applications, E-mail Clients, MP3 Player, MSN Messenger, Word, Excel, PowerPoint, Media, Player, Programming, and Virtual Memory Activities Durations One week Total Write / Read Requests 13,198,805 / 2,797,996 sectors Different LBA’s 1,669,228 3/29/2007 Embedded Systems and Wireless Networking Lab. 45 Performance Evaluation Performance Setup The maximum number of fine-grained slots is controlled by a parameter MFS. A parameter ST controls the frequency of switches between the two address translation mechanisms – n/ST. ST=0 => No constraint on the number of switches. Smaller ST => More switches. Larger ST => Less switches. 3/29/2007 Embedded Systems and Wireless Networking Lab. 46 23
  24. 24. Memory Space Requirements 1200 AFTL NFTL 1000 800 Memory Space(K) 600 400 200 0 L 0 0 0 0 0 0 0 0 0 00 50 00 FT ,5 ,0 ,5 0, 2, 5, =2 =5 =7 N =1 =1 =1 FS FS FS FS FS FS M M M M M M 1. MFS ranged from 2,500, 5,000, 7,500, 10,000, 12,500, to 15,000. 2. AFTL uses a little more memory space than NFTL. 3/29/2007 Embedded Systems and Wireless Networking Lab. 47 Address Translation Performance 1000000 ST=64 ST=32 ST=16 ST=0 NFTL Address Translation Time (ms) 950000 900000 850000 800000 750000 700000 650000 600000 0 0 0 00 00 00 L 00 50 00 FT ,5 ,0 ,5 0, 2, 5, =2 =5 =7 N =1 =1 =1 FS FS FS FS FS FS M M M M M M 1. Larger MFS => smaller address translation time - More address translations going through the fine-grained address translation mechanism. 2. Smaller ST => longer address translation time - More coarse-to-fine switches 3/29/2007 Embedded Systems and Wireless Networking Lab. 48 24
  25. 25. Garbage Collection Overhead 550000 ST=64 ST=32 ST=16 ST=0 NFTL 10 ST=64 ST=32 ST=16 ST=0 NFTL A v e ra g e N u m b e r o f V a li d P a g e s 530000 N u m b e r o f B l o c k s E ra s e d 510000 9 490000 8 470000 450000 7 C o p ie d 430000 6 410000 390000 5 370000 350000 4 TL TL 0 00 0 00 00 0 00 00 00 00 0 0 ,50 ,50 ,5 0 NF ,50 ,00 5 ,0 2,5 5,0 0,0 2,5 5,0 NF 0 ,0 =7 =2 =7 12 15 S= S= S= =1 =1 =1 =1 FS FS FS S= S= MF MF MF FS FS FS FS M MF MF M M M M M M AFTL outperforms NFTL. - Coarse-to-fine switches can avoid immediate recycling of their primary and replacement blocks and related valid data copyings. 3/29/2007 Embedded Systems and Wireless Networking Lab. 49 Space Utilization 3 ST=64 ST=32 ST=16 ST=0 NFTL Average Number of Free Pages Left 2.5 2 1.5 1 0.5 0 0 0 0 0 0 0 L 00 50 00 50 00 50 FT 0, 2, 5, , , , =2 =5 =7 N =1 =1 =1 FS FS FS FS FS FS M M M M M M The Space utilization might be better under AFTL. - Coarse-to-fine switches can delay the recycling of replacement blocks. - Free pages of primary blocks might be used in the future.. 3/29/2007 Embedded Systems and Wireless Networking Lab. 50 25
  26. 26. Summary δcg. RPBA + 5 δcg. RPBA + 7 AFTL is proposed to δ cg.PPBA δ cg.RPBA exploit the advantages of fine- grained/coarse-grained address (δ cg.VBA, δ cg PPBA, δ cgRPBA) translation mechanisms, and to switch dynamically and adaptively the mapping information between the two address translation mechanisms. AFTL does provide good performance in address mapping and space utilization and have garbage collection overhead and memory space requirements under proper management. 3/29/2007 Chin-Hsien Wu and Tei-Wei Kuo, 2006, “An Adaptive Two-Level Management for the Flash Translation Layer in Embedded Systems,” 51 Embedded Systems and Wireless Networking Lab. IEEE/ACM 2006 International Conference on Computer-Aided Design (ICCAD), November 5-9, 2006. Agenda Introduction Management Issues Performance vs Overheads Other Challenging Issues Conclusion 3/29/2007 Embedded Systems and Wireless Networking Lab. 52 26
  27. 27. Challenging Issues – Reliability Each Word Line is connected to control gates. Each Bit Line is connected to the drain. Control Gate Drain Source Cell IDS Selected cell 3/29/2007 Embedded Systems and Wireless Networking Lab. 53 Challenging Issues – Reliability Read Operation Program Operation When the floating gate is Electrons are moved into not charged with electrons, the floating gate, and the there is current ID (100uA) threshold voltage is thus if a reading voltage is raised. applied. (“1” state) 5V 1V 3/29/2007 Embedded Systems and Wireless Networking Lab. 54 27
  28. 28. Challenging Issues – Reliability Over-Erasing Problems Fast Erasing Bits à All of the cells connected to the same bit line of a depleted cell would be read as “1”, regardless of their values. Read/Program Disturb Problems DC erasing of a programmed cell, DC programming of a non-programmed cell, drain disturb, etc. Flash memory that has thin gate oxide makes disturb problems more serious! Data Retention Problems Electrons stored in a floating gate might be lost such that the lost of electrons will sooner or later affects the charging status of the gate! 3/29/2007 Embedded Systems and Wireless Networking Lab. 55 Challenging Issues – Observations The write throughput drops significantly after garbage collection starts! The capacity of flash-memory storage systems increases very quickly such that memory space requirements grows quickly. Reliability becomes more and more critical when the manufacturing capacity increases! The significant increment of flash-memory access rates seriously exaggerates the Read/Program Disturb Problems! Wear-leveling technology is even more critical when flash memory is adopted in many system components or might survive in products for a long life time! 3/29/2007 Embedded Systems and Wireless Networking Lab. 56 28
  29. 29. Wear Leveling versus Product Lifetime Settings File system: FAT16 file system with 8KB cluster size Flash memory: 256MB small-block flash memory with 100K erase cycles Updating of a 16MB file repeatedly with the throughput: 0.1MBs The file requires 2K clusters = 16MB ÷ 8KB(cluster size) The FAT size of this file is 4KB (2K(clusters) x 2 bytes) The 20% of blocks in flash memory joins the dynamic wear leveling Data of a 16MB file is stored in 1K blocks (16MB ÷ 16KB(block size)) Suppose flash memory is managed in the block level File systems update the FAT in each cluster writing so that FAT is updated 2K times for a 16MB file Writing of a 16MB incurs 1K block erases because of the reclaiming of invalid space. 3/29/2007 Embedded Systems and Wireless Networking Lab. 57 Wear Leveling versus Product Lifetime Ways in Data Updates In-Place-Updates: Rewriting on the Same Page Dynamic Wear Leveling: Rewriting over Another Free Page with Erasing over Blocks with Dead Pages Static Wear Leveling: Rewriting over Another Free Page with Erasing over Any Blocks Expected Lifetime of 16(MB) 100K NO Wear Leveling (in - place update) = × ≈ 0.09(days) 0.1(MB/second) 2K × 24 × 60 × 60 16(MB) 16K (blocks) × 20% ×100K Dynamic Wear Leveling = × ≈ 197.5(days) 0.1(MB/second) (2 K + 1K ) × 24 × 60 × 60 16(MB) 16K (blocks) ×100% ×100K Static Wear Leveling = × ≈ 987.5(days) 0.1(MB/second) (2 K + 1K ) × 24 × 60 × 60 3/29/2007 Embedded Systems and Wireless Networking Lab. 58 29
  30. 30. Wear Leveling versus Product Lifetime Static Wear Leveling – Block-Level Mapping Use a counter for each block The garbage collector always finds the block with the least erase count. Some heuristic approach erases a block to maintain 2 free blocks when the garbage collector finds the erase count of the block is over a given threshold. Problems: GC startsà find a victim High extra block erases and GC starts data to block Update data in block 3 4 Write new block 15 block live-page copyings High main-memory consumption 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 High computation cost Flash Memory : index in the selection of a victim block : index to the selected free block 5 5 5 5 4 5 5 4 5 5 4 5 4 5 5 5 4 5 4 4 5 Counter : block contains (some) valid data : free block : dead block 3/29/2007 Embedded Systems and Wireless Networking Lab. 59 Conclusion Summary The Characteristics of Flash Memory and Management Issues Popular Implementations: FTL vs NFTL Adaptive Two-Level Address Translation Performance, Cost, and Reliability Challenges 3/29/2007 Embedded Systems and Wireless Networking Lab. 60 30
  31. 31. Conclusion What Is Happening? Solid-State Storage Devices New Designs in the Memory Hierarchy More Applications in System Components and Products Challenging Issues: Performance, Cost, and Reliability Scalability Technology Reliability Technology Customization Technology 3/29/2007 Embedded Systems and Wireless Networking Lab. 61 Contact Information • Professor Tei-Wei Kuo l ktw@csie.ntu.edu.tw l URL: http://csie.ntu.edu.tw/~ktw l Flash Research: http://newslab.csie.ntu.edu.tw/~flash/ l Office: +886-2-23625336-257 l Fax: +886-2-23628167 l Address: Dept. of Computer Science & Information Engr. National Taiwan University, Taipei, Taiwan 106 3/29/2007 Embedded Systems and Wireless Networking Lab. 62 31
  32. 32. Q&A 32

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