hyperstone 32-Bit Flash Memory Controller User's Manual

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  • 1. Hyperstone F3-16X 32-Bit Flash Memory Controller Preliminary
  • 2. Specifications and information in this document are subject to change without notice and do not represent a commitment on the part of Hyperstone AG. Hyperstone AG reserves the right to make changes to improve functioning. Although the information in this document has been carefully reviewed, Hyperstone AG does not assume any liability arising out of the use of the product or circuit described herein. Hyperstone AG does not authorize the use of the Hyperstone microprocessor in life support applications wherein a failure or malfunction of the microprocessor may directly threaten life or cause injury. The user of the Hyperstone microprocessor in life support applications assumes all risks of such use and indemnifies Hyperstone AG against all damages. No part of this manual may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose without the permission of Hyperstone AG. Hyperstone is a registered trademark of Hyperstone AG. For further information please contact: Hyperstone AG Line-Eid Str. 3 D-78467 Konstanz Germany Phone +49 – 7531 - 98030 Fax +49 – 7531 - 51725 E-Mail info@hyperstone.de URL: http://www.hyperstone.com © Copyright 1990 – 2005 Hyperstone AG
  • 3. TABLE OF CONTENTS 1 Table of Contents 1. Features ...............................................................................................................2 1.1. Host interface...........................................................................................2 1.2. Flash Memory Interface ..........................................................................2 1.3. Controller Core........................................................................................2 2. General Description.............................................................................................3 3. Bus Signals ..........................................................................................................6 4. Functional Description ........................................................................................9 4.1. Block Diagram.........................................................................................9 4.2. System Memory Map ............................................................................10 4.3. Direct Flash Access Logic.....................................................................11 4.4. Flash Memory Interface ........................................................................12 4.5. ECC Unit ...............................................................................................12 4.6. Hyperstone Sector Buffer Access..........................................................13 4.7. Internal ROM.........................................................................................13 4.8. Ultra DMA ............................................................................................13 CONFIDENTIAL, distribution of this document without prior permission of Hyperstone will be prosecuted
  • 4. 2 CONFIDENTIAL Preliminary Features 1. Features 1.1. Host interface r PCMCIA 2.1, 3.0 and PC Card ATA standard compatible r Memory mapped or I/O operation r Fast ATA host-to-buffer transfer rates supporting PIO mode 6, MDMA mode 4, UDMA mode 5 in True-IDE mode r Automatic sensing of PCMCIA or True-IDE host interface mode r Dual integrated 512 Byte PCMCIA Sector Buffers and 256 Byte PCMCIA Attribute Memory r PCMCIA Configuration Option Register, Card Configuration and Status Register and Pin Replacement Register support 1.2. Flash Memory Interface r Supports dual flash access channel r Supports all control signal for serial type flash memory connection r Supports direct connection of up to 16 flash memory chips. Eight per channel r Supports 32, 64, 128, 256, 512Mbit, 1, 2, 4, 8, 16 Gbit NAND type flash memories r Supports 256 Mbit, 1Gbit and 4Gb AG-AND type flash memories r Flash memory power down logic and flash memory write protect control r Firmware storage in flash memory r Firmware is loaded into internal memory by the boot ROM r Error Correcting Code capable of correcting 4 symbols in a 512 bytes sector r On-chip voltage regulator for 3.3V/1.8V flash memory power supply r On-chip voltage regulator for 2.5V processor core power supply 1.3. Controller Core r High performance microprocessor core based on the Hyperstone architecture r Clock frequency from 10MHz to 60MHz using trimmable internal oscillator r 16 Kbyte Internal Boot ROM r 20 Kbyte internal RAM r Automatic power-down mode during wait periods for host data or flash memory operation completion r Automatic sleep mode during host inactivity periods, Icc << 100 µA r 0.25 µm CMOS technology r Supply voltage 5.0V ±10% or 3.3V ±10% CONFIDENTIAL, distribution of this document without prior permission of Hyperstone will be prosecuted
  • 5. GENERAL DESCRIPTION 3 2. General Description The Hyperstone F3-16X flash memory controller is among the most powerful single-chip controllers on the market for designing ATA based Flash Memory PC Cards / CompactFlash Cards. The required external component count is reduced to a bare minimum of few passive components enabling the design of very low-cost but high- performance ATA flash memory cards / CompactFlash Cards. The Hyperstone F3-16X flash memory controller can operate with NAND or AG-AND type flash memory devices. It operates with 5.0V and 3.3V and enables automatic voltage detection for the cards. A highly sophisticated Error Correction Code and a wear-leveling algorithm are also implemented. A complete set of development tools is available which enables you to design ATA Flash Memory Cards / CompactFlash Cards with a very competitive cost/performance ratio. The main features of Hyperstone F3-16X flash memory controller are: r Inexpensive single-chip controller for ATA flash memory cards / CompactFlash cards r Full support for all NAND and AG-AND type flash memories, as well as Samsung MLC and Toshiba SLC/MLC flash chips. r Built-in 3.3V/1.8V voltage regulator for flash memory supply r Built-in 2.5V voltage regulator for processor core supply r Built-in PC card / CompactFlash Interface r Data transfer rate to flash memories: up to 80 MBytes/s r Data transfer rate PIO mode 6 / MDMA mode 4 up to 25 MB/sec r Data transfer rate UDMA mode 5 up to 100 MBytes/s r Supports True-IDE mode r On-chip ECC unit r Sophisticated software for wear leveling r Automatic power-down mode and sleep mode r Direct flash access (DFA) mechanism r Dual flash access channel r Available for low-cost/high performance CompactFlash Card applications, supporting up to 16 flash memory chips. 8 chips per channel The Hyperstone F3-16X single-chip controller for ATA Flash Memory Cards / CompactFlash Cards is based on the Hyperstone E1-32X microprocessor core providing a modern 32-bit RISC architecture. The controller’s flash memory interface allows the direct connection of up to 16 flash memory chips and supports either NAND type or AG-AND type flash memories (32 Mbit to 16 Gbit). Additionally, the chip will give support for Samsung and Toshiba MLC flash chips. Next-generation flash memories will be supported as well. Through the sophisticated memory interface of the Hyperstone F3-16X, your flash memory card will achieve a superior performance with a data transfer rate to flash memories of up to 80 MBytes/s. An on-chip ECC and CRC16 unit generates the required code bytes for error detection and correction of up to four random bytes per 512 Byte data CONFIDENTIAL, distribution of this document without prior permission of Hyperstone will be prosecuted
  • 6. 4 GENERAL DESCRIPTION sector. Code byte generation during write operations as well as error detection during read operation is implemented on the fly without any speed penalties. The controller is implemented with a powerful direct flash access (DFA) mechanism and two access channels, to flash memory chips, which can operate in parallel. An additional feature, is the possibility to cascade several controllers; in order to make storage systems that use 32, 64, or more flash memory chips. The controller is equipped with 20 KByte internal memory that is used for storage of code and data. The internal memory can also be used as an intermediate memory for storing data blocks during a wear-leveling procedure. The Hyperstone F3-16X controller works at power supply voltages of 5.0V as well as 3.3V. It provides a built-in voltage regulator of 3.3V/1.8V to supply flash memories with the required voltage even when the interface from the host offers just a voltage of 5.0V. An 16 KByte internal boot ROM includes basic routines for accessing the flash memories and for loading the main code into the internal memory of the Hyperstone F3-16X. This boot concept offers a high degree of flexibility while keeping the component count small. The PC Card / CompactFlash interface provides all required signals and is fully compliant with the PC Card standard Rel. 2.1 and 3.0. The PC Card controller part of the Hyperstone F3-16X includes 256 Byte attribute memory, PCMCIA configuration and status registers, two 512 Byte sector buffers and the complete ATA register set. Optionally, the controller can be operated in True-IDE mode. It supports UDMA transfer mode 5, allowing maximum performance. CONFIDENTIAL, distribution of this document without prior permission of Hyperstone will be prosecuted
  • 7. GENERAL DESCRIPTION 5 3. Bus Signals 3.1 Bus Signals for the F3-16X Flash Memory Controller The following table is an overview of the bus signals of the Hyperstone F3-16X flash memory controller. The signal states are defined as I = input, O = output, pu = pull-up, pd = pull-down, h = hold and s = strong. Status Pins Signal Name Description F3-16X Flash Memory Control O 1 FWE# Flash Write Enable. Channel 0 O 1 FEW#_1 Flash Write Enable. Channel 1 O 1 FOE# Flash Output Enable. Channel 0 O 1 FOE#_1 Flash Output Enable. Channel 1 I/pu/s 8 FRDY0(3:0) Flash Ready/Busy. Channel 0 I/pu/s 8 FRDY_1(3:0) Flash Ready/Busy. Channel 1 O/pd 1 FRES# Flash Reset/Write Protect . Channel 0 O/pd 1 FRES#_1 Flash Reset/Write Protect . Channel 1 O 1 ALE Flash ALE. Channel 0 O 1 CLE Flash CLE. Channel 0 O 1 ALE_1 Flash ALE. Channel 1 O 1 CLE_1 Flash CLE. Channel 1 O 8 CE(7:0) Flash CE signals. Channel 0 O 8 CE_1(7:0) Flash CE signals. Channel 1 O 8 FD(7:0) Flash data bus. Channel 0 O 8 FD_1(7:0) Flash data bus. Channel 1 PC Card Interface I/pu 1 PCE1# Card Enable 1 I/pu 1 PCE2# Card Enable 2 I/h 1 PREG# Attribute Memory or I/O Enable I/pu 1 PWE# Memory Write Enable, Service Mode I/pu 1 POE# Memory Output Enable, True-IDE Mode Select I/pu 1 PIOWR# I/O Write Enable I/pu 1 PIORD# I/O Read Enable I/pu 1 PCSEL# True-IDE Chip Select I/h 1 PRESET Reset Signal I/h 11 PA(10..0) Address Bus I/O/h 16 PD(15..0) Data Bus O 1 PIOIS16# Write Protect / 16-bit I/O Transfer O 1 PINPACK# Input Acknowledge O/pu 1 PIREQ# Ready/Busy / Interrupt Request O/pu 1 PSTSCHG# Status Change / True-IDE DIAG CONFIDENTIAL, distribution of this document without prior permission of Hyperstone will be prosecuted
  • 8. 6 GENERAL DESCRIPTION States Pins Signal Name Description F3-16X O/pu 1 PSPKR# Speaker / DMA Request / True-IDE DASP I/O/pu 1 PWAIT# Wait Signal (input for service mode only) Output DDMARDY*,DSTROBE @ UDMA General Control O 1 BUSRQ# Multiple Controller Bus Request I 1 RESET# Reset Debugging I/pd 1 UART_CLK Debugging UART Clock I/pu 1 UART_RX Debugging UART Receive Data O 1 UART_TX Debugging UART Transmit Data Table 1: Bus Signals for the F3-16X Flash Memory Controller CONFIDENTIAL, distribution of this document without prior permission of Hyperstone will be prosecuted
  • 9. GENERAL DESCRIPTION 7 3.2 Bus Signal Description The following section describes the bus signals for the Hyperstone F3-16X controller in detail. In the following signal description, the signal states are defined as I = input, O = output, U = pull-up, D = pull-down. O ALE Connect to the flash ALE# pin in Chanel 0. O CLE Connect to the flash CLE# pin in Channel 0. O ALE_1 Connect to the flash ALE# pin in Channel 1. O CLE_1 Connect to the flash CLE# pin in Channel 1. O CE7..CE0 Chip select signals for up to 8 Flash memory chips in channel 0 O CE7_1.. CE0_1 Chip select signals for up to 8 Flash memory chips in channel 1 O/I FD7..FD0 Data bus. The signals D7..D0 represent the bidirectional data bus connected to the flash data bus in Channel 0; active high signals a "one". O/I FD7_1..FD0_1 Data bus. The signals D7..D0 represent the bidirectional data bus connected to the flash data bus in Channel 1; active high signals a "one". O BUSRQ# Multiple Controller Bus Request. This pin is used for the communication between multiple controllers connected to the PCMCIA bus. I RESET# Reset processor. RESET# low resets the processor to the initial state and halts all activity. RESET# must be low for at least one cycle. On a transition from low to high, a Reset exception occurs and the processor starts booting from. The transition may occur asynchronously to the clock. If the reset input is not needed, this pin must be high. In this case, an internal voltage detector will generate a reset pulse of about 0.5ms when the supply voltage has reached about 1.5V. I,U PCE1# PCMCIA Card Enable 1 I,U PCE2# PCMCIA Card Enable 2 I PREG# PCMCIA Attribute Memory or I/O Enable I,U PWE# PCMCIA Memory Write Enable, Service Mode select (see Boot ROM description) I,U POE# PCMCIA Output Enable, True-IDE Mode select I,U PIOWR# PCMCIA I/O Write Enable I,U PIORD# PCMCIA I/O Read Enable I,U PCSEL# True-IDE Master/Slave select I PRESET PCMCIA Reset signal. This pin includes an input filter that filters pulses shorter than about 40 ns. I PA(10..0) PCMCIA Address Bus CONFIDENTIAL, distribution of this document without prior permission of Hyperstone will be prosecuted
  • 10. 8 GENERAL DESCRIPTION I/O PD(15..0) PCMCIA Data Bus O PIOIS16# PCMCIA Write Protect / I/O is 16 bit signal O PINPACK# PCMCIA Input Achnowledge O,U PIREQ# PCMCIA Ready/Busy signal / Interrupt Request O,U PSTSCHG# PCMCIA Status Change / True-IDE DIAG O,U PSPKR# PCMCIA Speaker / True-IDE DASP I/O PWAIT# PCMCIA Wait (input for service mode only. As output, DDMARDY*,DSTROBE @ UDMA O FWE# NAND Flash Memory Write Enable in Channel 0. Connect to the flash WE# pin. O FOE# NAND Flash Output Enable in Channel 0. Connect to the flash RE# pin. O FEW#_1 NAND Flash Memory Write Enable in Channel 1. Connect to the flash WE# pin. O FOE#_1 NAND Flash Output Enable in Channel 1. Connect to the flash RE# pin. I,U FRDY3..FRDY0 NAND Flash Ready/Busy signals. FRDY3..FRDY0 are connected to the 8 flash memory chips in Channel 0.FRDY3 is connected to flash chips 7 and 3, FRDY2 to chips 6 and 2, FRDY1 to chips 5 and 1, FRDY0 to chips 4 and 0. In a similar way, FRDY7..FRDY4 are distributed in Channel 1. In order that this works properly, flash chips sharing the same ready/busy line must not be issued at the same time. I,U FRDY3_1..FRDY0_1 NAND Flash Ready/Busy signals. FRDY3..FRDY0 are connected to the 8 flash memory chips in Channel 0.FRDY3 is connected to flash chips 7 and 3, FRDY2 to chips 6 and 2, FRDY1 to chips 5 and 1, FRDY0 to chips 4 and 0. In a similar way, FRDY3_1..FRDY0_1 are distributed in Channel 1. In order that this works properly, flash chips sharing the same ready/busy line must not be issued at the same time. O,D FRES# NAND Flash Write Protect/Reset signal. Connect to the flash WP# pin in Channel 0. O,D FRES#_1 NAND Flash Write Protect/Reset signal. Connect to the flash WP# pin in Channel 1. I/U UART_CLK Debugging UART Clock Input. I/U UART_RX Debugging UART Receive Data Input. O/U UART_TX Debugging UART Transmit Data Input. CONFIDENTIAL, distribution of this document without prior permission of Hyperstone will be prosecuted
  • 11. CONFIDENTIAL, distribution of this document without prior permission of Hyperstone will be prosecuted 9 4 Functional Description 4.1 Block Diagram 3.3V/1.8V Regulato r 16 Flash Channel 0 Memory DF Chips A 8 Bit Wide DF A Channel 1 Contro Card UDM ATA 512 Byte 256 Byte UAR Debug l Interface A Sector Buffer Attribute Memory T Registe PC Card / Compact Flash Interface 4.2 System Memory Map The processor provides on-chip all functions for controlling memory and peripheral devices. The number of bus cycles used for a memory or I/O access is also defined by the processor, thus, no external bus controllers are required. All memory and peripheral devices can be connected directly, pin by pin, without any glue logic. The memory address space is divided into 7 partitions as follows:
  • 12. 10 CONFIDENTIAL, distribution of this document without prior permission of Hyperstone will be prosecuted Address (Hex) Address Space Memory Type 4000 0000..7FFF FFFF MEM1 Not available 8000 0000..BFFF FFFF MEM2 external Flash Memory C000 0000..C7FF FFFF IRAM Internal RAM C800 0000..CFFF FFFF IRAM DFA, Sector Buffers, Attribute Memory D000 0000..D7FF FFFF MMIO Memory-Mapped I/O D800 0000..DFFF FFFF IROM Internal Boot ROM E000 0000..FFFF FFFF MEM3 Not available There are no access signals for external memory or I/O accesses, so the MEM0, MEM1 and MEM3 areas are not available to the user. 4.2.1 Memory-Mapped I/O Address Space The memory address space from 0xD000 0000 to 0xD7FF FFFF addresses the internal memory-mapped I/O peripherals. Address bits 0 and 1. Address bits 2 to 8 are select bits for up to 128 registers for each peripheral. Only word load or store accesses are allowed. The following table specifies the address ranges, selected by address bits 9 to 11: A11 A10 A9 Description 0 0 0 Interrupt Controller 0 0 1 ECC and CRC Unit / DFA Registers 0 1 0 ATA Task Files / PCMCIA Configuration Registers 0 1 1 PCMCIA Control / UDMA Registers 1 0 0 UART 1 1 0 Attribute Memory 256 bytes 4.3 Direct Flash Access Logic (DFA) The Direct Flash Access (DFA) Logic is a hardware means for transporting data between the Host Interface sector buffers and the external memory interface where usually the flash memory is connected. DFA can operate independently, relieving the CPU of the data transport tasks. The Hyperstone F3-16X supports two flash memory channels, each of them, working with a separate DFA unit. The DFA Unit includes two Program Buffers of 256 bytes each which can be accessed by the DFA Unit or the CPU. The selection, which of the buffers is accessed from the CPU side and from the DFA side, depends on the DFA Buffer Swap bit. The DFA buffers are available on the Hyperstone side in the IRAM access space, starting at C800 200016 4.4 Flash Memory Interface NAND type flash memory chips are connected to the Hyperstone F3-16X as described below.
  • 13. CONFIDENTIAL, distribution of this document without prior permission of Hyperstone will be prosecuted 11 Flash Chip Signal F3-16X CLE CLE ALE ALE CE# one of CE7..CE0 WE# FWE# RE# FOE# I/O 0 ... I/O 7 D0 ... D7 WP# FWP# Ready/Busy# one of FRDY3..FRDY0/FRDY3_1..FRDY0_1 CPU can access flash memory chips directly or through the DFA. Control signals and chips select are generated separately in CPU or DFA, but they share the same flash memory interface. At most 16 NAND flash chips, 8 per channel, can be connected to the Hyperstone F3-16X. Flash chip 0 CE# is CE0, chip 1 CE# is CE1, ... chip 7 CE# is CE7. 4.5 ECC and CRC Unit The ECC unit consists of the Parity Unit (parity byte generation), the Syndrome Unit (syndrome byte computation), and the CRC unit (CRC16 code generation). This unit implements a Reed-Solomon ECC over the GF(210) field that is able to detect and correct four random bytes in an ECC block. The maximum ECC block length is 1015 bytes. The parity information is 80 bits long, packed into 10 bytes for storage on the flash. Code generation and error detection are executed by hardware. Error correction is executed by software. 4.5.1 CRC Unit The CRC unit supports the error detection (as the Reed-Solomon ECC is not suitable for this). The CRC unit implements a 16 bit CRC generated by the standard CRC-XMODEM generator polynomial x16 + x15 + x10 + x 3 . The CRC calculation is executed during MEM2 read or write accesses, using the inverted byte present on the input or output data lines. The calculation processes one byte per clock cycle. The generated CRC result can be read from the CRC unit, through MMIO access. 4.6 Hyperstone Sector Buffer Access The sector buffers and the attribute memory are available on the Hyperstone side in the IRAM access space, starting at C800 000016. There are two sector buffers of 512 bytes and a 256-byte attribute memory. Read accesses to these memories are unrestricted, write accesses must always be in 32 bit units (byte or halfword write accesses are not allowed). The selection, which of the sector buffers is accessed from the Hyperstone side and from the host side, depends on the Sector Buffer Select bit, and on the Busy state. The access
  • 14. 12 CONFIDENTIAL, distribution of this document without prior permission of Hyperstone will be prosecuted modes are detailed in the following table. When Busy is 0, the host side (PCMCIA) always has access to sector buffer SB0 when Sector Buffer Select bit is 1, and to sector buffer SB1 when Sector Buffer Select bit is 0. The 256 byte attribute memory is mapped to 256 words in this address range. Busy Hyperstone Address Bits Hy Access Hy Access SB Select=1 SB Select=0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 x 0 x x 512 byte SB0 SB1 1 0 x x x 1 1 256 byte 0 0 Attribute Memory 4.7 Internal ROM The F3-16X begins booting from its internal boot ROM. The F3-16X has 16 Kbytes of internal ROM at address D000 000016 with a wraparound modulo 16 Kbytes up to DFFF FFFF16. At reset, the reset trap begins executing the internal boot ROM code at DFFF FFF816. 4.8 Ultra DMA UDMA makes it possible to transfer data to the host at higher rates. Ultra DMA uses Cyclical Redundancy Checking, offering a level of data protection. Hyperstone F3-16X supports Ultra DMA mode 5, achieving a data transfer rate up to 100 MB/s.
  • 15. CONFIDENTIAL, distribution of this document without prior permission of Hyperstone will be prosecuted 13 Hyperstone AG Line-Eid-Straße 3 D-78467 Konstanz Germany Phone +49 – 7531 - 98030 Fax +49 – 7531 - 51725 E-Mail info@hyperstone.de http://www.hyperstone.com