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  • 1. IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 3, MARCH 2009 265 High Injection Efficiency and Low-Voltage Programming in a Dopant-Segregated Schottky Barrier (DSSB) FinFET SONOS for NOR-type Flash Memory Sung-Jin Choi, Jin-Woo Han, Moon-Gyu Jang, Jin Soo Kim, Kwang Hee Kim, Gi Sung Lee, Jae Sub Oh, Myeong Ho Song, Yun Chang Park, Jeoung Woo Kim, and Yang-Kyu Choi Abstract—A dopant-segregated Schottky barrier (DSSB) Fin- electrons for programming at low voltage is therefore attractive FET silicon–oxide–nitride–oxide–silicon (SONOS) for NOR-type because of its high injection efficiency and absence of con- Flash memory is successfully demonstrated. Compared with a straints on the optimization of Vgs and Vds [2]. Previous reports conventional FinFET SONOS device, the DSSB FinFET SONOS device exhibits high-speed programming at low voltage. The sharp on source-side injection by the decoupling of hot electrons from dopant-segregated Schottky contact at the source side can gen- the drain field demonstrated a fast low-voltage programming erate hot electrons, and it can be used to provide high injection operation [1], [2]; however, that approach is difficult to adapt efficiency at low voltage without any constraint on the choice of the to NOR-type Flash memory because it requires extra processes proper gate and drain voltage. The DSSB FinFET SONOS device and different circuitry. is therefore a promising candidate for NOR-type Flash memory with high-speed and low-power programming. On the one hand, the dopant-segregated Schottky-barrier (DSSB)-based MOSFET has attracted considerable attention Index Terms—Dopant-segregated, FinFET, hot electrons, non- as a candidate for a high-performance device in future ULSIs volatile memory, NOR Flash, Schottky barrier, source-side injec- tion, silicon–oxide–nitride–oxide–silicon (SONOS). because of the enhanced injection velocity from the source side and low parasitic resistance at the S/D [3], [4]. In addition, DSSB devices, in particular, are expected to become high-speed I. I NTRODUCTION devices because the hot carrier injection from the source side can be generated by a unique band structure [4]–[6]. C HANNEL hot electron injection (CHEI) programming in conventional NOR-type Flash memories poses a constraint on the choice of the proper gate voltage (Vgs ) and drain voltage By using these hot electrons for programming, we suc- cessfully demonstrated a novel NOR-type Flash memory (Vds ). A high Vds is necessary to induce a high lateral electric cell based on DSSB FinFET devices with a silicon–oxide– field for the generation of hot electrons. Furthermore, a high Vgs nitride–oxide–silicon (SONOS) structure. In contrast to a is indispensable for attaining a sufficient vertical electric field conventional FinFET SONOS device, our approach achieves for the injection of hot electrons into a charge storage node. high-speed low-voltage programming due to the source-side Simultaneous optimization of the lateral and vertical electric injection of hot electrons that originate from the unique abrupt field is very difficult [1]. Moreover, the high voltage needed energy band structure. to generate adequate hot electrons for programming consumes a serious amount of power. The source-side injection of hot II. R ESULTS AND D ISCUSSION DSSB FinFET SONOS devices and conventional FinFET Manuscript received October 19, 2008. First published January 13, 2009; current version published February 25, 2009. This work was supported by the SONOS devices were fabricated on an SOI substrate. The National Research Program for the 0.1-Terabit Nonvolatile Memory Develop- process flow of the DSSB FinFET SONOS device is the same as ment Initiative, which is sponsored by Korea Ministry of Commerce, Industry that of our previous work [7], except for the formation of gate and Energy. The review of this letter was arranged by Editor T. Wang. S.-J. Choi, J.-W. Han, and Y.-K. Choi are with the Division of spacers and the dopant-segregated silicided S/D. For dopant- Electrical Engineering, School of Electrical Engineering and Computer segregated Schottky junctions, arsenic was implanted at a dose Science, Korea Advanced Institute of Science and Technology, Daejeon 305- of 5 × 1015 /cm2 with 5 keV of energy. After that, we formed a 701, Korea (e-mail: sjchoi@nobelab.kaist.ac.kr; jinu0707@nobelab.kaist.ac.kr; ykchoi@ee.kaist.ac.kr). dopant-segregated S/D junction by using nickel (Ni) silicidation M.-G. Jang is with the Electronics and Telecommunications Research Insti- with a two-step rapid thermal process to prevent unwanted tute, Daejeon 305-350, Korea (e-mail: jangmg@etri.re.kr). encroachment. J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, and J. W. Kim are with the National Nanofab Center, Daejeon 305-701, Fig. 1(a) explains the different injection point of hot electrons Korea (e-mail: jskim@nnfc.com; khkim@nnfc.com; comesee@nnfc.com; for the DSSB Flash memory device and the conventional Flash jsoh@nnfc.com; smh@nnfc.com; parkyc@nnfc.com; jwkim@nnfc.com). memory device under the programming bias condition of CHEI Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. (Vgs > 0 and Vds > 0). In the case of the conventional Flash Digital Object Identifier 10.1109/LED.2008.2010720 memory device, hot electrons are generated near the drain side 0741-3106/$25.00 © 2009 IEEE Authorized licensed use limited to: Korea Advanced Institute of Science and Technology. Downloaded on February 25, 2009 at 08:34 from IEEE Xplore. Restrictions apply.
  • 2. 266 IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 3, MARCH 2009 Fig. 1. (a) Comparison of the DSSB device and the conventional device in terms of the charge injection point of hot electrons. The generation and injection point of hot electrons is different in each case. (b) The simulated energy band diagram of both the DSSB device and the conventional device at a programming state. The DSSB device has a higher lateral electric field at the source side. Fig. 2. (a) Program and erase transient characteristics for various program voltages. The DSSB FinFET SONOS device has excellent program efficiency due to the source-side injection. However, the erase efficiency is similar to that of the control group. (b) The fresh state and postcycled retention characteristics where the device is under a high lateral electric field; the hot of the DSSB FinFET SONOS device. The Vth window is expected to be more electrons are then injected into the drain-side charge storage than 2 V after ten years of reading. node. However, the drain-side region has a low vertical electric field due to the low gate-to-drain potential difference (Vgd = Fig. 2(a) shows the measured programming and erasing Vg − Vd , Vd = Vdd ). As a result, the injection efficiency is transient characteristics. A comparative study was performed lowered. Moreover, due to high Vds , a Flash memory cell that with a conventional FinFET SONOS device with the diffused p- uses a conventional CHEI method is not readily suitable for n junction as a reference. The program conditions of Vgs = 7 V applications with a low power supply. and Vds = 4 V with tPGM = 350 ns exhibit a threshold voltage In contrast to a conventional device, however, the DSSB (Vth ) shift of 4.5 V in the DSSB FinFET SONOS device. device naturally has an abrupt band bending capability near The DSSB FinFET SONOS device and a conventional FinFET the source-side region, and this capability provides a naturally SONOS device for programming have a different Vth shift built-in high lateral electric field to generate sufficient source- value of approximately 3.5 V at a programming time of 350 ns. side hot electrons, even at a low voltage [4]–[6]. In addition, this This difference is attributed to the high lateral and vertical source-side region experiences a high vertical field due to the electric field at the source side, which would originate from high gate-to-source potential difference (Vgs = Vg − Vs , Vs = the sharp band bending caused by the dopant-segregated region 0 V). As a result, hot electrons are injected into the source-side as well as the intrinsic band profile. In a programming state, storage node rather than the drain-side storage node, thereby electrons injected from the source electrode via thermionic ensuring that the DSSB device has higher injection efficiency emission or a tunneling process are accelerated by the high than the conventional device. lateral electric field and can become hot at the source side. Fig. 1(b) shows a simulated energy band diagram of both The electrons can subsequently go over the tunnel oxide bar- cases in a programming state [8]. The magnitude of the sim- rier around the source side. As a result, the programming is ulated lateral electric field in a programming state is also more efficient. As expected, in the erasing state made by FN inserted. Note also that the DSSB FinFET SONOS device tunneling, there is no significant difference between the DSSB has larger lateral electric field than the conventional FinFET FinFET SONOS device and the conventional FinFET SONOS SONOS device under the same programming conditions. This device. result is mainly attributed to the intrinsic sharp band bending of The retention characteristics of the DSSB FinFET SONOS the DSSB junction at the source side. device at both the fresh state and the 1k postcycled state are Authorized licensed use limited to: Korea Advanced Institute of Science and Technology. Downloaded on February 25, 2009 at 08:34 from IEEE Xplore. Restrictions apply.
  • 3. CHOI et al.: HIGH INJECTION EFFICIENCY AND LOW-VOLTAGE PROGRAMMING IN A DSSB FinFET SONOS 267 preferentially inject into the source side in the DSSB FinFET SONOS device. The behavior of the DSSB FinFET SONOS device is exactly opposite to that of the conventional FinFET SONOS device. After the CHEI programming, the surface potential of the DSSB FinFET SONOS device is more sensitive to Vds in the reverse state than in the forward state because of the source-side injection of hot electrons. Even though the Vth shift, as well as the degradation of subthreshold swing (SS) caused by captured hot electrons at the drain side, is shown in the forward read state (τPGM = 320 ns), the amount of captured electrons at the drain side is much smaller than that at the source side. As a result, the Vth shift, as well as the degradation of SS, is not shown in high drain bias of the forward read state. On the other hand, this phenomenon is not shown in the relatively short programming time of 60 ns when the source- side injection is only occurred. Moreover, Fig. 3(a) shows the increased OFF-state current in relation to Vds during the reverse read operation. The data of the Vth shift and changed OFF-state current in relation to Vds are reconstructed in Fig. 3(b). As shown in Fig. 4, the simulated energy band diagrams of the forward and reverse read operation are plotted to explain the Vth shift and the changed OFF-state current in Fig. 3. The OFF- state current in the Schottky-barrier (SB) MOSFET is known to originate from the hole tunneling because of the narrowed tunneling width at the drain side [9]. In a reverse read operation (i.e., charge trapped region is in the drain side, and a read voltage is applied also to drain), the trapped charge can narrow the tunneling width of the drain side in an OFF state. As a result, the OFF-state current is more sensitive to Vds in the reverse read state than in the forward read state; it also increases in relation to the increment of Vds . Fig. 3. (a) Ids –Vgs characteristics as a parameter of Vds at the fresh and pro- grammed states in a forward and reverse read operation. (b) The reconstructed data of (a). The Vth shift and the OFF-state current are shown in relation to Vds . III. S UMMARY A novel DSSB FinFET SONOS device for NOR-type Flash memory is proposed. We demonstrate how the source-side injection of hot electrons achieves high-speed low-voltage pro- gramming with excellent injection efficiency and no constraints on the optimization of Vgs and Vds . Thus, the DSSB FinFET SONOS device is a promising candidate for attaining a lower programming voltage and power consumption. R EFERENCES [1] A. T. Wu, T. Y. Chan, P. K. Ko, and C. Hu, “A novel high-speed, 5-volt programming EPROM structure with source-side injection,” in IEDM Tech. Dig., 1986, pp. 584–587. [2] D. K. Y. Liu, C. Kaya, M. Wong, J. Paterson, and P. Shah, “Optimization of a source-side-injection FAMOS cell for Flash EPROM applications,” in IEDM Tech. Dig., 1991, pp. 315–318. Fig. 4. Simulated energy band diagram of a forward and reverse read state at [3] A. Kaneko, A. Yagishita, K. Yahashi, T. Kubota, M. Omura, K. Matsuo, the OFF-state. The trapped charges can narrow the tunneling width of the drain I. Mizushima, K. Okano, H. Kawasaki, T. Izumida, T. Kanemura, N. Aoki, side in the OFF-state. A. Kinoshita, J. Koga, S. Inaba, K. Ishimara, Y. Toyoshima, H. Ishiuchi, K. Suguro, K. Eguchi, and Y. Tsunashima, “High-performance FinFET shown in Fig. 2(b). These characteristics are measured at room with dopant-segregated Schottky source/drain,” in IEDM Tech. Dig., 2006, pp. 1–4. temperature. The Vth window is expected to have a value of 2 V [4] A. Kinoshita, T. Kinoshita, Y. Nishi, K. Uchida, S. Toriyama, after ten years. R. Hasumi, and J. Koga, “Comprehensive study on injection velocity To trace a position of the injected charges experimentally, enhancement in dopant-segregated Schottky MOSFETs,” in IEDM Tech. Dig., 2006, pp. 1–4. we analyzed the transfer characteristics after the CHEI pro- [5] K. Uchida, K. Matsuzawa, J. Koga, S. Takagi, and A. Toriumi, gramming as shown in Fig. 3(a). It confirms that hot electrons “Enhancement of hot-electron generation rate in Schottky source Authorized licensed use limited to: Korea Advanced Institute of Science and Technology. Downloaded on February 25, 2009 at 08:34 from IEEE Xplore. Restrictions apply.
  • 4. 268 IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 3, MARCH 2009 metal–oxide–semiconductor field-effect transistors,” Appl. Phys. Lett., and Y.-K. Choi, “Partially depleted SONOS FinFET for Unified RAM vol. 76, no. 26, pp. 3992–3994, Jun. 2000. (URAM)—Unified function for high-speed 1T DRAM and nonvolatile [6] H. C. Lin, C. Y. Lin, K. L. Yeh, R. G. Huang, M. F. Wang, C. M. Yu, memory,” IEEE Electron Device Lett., vol. 29, no. 7, pp. 781–783, T. Y. Huang, and S. M. Sze, “A novel implantless MOS thin-film transistor Jul. 2008. with simple processing, excellent performance and ambipolar operation [8] Taurus-Medici User’s Manual, Synopsys, Inc., Mountain View, CA, 2007. capability,” in IEDM Tech. Dig., 2000, pp. 857–859. [9] M. Jang, J. Oh, S. Maeng, W. Cho, and S. Lee, “Characteristics of erbium- [7] J.-W. Han, S.-W. Ryu, C.-J. Kim, S. Kim, M. Im, S.-J. Choi, J. S. Kim, silicided n-type Schottky-barrier tunnel transistors,” Appl. Phys. Lett., K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, vol. 83, no. 13, pp. 2611–2613, Sep. 2003. Authorized licensed use limited to: Korea Advanced Institute of Science and Technology. Downloaded on February 25, 2009 at 08:34 from IEEE Xplore. Restrictions apply.