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Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
Flash Memory Testing Flash Memory Testing
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Flash Memory Testing Flash Memory Testing

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  • 1. Flash Memory Testing Cheng-Wen Wu 吳誠文 Lab for Reliable Computing Dept. Electrical Engineering National Tsing Hua University
  • 2. Outline • Introduction to flash memories • Flash memory fault models − Disturbance faults − Conventional memory faults − Other flash memory faults • Flash memory test algorithms − March-based test algorithms − Diagonal test algorithms • Flash memory fault-coverage analysis − RAMSES-FT • Flash memory BIST • Flash memory BISD • Conclusions m08flash5.05 Cheng-Wen Wu, NTHU 2
  • 3. Flash Memory Testing • Testing nonvolatile memories: − Masked ROM---exhaustive; pseudorandom − PROM (OTP) & EPROM---dummy row − EEPROM & flash memory---dummy row? • Testing flash memory core is hard − Customized core and I/O − Isolation (accessibility) − Reliability issues: disturbances, over program/erase, under program/erase, data retention, cell endurance, etc. − Long program/erase time m08flash5.05 Cheng-Wen Wu, NTHU 3
  • 4. A Typical Test Flow of Flash Memories Fab Out Assembly UV Erase FT1 WP1 Burn-in Cycling Test FT2 WP2 m08flash5.05 Cheng-Wen Wu, NTHU 4
  • 5. Test Approaches • Reasonable fault models for reliability-related defects • Efficient test algorithms to reduce test time and increase fault coverage • Built-in self-test (BIST) circuit for embedded flash memories − Replace or reduce the requirement of ATE • “Built-in self-test and built-in self-repair will be essential to test embedded memories and to maintain production throughput and yield” [ITRS 2001] m08flash5.05 Cheng-Wen Wu, NTHU 5
  • 6. Flash Memory Overview • Flash memory can be programmed and erased electrically − Has the advantages of EPROM and EEPROM • A stacked gate transistor with both the control gate (CG) and floating gate (FG): Control gate Floating gate Source Drain D n+ n+ G P-Si S m08flash5.05 Cheng-Wen Wu, NTHU 6
  • 7. Flash Memory Program & Erase • Program(1 to 0): channel hot-electron (CHE) injection or Fowler- Nordheim (FN) electron tunneling • Erase (0 to 1): FN electron tunneling • By the entire chip or large blocks (flash erasure) • Different products have different program/erase mechanisms +12V GND Control Gate Control Gate GND +6V +12V floating Floating Gate Floating Gate Source Drain Source Drain Substrate Substrate Program: CHE injection Erase: FN-tunneling Write 0 Write 1 m08flash5.05 Cheng-Wen Wu, NTHU 7
  • 8. Flash Memory Read ID "1" "0" +5V Control Gate GND +1V Floating Gate ID ("1") Source Drain ∆VT Substrate Read ID("0") VT1 5V VT0 VGS I-V Curves • The Erase operation is much slower than the Program operation, which in turn is slower than the Read operation m08flash5.05 Cheng-Wen Wu, NTHU 8
  • 9. Flash Memory Cell Types • Stacked-gate Split-gate Select-gate • Operations: Read, Program, Erase (Flash Erase) − As opposed to Read and Write in RAM m08flash5.05 Cheng-Wen Wu, NTHU 9
  • 10. NOR-Array Structure m08flash5.05 Cheng-Wen Wu, NTHU 10
  • 11. NAND-Array Structure Select (drain) WL 1 WL 2 WL 3 WL 4 WL 16 Select (source) BL i m08flash5.05 Cheng-Wen Wu, NTHU 11
  • 12. Disturbance Example (I) Program Disturbance BL0 SL BL1 BL2 SL BL3 WL 0 0V 0V 6V Drain-Disturb on "Programmed Cell" WL 1 10V 10V 10V 0V 0V 6V 0V 0V Programming Gate-Disturb on "Erased Cell" WL 2 NOR-Type Common Ground – Standard (Stacked Gate) m08flash5.05 Cheng-Wen Wu, NTHU 12
  • 13. Disturbance Example (II) Read Disturbance BL0 SL BL1 BL2 SL BL3 WL 0 WL 1 5V 0V 1V Soft-Program on "Selected Cell" WL 2 m08flash5.05 Cheng-Wen Wu, NTHU 13
  • 14. Disturbance Example (III) Program Disturbance BL 0 BL 1 BL 2 3.3V 0V SSL 3.3V 3.3V Gate-Disturb on "Erased Cell" 0V WL 0 10V 2.8V 0V WL 1 18V 18V Program '1' Program '0' 2.8V 0V WL 2 10V 10V 2.8V 0V Gate-Disturb on "Programmed Cell" GSL 0V 0V m08flash5.05 Cheng-Wen Wu, NTHU 14
  • 15. Disturbance Example (IV) Read Disturbance Erase Disturbance BL0 BL1 BL2 BL0 BL1 BL2 5V 0.7V SSL 5V 5V SSL Floating Floating WL0 5V 5V WL0 21V 0V 21V 0V 21V WL1 0V 0V WL1 21V 0V 21V 0V 21V Vth=+2V Vth=-3V WL2 5V 5V WL2 21V 0V 21V 0V 21V soft-program GSL 5V 5V GSL Floating Floating m08flash5.05 Cheng-Wen Wu, NTHU 15
  • 16. Word-Line Program Disturb Fault (WPDF) Conditions: G 1.Victim cell initial value is a logic ‘1’ 2.Aggressor “1→0” (program) Control Gate Victim “1→0” (program) S Floating Gate D V(L) V(H) Source Drain V(H) Substrate V(L) B V(Gd) m08flash5.05 Cheng-Wen Wu, NTHU 16
  • 17. WPDF 0V 5V 0V 0V Addressed cell Be programmed 0V (aggressor) (victim) 12V 0V Source (0V) 0V m08flash5.05 Cheng-Wen Wu, NTHU 17
  • 18. Word-Line Erase Disturb Fault (WEDF) Conditions: G 1.Victim cell initial value is a logic ‘0’ 2.Aggressor “1→0” (program) Control Gate Victim “0→1” (erase) S Floating Gate D V(L) V(H) Source Drain V(H) Substrate V(L) B V(Gd) m08flash5.05 Cheng-Wen Wu, NTHU 18
  • 19. WEDF 0V 5V 0V 0V Addressed cell Be erased (aggressor) 0V (victim) 12V 0V Source (0V) 0V m08flash5.05 Cheng-Wen Wu, NTHU 19
  • 20. Bit-Line Program Disturb Fault (BPDF) Conditions: 1.Victim cell initial value is a logic ‘1’ 2.Aggressor “1→0” (program) Victim “1→0” (program) V(H) • During programming, erased cells on V(H) unselected rows on a bit-line that is being programmed may have a fairly deep depletion region formed under them • Electrons entering this depletion region can V(L) be accelerated by the electric field and injected over the oxide potential barrier to adjacent floating gates V(Gd) m08flash5.05 Cheng-Wen Wu, NTHU 20
  • 21. BPDF 0V 5V 0V 0V Addressed cell 0V (aggressor) 12V Be programmed (victim) 0V Source (0V) 0V m08flash5.05 Cheng-Wen Wu, NTHU 21
  • 22. Bit-Line Erase Disturb Fault (BEDF) Conditions: 1.Victim cell initial value is a logic ‘0’ G 2.Aggressor “1→0” (program) Victim “0→1” (erase) Control Gate S Floating Gate D V(L) V(H) Source Drain V(H) Substrate V(L) B V(Gd) m08flash5.05 Cheng-Wen Wu, NTHU 22
  • 23. BEDF 0V 5V 0V 0V 0V Addressed cell (aggressor) 12V Be erased (victim) 0V Source (0V) 0V m08flash5.05 Cheng-Wen Wu, NTHU 23
  • 24. Excitation Requirements Fault Initial Excitation Faulty Faulty Cell Model Content Operation Value Location WPD 1 Program (w0) 0 Word-line WED 0 Program (w0) 1 Word-line BPD 1 Program (w0) 0 Bit-line BED 0 Program (w0) 1 Bit-line m08flash5.05 Cheng-Wen Wu, NTHU 24
  • 25. Read Disturb Fault (RDF) Conditions: 1. Occurs on the selected cell G 2. Cell initial value is ‘1’ or ‘0’ •Soft program: After Control Gate repeated read operations, S Floating Gate D hot carriers can be injected from the channel into the Source Drain FG even if at low gate voltages Substrate •Soft erase: The selected cell is unable to maintain the state 0 after repeated B reads, due to charge leakage on the FG m08flash5.05 Cheng-Wen Wu, NTHU 25
  • 26. Over Erase Fault (OEF) • Flash memory erase mechanism is not self-limiting • Threshold voltage can be low enough to turn the cell into a depletion-mode transistor • Fault behavior: − An unselected cell in the same bit-line has excessive source-drain leakage current; reading that cell leads to incorrect value (like DEDF) − Cannot be programmed correctly (like TF) m08flash5.05 Cheng-Wen Wu, NTHU 26
  • 27. Basic RAM Faults for Flash Memory • Address-Decoder Fault (AF) • Stuck-At Fault (SAF) • Transition Fault (TF) • Stuck-Open Fault (SOF) • Bridging Fault (BF) Coupling faults need not be considered! Replaced by disturb faults m08flash5.05 Cheng-Wen Wu, NTHU 27
  • 28. Reliability Consideration • Reliability characteristics of floating-gate ICs depend on − Circuit density, circuit design, and process integrity − Memory array type and cell structure • Reliability stressing and testing must then be oriented toward determining the relevant failure rates for the particular array under consideration m08flash5.05 Cheng-Wen Wu, NTHU 28
  • 29. Data Retention Fault • Retention time: the time from data storage to the time at which a verifiable error is detected from any cause − Intrinsic retention times exceed millions of years in the operating temperature range ∗ Months at 300°C ∗ 1 million years at 150 °C ∗ 120 million years at 55 °C • Data Retention Fault (DRF) − Static leakage − Built-in data retention test circuit m08flash5.05 Cheng-Wen Wu, NTHU 29
  • 30. Cell Endurance Fault • Endurance: a measure of the ability to meet data- sheet specifications as a function of accumulated program/erase cycles − Endurance limit is a result of damage to the dielectric around the floating gate caused by electric stresses − In many flash devices, the end of endurance is generally caused by hot electron trapping in the charge transport oxide • Cell Endurance Fault (CEF) − Threshold window shift due to increased program/erase cycles − Built-in stress test circuit m08flash5.05 Cheng-Wen Wu, NTHU 30
  • 31. Composite Failure Rate Determination • 125°C dynamic life stress − The 125°C dynamic life stress is the standard MOS memory continuous dynamic read in a burn-in chamber • Endurance test − The endurance test is the repeated data complementing of floating-gate devices, possibly at temperature extremes • Extended data retention stress − This test is constituted by a high-temperature bake with a charge polarity that is opposite to the equilibrium state on the floating gate m08flash5.05 Cheng-Wen Wu, NTHU 31
  • 32. Testing WPDF 1 Flash 2 Program the first column 3 Read all cells except the first column 4 Flash 5 Program any column except the first 6 Read the first column *Assume reading and programming are done column-wise Source: Saluja, et al., Int. Conf. VLSI Design, 2000 m08flash5.05 Cheng-Wen Wu, NTHU 32
  • 33. Testing WEDF 1 Flash 2 Program all cells 3 Read all cells except the last column 4 Program any column except the last 5 Read the last column *Assume reading and programming are done column-wise Source: Saluja, et al., Int. Conf. VLSI Design, 2000 m08flash5.05 Cheng-Wen Wu, NTHU 33
  • 34. Test Coverage: Previous Results Fault DCP DCE DD EF GF SAF 50% 50% 50% 100% 100% TF 12.5% 50% 50% 87.5% 62.5% AF 40% 0% 0% 44.5% 40% SOF 0% 0% 0% 12.5% 6.2% CFst 25% 25% 25% 50% 50% WPDF 33.3% 0% 0% 100% 33.3% WEDF 0% 100% 75% 100% 100% BEDF 0% 75% 100% 100% 100% BPDF 0% 0% 0% 0% 0% Source: Saluja, et al., Int. Conf. VLSI Design, 2000 m08flash5.05 Cheng-Wen Wu, NTHU 34
  • 35. March-Based Flash Test: March-FT • {(f); ⇓(r1,w0,r0); ⇓(r0); (f); ⇑(r1,w0,r0); ⇑(r0)} This flash memory is of NOR type (stacked gate). Memory size (N) : 65536 Test length : 2(chip erase time) + 131072(word program time) + 393216(word read time) Test time : 7.207173 sec SAF : 100% (131072 / 131072) P.S. TF : 100% (131072 / 131072) Flash Type = NOR SOF : 100% (65536 / 65536) Gate Type = Stack AF : 100% (4294901760 / 4294901760) Row Number = 256 CFst : 100% (17179607040 / 17179607040) Col Number = 256 WPD : 100% (16711680 / 16711680) Word Length = 1 WED : 100% (16711680 / 16711680) Chip erase time = 3 sec BPD : 100% (16711680 / 16711680) Word program time = 9u sec BED : 100% (16711680 / 16711680) Word read time = 70n sec RD : 100% (65536 / 65536) OE : 100% (65536 / 65536) Ref: DELTA02 m08flash5.05 Cheng-Wen Wu, NTHU 35
  • 36. Test Length (Bit-Oriented) • Notation: DCP 2(F) + 2r(P) + rc(R) − F : Flash time DCE (F) + (c+1)r(P) + rc(R) − P : Program time DD (F) + (r+1)c(P) + rc(R) − R : Read time − r : row number EF 2(F) + (rc+2r+c-2)(P) + (2rc+r+c-3)(R) − c : column number GF 2(F) + (rc+2r+c-1)(P) + (2rc+c+r-2)(R) FT 2(F) + 2rc(P) + 6rc(R) m08flash5.05 Cheng-Wen Wu, NTHU 36
  • 37. Test Length (Word-Oriented) • Word length = w: − 2(F)+2rc(P)+6rc(R)+log(w)[2(F)+rc(P)+rc(R)] solid background standard background testing time testing time − Solid: 0000 (1111) − Standard: 0101 (1010), 0011 (1100) • Ex: word length w = 4 − 6(F) + 4rc(P) + 8rc(R) m08flash5.05 Cheng-Wen Wu, NTHU 37
  • 38. RAMSES-FT: Fault Simulator • Extended from RAMSES (for RAM) Test Memory FDs Alg Spec (Size) • Fault descriptors: − AGR: aggressor − SPT: suspect Simulation Engine − VTM: victim − RCV: recoverer • Fault coverage report Fault March and March Signature Coverage Signatures generation Ref: VTS02 m08flash5.05 Cheng-Wen Wu, NTHU 38
  • 39. Fault Simulation Example • Example: WPD − AGR: P, SPT: w, VTM: R1, RCV: P or E − March-like element: (R1, P) 0 1 2 3 Address 4 5 6 7 A0: R1 P A1: R1 A1: P A2: R1 Value 1 1 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Status A V V V A D V V V A V V V A D V m08flash5.05 Cheng-Wen Wu, NTHU 39
  • 40. Diagnostic Algorithm • March signature • March-FD: E ; ⇑ ( R1); ⇑ ( R1, P, R 0); E ; ⇑ ( R1); ⇓ ( R1, P, R0, R0); ⇑ ( R0, P); ⇑ ( R0); (00001000011101) TF(D), SAF(1) (00000000000100) WEDS, BEDS (00000000000001) WEDL, BEDL (00100000000000) WPDS, BPDS, AFS, CFst(0;1/0)S (00000001000000) WPDL, BPDL, AFL, CFst(0;1/0) L m08flash5.05 Cheng-Wen Wu, NTHU 40
  • 41. State Transition Diagram Pi, Pj Pj Pi Pi, Pj Aggressor: Cell i Victim: Cell j S00 S01 S00 Pi E E Pi E Pi Pi S10 E S11 S10 E S11 Pj Pj E Pj Pj E Fault free cells Faulty cells (AFs, CFst(0;1/0)s, WPDs, BPDs) m08flash5.05 Cheng-Wen Wu, NTHU 41
  • 42. Test Algorithm Generation by Simulation (TAGS) T(N) Test algorithms 2N (f); ⇓(r1) 3N (f); ⇓(w0); ⇓(r0) 4N (f); ⇓(r1,w0); ⇓(r0) 5N (f); ⇓(r1,w0,r0); ⇓(r0) 6N (f); ⇓(r1,w0,r0); ⇓(r0,w0) 7N (f); ⇓(r0); ⇓(r1,w0,r0); ⇓(r0,w0) 8N (f); ⇓(r1,w0); (f); ⇑(r1,w0,r0); ⇓(r0) 9N (f); ⇓(r1,w0); ⇓(r0); (f); ⇑(r1,w0,r0); ⇓(r0) 10N (f); ⇓(r1,w0,r0); ⇑(r0); (f); ⇑(r1,w0,r0); ⇓(r0) m08flash5.05 Cheng-Wen Wu, NTHU 42
  • 43. RAMSES-FT Results for TAGS 1 0.9 0.8 SAF TF 0.7 CFst SOF 0.6 AF 0.5 GPD GED 0.4 DPD 0.3 DED RD 0.2 OE 0.1 0 2N 3N 4N 5N 6N 7N 8N 9N 10N m08flash5.05 Cheng-Wen Wu, NTHU 43
  • 44. Diagonal Test Scheme (0,0) n (0,0) n m Diagonal 1 (D1 ) Diagonal 2 (D2 ) (a) m (0,0) n m (b) (c) Ref: ITC02 m08flash5.05 Cheng-Wen Wu, NTHU 44
  • 45. Diagonal Flash Test Step 1: Flash Erase Step 2 : ⇑ (R 1 ,P,R 0 ) Step 3: ⇑ (R1 ,P,R 0 ) Step 4 : ⇑ (R 0 ) Step 5: Flash Erase (0,0) ! D1 D1 ! D1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Step 6 : ⇓ (R 1 ,P,R 0 ) Step 7 : ⇑ (R 1 ) Step 8: ⇓ (R1 ,P,R 0 ) Step 9: ⇑ (R 0 ) D1 ! D1 D2 D1 ⎧( E ); ⇑ ( R1, P , R0); ⇑ ( R1, P , R0); ⇑ ( R0); ⎫ ⎪ ! D1 D1 ! D1 ⎪ Diagonal − FT : ⎨ ⎬ ⎪( E ); ⇓ ( R1, P , R0); ⇑ ( R1) ⇓ ( R1, P , R0); ⇑ ( R0)⎪ ⎩ D1 ! D1 D2 D1 ⎭ m08flash5.05 Cheng-Wen Wu, NTHU 45
  • 46. Flash Memory Fault Diagnosis • March-FD Algorithm: ⎧( E ); ⇑ ( R1); ⇑ ( R1, P , R0); ( E ); ⇑ ( R1);⎫ ⎪ ⎪ ⎨ ⎬ ⎪⇓ ( R1, P , R0, R0); ⇑ ( R0, P ); ⇑ ( R0) ⎪ ⎩ ⎭ Time complexity: 2e + (3N)p + (9N)r • Indistinguishable faults and their signatures for March-FD March Signatures Indistinguishable faults (00001000011101) TF(D),SAF(1) (00000000000100) WEDS, BEDS (00000000000001) WEDL, BEDL (00100000000000) WPDS, BPDS, AFS, CFst(0;1/0)S (00000001000000) WPDL, BPDL, AFL, CFst(0;1/0)L m08flash5.05 Cheng-Wen Wu, NTHU 46
  • 47. Diagonal Flash Diagnosis (Diagonal-FD) Step 1 : Flash Erase Step 2 : ⇑ ( P ; ⇑ (R 1 ); ⇑ (R 1 )) Step 3 : ⇓ ( P ; ⇑ (R 0 ); ⇑ (R 0 )) Step 4 : ⇑ (P ) D1 i ,! D 1 j ,! D 1 D2 i,D1 j,D1 !D1 (0,0) R1 1 1 1 1 P WPD R0 1 1 1 1 BED 1 1 1 1 R1 1 1 1 1 P R0 BPD WED Step 5 : ⇑ ( P ; ⇑ (R 0 ); ⇑ (R 0 )) Step 6 : Flash Erase Step 7 : ⇓ ( P ; ⇑ (R 1 ); ⇑ (R 1 )) D1 i ,! D 1 j ,! D 1 D2 i,D1 j,D1 P R0 WED 1 1 1 1 R1 1 1 1 1 BPD R0 1 1 1 1 1 1 1 1 P R1 BED WPD ⎧ ( E ); ⇑ ( P ; ⇑ ( R 1 ); ⇑ ( R 1 )); ⇓ ( P ; ⇑ ( R 1 ); ⇑ ( R 1 )); ⇑ ( P ); ⎫ ⎪ D1 i ,! D 1 j ,! D 1 D2 i,D1 j,D1 !D1 ⎪ ⎨ ⎬ ⎪ ⇑ ( P ; ⇑ ( R 0 ); ⇑ ( R 0 )); ( E ); ⇓ ( P ; ⇑ ( R 0 ); ⇑ ( R 0 )) ⎪ ⎩ D1 i ,! D 1 j ,! D 1 D2 i,D1 j,D1 ⎭ m08flash5.05 Cheng-Wen Wu, NTHU 47
  • 48. Fault Simulation: Test Time • Fault simulator: RAMSES-FT • DUT: industrial 2Mb (256K×8) flash memory core. *Mass Erase Time: 200ms; Byte Program Time: 12µs; Byte Read Time: 10ns. Algorithm Complexity (N = m x n) Test Time Erase Program Read EF 2 1N + 2 N 2N + N 3.569 sec. Flash March 2 2N 4N 6.702 sec. March-FT 2 2N 6N 6.707 sec. Diagonal-FT 2 1N + 2 N 4N + 3 N 3.569 sec. March-FD 2 3N 9N 9.861 sec. Diagonal-FD 2 1N + 3 N 4N 3.575 sec. m08flash5.05 Cheng-Wen Wu, NTHU 48
  • 49. Fault Simulation: Fault Coverage WPD WED BPD BED OE RD Total 100% 100% 0% 100% 100% 100% EF SAF TF SOF AF CFst 72.23% 100% 87.5% 12.5% 44.5% 50% WPD WED BPD BED OE RD Total 100% 100% 100% 100% 100% 100% Flash March SAF TF SOF AF CFst 93.18% 100% 100% 50% 100% 75% WPD WED BPD BED OE RD Total 100% 100% 100% 100% 100% 100% March-FT SAF TF SOF AF CFst 100% 100% 100% 100% 100% 100% WPD WED BPD BED OE RD Total 100% 100% 100% 100% 100% 100% Diagonal-FT SAF TF SOF AF CFst 97.34% 100% 100% 100% 81.6% 89.15% m08flash5.05 Cheng-Wen Wu, NTHU 49
  • 50. Extended Diagonal Flash Test Step 1: Flash Erase Step 2 : ⇑ (R 1 ,P,R 0 ) Step 3: ⇑ (R1 ,P,R 0 ) Step 4 : ⇑ (R 0 ) Step 5: Flash Erase (0,0) ! D1 D1 ! D1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Step 6 : ⇓ (R 1 ,P,R 0 ) Step 7 7 : ⇓⇑(R 1, P , R 0 ) 8: ⇓ (R1 ,P,R 0 ) Step : (R 1 ) Step Step 9: ⇑ (R 0 ) D1 ! DD 1 !1 D2 D1 • Fault coverage can achieve 100%. • Test length: 2e + (2N)p + (5N)r. • Test time for the 2Mb flash memory core: 6.705 sec. m08flash5.05 Cheng-Wen Wu, NTHU 50
  • 51. Test Time and Area Comparison (CMOS 1P4M 0.35um) Fault Complexity (N=mxn) Testing Time BISD Area Algorithm Coverage (@100MHz) (gate count) Erase Program Read March-FT 100% 2 2N 6N 8.000 sec. 2,502 Diagonal-FT 97.34% 2 1N + 2 N 4N + 3 N 4,585 sec. 2,551 Comparison -2.66% 0 − (1N− 2 N ) −(2N−3 N) -42.69% +49 March-FD 2 3N 9N 11.450 sec. 100% Diagonal-FD 2 1N + 3 N 4N 4.591 sec. Total 100% 4 4N + 3 N 13N 16.041 sec. m08flash5.05 Cheng-Wen Wu, NTHU 51
  • 52. Built-In Self-Test Design Address From Flash Controller Data Control Signals CMD Address BSI EOP Address BSO Data To Flash CTR ERR TPG Data MUX Memory CONT Control Control BMS ENA Signals Signals BRS DONE BCE CLK (Test Collar) BNS BSI: BIST serial input BSO: BIST serial output BMS: BIST mode select BRS: BIST reset BNS: BIST/Normal select BCE: BIST commend end CLK: System clock Ref: DELTA02 m08flash5.05 Cheng-Wen Wu, NTHU 52
  • 53. Case I • A typical 4Mb (512K x 8) embedded flash memory core with BIST circuitry Address Data HV Generator Address Buffer Address X - Decoder CE Control Control Flash OE signals Logic Control Cell Array Test Collar WE signals Address Y - Decoder & BSI Y - MUX BSO Data Test mode Test Mode BMS BIST signals BRS Control Registers I/O Buffer & BCE signals Sense Amp. CLK Data BNS m08flash5.05 Cheng-Wen Wu, NTHU 53
  • 54. Case II • A commodity 1Mb (128K x 8) flash memory chip with BIST circuitry CE Control OE Address PGM/ER HV Input WE Logic Reset Data X-Decoder Command Flash Address Data Latch Control Array Command Signals Test Collar Din/Dout Decoder & State Reg. Y-Decoder Address Y-Pass BSI Gate BSO Data BMS BIST BRS Sense PGM BCE Control DATA Signals Amp. HV CLK BNS I/O Buffer m08flash5.05 Cheng-Wen Wu, NTHU 54
  • 55. Experimental Results Embedded Flash Commodity Flash Core Chip Memory Size 512K bytes 128K bytes Mass Erase Time 200ms 190ms Byte Program Time 20us 8us Erase Penalty 2.5ms 1us Program Penalty 21us 1us Scrambling Type Data Address Built-In Test March FT March FT Algorithm (Only solid (With standard background) background) Hardware Overhead 3.2% 2.28% Testing Time 44.612 sec 13sec m08flash5.05 Cheng-Wen Wu, NTHU 55
  • 56. Typical Test Modes (Characterization) • Stress (row/column) − Reverse tunneling stress − Punch through stress − Tox stress − DC stress • Mass program • Weak erase • Leak (thin-oxide, bit-line, etc.) • Cell current; cell Vt • Margin • Etc. m08flash5.05 Cheng-Wen Wu, NTHU 56
  • 57. Test Items in WP1 WP1 Start Open/Short test Input/Output leakage test Standby/Active current test Read ID test DC stress test Chip erase/verify Margin read 1 verify Sector Protect/Unprotect verify Functional Mass Program/verify Test Margin read 0 verify Items Thin-oxide stress Row/Column stress Sector erase/verify (whole-chip) CKBP program/verify !CKBP program/verify Chip erase/verify WP1 Done m08flash5.05 Cheng-Wen Wu, NTHU 57
  • 58. Functional Test Items • MSCAN-like − {(f ); (r1); (p0); (r0); (pCB); (rCB); (p!CB); (r!CB); } − Covers SAF, TF, WPD, BPD, & OE Notation Operations Notation Address Sequence f Erase ⇑ Ascending p Program ⇓ Descending r Read Either Notation Background Notation Applied Patterns 0 All-zero CB Checkerboard 1 All-one !CB Inverse Checkerboard m08flash5.05 Cheng-Wen Wu, NTHU 58
  • 59. Test Time Improvement • Using the March-FT* to improve test coverage and test time − {(f );(r1, p0, r0); (r0) (f ); (r1, p0, r0); (r0);} − Covered SAF, SOF, TF, AF, CFst, WPD, WED, BPD, BED, RD, OE • Test time reduction in WP1: 2Te + 2Tp + 6Tr Te: erase time (ms) 1- Tp: program time (us) 3Te + 3Tp + 6Tr Tr: read time (ns) • Overall test time reduction: 8Te + 8Tp + 24Tr 1- 11Te + 11Tp + 22Tr ∗ Ref: “Flash Memory Built-In Self-Test Using March-like Algorithms”, DELTA 2002 m08flash5.05 Cheng-Wen Wu, NTHU 59
  • 60. Built-In Self-Test and Self-Diagnosis • Use BIST to reduce the number of test pins • Use BISD to support diagnosis • Support high-voltage (High-V) mode for commodity flash devices − Simplify mode control • Support cycling test and burn-in test − Reduce the complexity of cycling board and burn-in board m08flash5.05 Cheng-Wen Wu, NTHU 60
  • 61. Area Overhead of BIST and BISD • Implemented BIST and BISD on a 2Mb flash memory---7.6mm2 (0.25um process) BISD BISD with BIST BISD with High-V and High-V Cycling Area (mm2) 0.0293 0.0432 0.0511 0.0570 Gate Count 1695 2512 2957 3298 Overhead 0.39% 0.57% 0.67% 0.75% m08flash5.05 Cheng-Wen Wu, NTHU 61
  • 62. BiNOR-Type Flash Memory • Bi-directional tunneling program/erase NOR- type flash memory • Low power consumption and excellent reliability Program Erase NOR VT is raised VT is decreased BiNOR VT is decreased VT is raised Source: IEEE Trans. Electron Devices, 2001 m08flash5.05 Cheng-Wen Wu, NTHU 62
  • 63. Flash Memory Diagnosis Methodology Fault Models SAF, TF, SOF, CFst, AF, Fault Map WPD, WED, BPD, BED, OP Fault Fault Dictionary Simulator (SA1) Diagnosis Error Catch Algorithm March-FT and Analysis* Parser (WPD) (to get BISD Tester Log signatures) Error Bit Map (BPD) Source: ICCAD00 m08flash5.05 Cheng-Wen Wu, NTHU 63
  • 64. Part of the March-FT Fault Dictionary • March-FT: { (f); ⇑(r1,p0,r0); (r0); (f); ⇓(r1,p0,r0); (r0); } <0 0 0 1 1 0 0 0 1 1> Signatures Fault Sets Groups <0100001000> SAF(0), OPM, SOFM, SOFT A <0001100011> SAF(1), TF(D) B <0000001000> TF(U), CFst(0;1/0)L, OPH, C CFst(1;1/0)S, AFL, WPDL, BPDL m08flash5.05 Cheng-Wen Wu, NTHU 64
  • 65. BISD with Enhanced Test Mode Control • Built-in March-FT algorithm • Programmable diagnosis algorithms • Flexible output format for test and/or diagnosis • Supports dynamic burn-in (BI) test • Engineering test mode can be accessed by BISD − Overall test time is reduced • Provides various types of access commands, e.g., Reset Wait m08flash5.05 Cheng-Wen Wu, NTHU 65
  • 66. High Voltage (HI-V) Tests • HI-V tests usually employed to reduce the test time in the engineering test mode • TExecution(HI-V Erase) < TExecution(Erase) {A9, RSTB, OEB} HI-V Detector Normal flags Signal Test Collar Memory {A[17:10], A[8:0]} Controller DQ {WEB, CEB} Memory BISD Array m08flash5.05 Cheng-Wen Wu, NTHU 66
  • 67. BISD Architecture 2 RBB BSI MUX CMD Reg. WPB 5 FSM FOPC Look- of Up Table CLK I/O Selector 8 BRS CMD 5 TPG I/O1 BMS FSM Decision ADDR March BNS of Generator 8 BIM Op. CTR I/O2 BAC Counter DB Generator BFI & Comparator CEB 7 E-info. Selector 43 E-info. Control Signal 5 WEB BSO REB E-info. Register Collector Generator CLE ALE BISD Controller Test Pattern Generator (CTR) (TPG) m08flash5.05 Cheng-Wen Wu, NTHU 67
  • 68. A Configurable Flash Tester • PC-based low-cost MECA Parallel Port test and diagnosis or USB2.0 Desktop PC solution, called CONFLUENCE GPIB GPIB • Memory Error Catch Function Logic and Analysis (MECA*) Generator Analyzer • GPIB: General- RAM BISD Purpose Interface Bus Flash Under ∗ Ref: “Error catch and analysis for Diagnosis semiconductor memories using March tests”, FPGA ICCAD 2000 Board m08flash5.05 Cheng-Wen Wu, NTHU 68
  • 69. Parallel Test Methods Original Program/Erase Unit Page buffer & SA Page buffer &SA Y-Decoder Block 0 Block 1024 Block 1 Block 1025 Block 2 Block 1026 Plane 0 Plane 1 Flash Memory Block 1023 Block 2047 Controller Page buffer & SA Page buffer &SA Charge pump and other analog circuitry X-Decoder m08flash5.05 Proposed Cheng-Wen Wu, NTHU Unit Program/Erase 69
  • 70. Experimental Results Case I Case II Flash memory area 7.6mm2 60mm2 Flash memory capacity 2Mb 256Mb BISD area 0.05mm2 0.3mm2 Area overhead 0.67% 0.5% BISD frequency 10MHz 40MHz • BISD circuit implemented on FPGA • BISD test results compared with those of ATE m08flash5.05 Cheng-Wen Wu, NTHU 70
  • 71. Diagnosis Result for 2Mb Flash Chip1 Chip2 Chip3 Chip4 Chip5 Chip6 Chip7 Chip8 MSCAN Pass Fail Pass Fail Partial Fail Pass Pass March-FT Fail Fail Fail Fail Fail Fail Fail Pass Unmodeled Faults 0 10 0 --- 0 --- 0 0 A: 1 B: 19 A: 4 A: 6 A: 5 C: 4 C:182 C: 1 C:113 C:876 D: 1 C:940 D: 81 E: 2 D: 16 D:550 Fault D:496 F: 1 Groups G: 1 J:105 J: 30 K: 54 m08flash5.05 Cheng-Wen Wu, NTHU 71
  • 72. The Error Bitmap for Chip 5 m08flash5.05 Cheng-Wen Wu, NTHU 72
  • 73. The Fault Bitmap for Chip 5 m08flash5.05 Cheng-Wen Wu, NTHU 73
  • 74. Results for 256Mb Flash Memory • Three chips are tested in this case • ATE test result: one passed and two failed • FPGA (BISD prototype) test results: two passed and one failed − The difference between ATE and FPGA is clock rate − Real BISD can perform at-speed test • Diagnosis result for the failed chip: one block cannot be erased (SA0) − Same for ATE & FPGA m08flash5.05 Cheng-Wen Wu, NTHU 74
  • 75. Conclusions • Flash memory fault models and test algorithms are proposed − Both march-based and diagonal tests are effective • A flash memory simulator has been developed to facilitate the analysis and generation of the test algorithms • Flash memory BIST/BISD is feasible • Future work: − To support more flash memory types and other realistic fault models − Diagnosis methodology for flash memories − BISR m08flash5.05 Cheng-Wen Wu, NTHU 75

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