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Transcript

  • 1. Flash Memory Presented By: Rob Douglas, Alex Alexandrov
  • 2. Points of Discussion
    • Flash Memory Generalities
      • Construction & Properties
    • History of Flash Memory
    • NOR & NAND Architectures
    • Optimizations
    • Standardization
    • New Developments & Future of Flash
    • Closing Statements
  • 3. Flash Memory
    • A type of EEPROM (Electrically-Erasable Programmable Read-Only Memory)
    • Non-volatile, solid state technology
    • Relatively limited lifespan
    • Information is stored in an array of memory cells made from floating-gate (FG) transistors
  • 4. Flash Memory
    • Packaged inside a memory card:
      • Extremely durable
      • Can withstand intense pressure
      • Immersion in water
    • Better kinetic shock resistance than hard disks
    • Average power requirements range from 5V-12V
  • 5. Flash Memory Cell
  • 6. History of Flash Memory
    • Invented by Fujio Masuoka while he was working for Toshiba in the early 1980s
    • First introduced at the 1984 International Electron Devices Meeting in San Francisco
  • 7. Manufacturers of Flash
  • 8. NOR Flash Memory
    • Developed to replace read only memory
    • Full address and data buses allow random access to any memory location
      • Can access any memory cell
      • Slow sequential access
  • 9. NAND Flash Memory
    • Developed to replace hard disks
    • Sequential-accessed command and data registers replace the external bus of NOR
      • Decreases chip real estate
      • Can only access pages
      • Faster sequential access
  • 10. Optimizations
    • Wear levelling
      • Counting writes & dynamically remapping blocks
    • Bad block management
      • Write verification and remapping bad sectors
    • Multi-Level Cell technology
      • Memory cells store more than one bit
  • 11. Standardization
    • Part of the reason for the success of Flash memory
    • Open NAND Flash Interface Working Group developed standard low-level interface
      • Standard pinout
      • Standard command set for reading, writing, and erasing NAND flash chips
      • Mechanism for self-identification
  • 12. New Developments
    • AND Flash
      • Bit line replaced with embedded diffusion line to reduce cell size
      • Low power dissipation (3V)
    • DINOR (DIvided bit-line NOR) Flash
      • Attempts to reduce the chip real estate compared to conventional NOR
      • Low power dissipation (3V), sector erase, high data transfer rate
  • 13. Future of Flash Memory
    • Continues to be among the most aggressively scaled electronic technologies
    • Memory cell size minimum of 20 nm expected to be met in 2010
    • May be replaced by Phase-Change RAM or other emerging technologies
  • 14. In Closing…
    • One of the most popular alternatives for portable device storage
    • Aggressive advances are still being made
  • 15. References Wikipedia - Flash Memory How Stuff Works - Flash Memory http:// smithsonianchips.si.edu
  • 16. Questions?