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  • 1. featured product: Altera MAX IIZ CPLD January 2008 www.portabledesign.com Dealing with the Limitations of FLASh MeMory wireless communications: Mobile WiMAX consumer electronics: Mixed-Signal SoC Verification portable power: CEO Interview: Programmable Clocks / Ray Zinn Lower Supply Voltages Micrel An RTC Group Publication
  • 2. Worldwide Semiconductor Revenue Forecast (Revenue in Millions of U.S. Dollars) contents 380,000 361,379 360,000 Millions of U.S. Dollars 340,000 334,061 320,000 303,492 300,000 291,360 departments 280,000 270,930 dave’s two cents 5260,000 260,222 editorial letter 6 240,000 industry news 8 analysts’ pages 12 220,000 12 analysts’ pages product feature 40 200,000 design idea 42 2006 2007 2008 2009 2010 2011 products for designers 44 cover feature Dealing with the Limitations of 16 Flash Memory Xerxes Wania and Steven Cliadakis, Sidense 16 flash memory wireless communications Mobile WiMax: How to Make Mobile 20 WiMax Consumer Devices a Reality Frank Ferro, Sonics, Inc. CPU DSP CPU (MAC) (PHY) (MAC2) consumer electronics Applying an Integrated Approach to 24 BUS Digital Design Mixed-Signal SoC Verification RTL Karen Chow, Mentor Graphics Corp. Analog Design Chip-Level RTL Simulation Schematic Capture Memory 20 mobile WiMax I/O CTL Top-Level Testbench portable power Synthesis Extend Battery Life Using 0 Simulation Mixed-Signal Simulation Static Timing Analysis Programmable Clock Technology Custom Layout Chip-Level Assembly Place and Route Greg Richmond, SpectraLinear, Inc. DRC/LVS DRC/LVS Extraction Lower Supply Voltages Enable Low-Power 4 Portable Electronic Devices Extraction Extraction Static Timing Analysis Aditya Rao, Microchip Technology, Inc. Post-Layout Simulation Post-Layout Simulation ceo interviewNo Design Meets Yes Yes Design Meets No Yes Design Meets No Ray Zinn 48 Specs? Specs? Specs? Tapeout! 24 mixed-signal design Micrel JANUARY 2008 
  • 3. team editorial team Editorial Director Warren Andrews, warrena@rtcgroup.com Editor-in-Chief John Donovan, johnd@rtcgroup.com Managing Editor Marina Tringali, marinat@rtcgroup.com Copy Editor Rochelle Cohn art and media team Creative Director Jason Van Dorn, jasonv@rtcgroup.com Art Director Kirsten T. Wyatt, kirstenw@rtcgroup.com Graphic Designer Christopher Saucier, chriss@rtcgroup.com Director of Web Development Marke Hallowell, markeh@rtcgroup.com Web Developer Brian Hubbell, brianh@rtcgroup.com management team Associate Publisher Marina Tringali, marinat@rtcgroup.com Product Marketing Aaron Foellmi, aaronf@rtcgroup.com Manager (acting) Western Advertising Manager Stacy Gandre, stacyg@rtcgroup.com Untitled-2 1 9/21/07 10:52:58 AM Western Advertising Manager Lauren Trudeau, laurent@rtcgroup.com Eastern Advertising Manager Nancy Vanderslice, nancyv@rtcgroup.com Circulation Shannon McNichols, shannonm@rtcgroup.com executive management Chief Executive Officer John Reardon, johnr@rtcgroup.com HOW WELL Vice President Vice President of Finance Cindy Hickson, cindyh@rtcgroup.com Cindy Muir, cindym@rtcgroup.com DO YOU KNOW Director of Corporate Marketing Director of Art and Media Aaron Foellmi, aaronf@rtcgroup.com Jason Van Dorn, jasonv@rtcgroup.com THE INDUSTRY? portable design advisory council Ravi Ambatipudi, National Semiconductor Doug Grant, Analog Devices, Inc. Dave Heacock, Texas Instruments Kazuyoshi Yamada, NEC America corporate office The RTC Group 905 Calle Amanecer, Suite 250 WWW.EMBEDDEDCOMMUNITY.COM San Clemente, CA 92673 Phone 949.226.2000 Fax 949.226.2050 www.rtcgroup.com For reprints contact: Marina Tringali, marinat@rtcgroup.com. Published by the RTC Group. Copyright 2007, the RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of the RTC Group. All other brand and product names are the property of their holders. Periodicals postage at San Clemente, CA 92673. Postmaster: send changes of address to: Portable Design, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673. Portable Design(ISSN 1086-1300) is published monthly by RTC Group 905 Calle Amanecer, Suite 250, San Clemente, CA 92673. Telephone 949-226-2000; 949- 226-2050; Web Address www.rtcgroup.com. Ride along enclosed. embeddedcommad_14v.indd 1 4 PORTABLE DESIGN 11/13/06 5:55:59 PM
  • 4. H dave’s two cents Happy New Year! I cannot believe 2008 is al- money to other valued functions, or we can use ready upon us. Early each year I draft a list of more memory. For example, “Kindle,” a wire- New Year’s resolutions. It is important to do less E-Book reader recently introduced by Ama- them early so I can forget them early. This year zon, reportedly sold out in less than six hours. It I resolve to be more organized, learn more Chi- has only 256 Mbytes of memory. This is small nese and, of course, live healthier. With any luck in today’s portable memory standards. With I will have eliminated all but one by February. memory inventory growing, maybe this device’s Another annual event of mine is to predict what memory could be bigger? However, this shows may happen during the incoming year. There are that even in a soft market and with gloomy pre- easy predictions. For instance, portable devices dictions that novel products can sell. will have more features at lower prices. And there are tougher predictions—like the total time I sit on the ground in an airplane. dave’s two cents on... Mixed predictions already exist about the My Forecasts for electronics industry for 2008. Last October, EE Times reported that “Japan’s IC execs see 2008 upturn.” [1] They went on to report that NEC and Toshiba projected growth of 10 percent or more 2008 for 2008. However, not everyone agrees with the rosy outlook. In December, EE Times reported, “Gartner pulls down chip forecast.” [2] It’s not that there won’t be growth; it’s just that the ex- pectations for growth are less—down from 8.2 to 6.2 percent. In another article published by Forbes, [3] a 50 percent probability of a recession For another example, an Olympic viewer is predicted for 2008. could record his favorite sport while off do- Generally, economic predictions are like ing other things. This may be an extension of weather forecasts. For example, a 30 percent the SlingPlayer™ Mobile. The sport could be chance of rain means that rain is likely to fall on viewed later on the portable device, or upon ar- 30 percent of the region covered by the forecast. rival at the hotel for a bigger screen. There are While some analysts say they have not forecast- plenty of good ideas to drive our industry. We ed a recession for the U.S., they have increased should not let the “gloomers” distract us. the probability from 10 to 35 percent, [2] or up I am not sure which is more complex—the to as much as 50 percent. How should these economy or the weather. But what I do know is numbers be interpreted? If they are like weather that reporting is more accurate than predicting predictions, then that percentage of the economy for either one. All in all, 2008 presents another could feel like it is in a recession. Or it could just year for opportunities. We can both get busy and be the probability of a recession, meaning that have a great year, or we can take a nap. Either under the predicted circumstances, that percent- one will make time go by. For my two cents, I age of the time we could enter a recession. If the predict a good year for 2008 with continued in- U.S. does enter a recession, the analysts predict novations and opportunities for all. I also predict that growth for the electronics industry will be that my resolutions have a 30 percent probability further reduced. of lasting more than three months, unless I win Unlike weather forecasting, economic predic- the lottery by finding the winning ticket. tions can influence the probability that the pre- dictions become reality. With weather, predicting Dave Freeman, Texas Instruments rain may make people carry an umbrella—but carrying an umbrella does not make it rain. EE Times: Semiconductor News, “Japan’s IC [1] However, predicting an economic downturn can exces see 2008 upturn,” Mark LaPedus http://www.eetimes.com/showArticle.jhtml?arti cause our industry to enter a hibernation mode, cleID=202200193. which in turn really can cause a downturn. Sub- sequently, those forecasting the downturn will EE Times: Semiconductor News, “Gartner [2] have been correct. pulls down chip forecasts,” Rick Merritt http://www.eetimes.eu/semi/204701202. I prefer information rather than forecasts and opinions. For example, inventories of DRAM Forbes: AFX News Limited, “Leading econo- [3] and flash devices are building. The average unit mists tell Congress recession dangers rising,” Thomson Financial News Limited 2007, URL: price (AUP) of these devices is falling at some http://www.forbes.com/afxnewslimited/feeds/ rate. This is usable information. We can use ei- afx/2007/12/05/afx4409040.html ther the same amount of memory and move the JANUARY 2008 5
  • 5. N editorial letter Navigating CES is all about logistics and com- undercut the main argument for MIDs. Besides, fortable shoes. Thanks to days of planning, the first-generation MID is already here. It’s countless Frappuccinos and a new pair of Rock- called the iPhone. ports, I managed to surf the hype, skim at least Not to belabor the point, but in an inadvertently the highlights and discover a few hidden gems. related keynote, Jerry Yang of Yahoo showed off Still, with 2700 companies displaying their the new Yahoo! Go 3.0, which offers “a better wares for the benefit of almost 150,000 attend- Internet experience,” as the marketers say, on ees, even hitting the highlights is an endurance the current crop of cell phones. It’s a handsome contest. GUI that Yahoo is opening to third-party devel- CES is all about generating buzz—or, worst opers, perhaps as a counter to Google’s Android case, trying to convince people that you have efforts. Whatever, it’s a lot easier to use than the it. Nobody cranked up the buzz machine louder frustrating menu structure that afflicts most cell than Intel, starting with Paul Otellini’s opening phone browsers. day keynote. Otellini’s entertaining presentation One standing-room-only SuperSesssion was focused on how the Internet has changed the titled, “The Top Ten Technologies You’ve Never world—and how much more it will change it Heard Of.” They’re all wireless technologies once everything goes wireless. Otellini contin- that our readers have heard of (NFC, WiMAX, ued to beat up on cell phones as a highly inferior etc.), but not the mainstream press, apparently. way to access the Internet, which they surely are. The panel concluded that in the near future al- His solution, most recently promoted at IDF, is most all products will be completely wireless, Mobile Internet Devices (MIDs), all of which he including power cords. In case anyone missed it, expects to be powered by Intel’s pending Menlo the “next killer app” is already here: it’s wireless chips. According to Otellini, the impact of MIDs connectivity. will be nothing less than the advent of television. The ZigBee Alliance proudly displayed a Come on, Paul, get a grip. range of wireless thermostats, power meters and other devices that can dynamically adjust home Leaving Las Vegas power consumption, under the control of either the power company or the homeowner. A num- ber of power companies and a few states—Cali- fornia and Texas among them—are mandating john donovan, editor-in-chief the use of ZigBee-powered control devices in new building starts. The demand for such “green technology” could finally see ZigBee take off in Still, with Intel planning on pumping billions a big way. of dollars into promoting MIDs, only a fool Analog Devices demonstrated mobile TV car- would bet against them, especially when they’re ried over Mobile Terrestrial DMB on a variety of addressing an admitted problem whose solution devices. These are clearly aimed at the European could open up a huge market—not coincidental- market, where that standard is prevalent, and not ly, an embedded market in which Intel has been the U.S., which is still assessing the MediaFlo a marginal player to date. Plenty of traditional vs. DVB-H fallout. They also had a fun demo handset makers are already jumping on the of their audio chips, enabling a pickup-equipped would-be bandwagon. Lenovo, AsusTek, Toshi- acoustic guitar to sound like it was unplugged. ba and Samsung all showed off MID prototypes Qualcomm showed off its mirasol displays, that could browse the Web, send emails, play based on a reflective MEMS technology. Com- music, take pictures and work on office docu- bining high resolution with extremely low power ments—and possibly even make a phone call. consumption, the devices rely on optically reso- Consumer acceptance of MIDs is anything nant cavities instead of LCD pixels; they require but a given. Why would I want to spend $500+ no backlighting and can work equally well in- to carry around yet another gadget that does doors or in direct sunlight. Qualcomm is right in very little beyond what my cell phone already considering this a “disruptive technology,” but does? The lack of infrastructure is another ma- we’d like to see full-color displays in production Portable Design blog jor problem. Cell phone service isn’t up to full before drawing final conclusions. For more detailed coverage of the video streaming; Wi-Fi access is too spotty; and All told, CES was a harrowing, fun experi- Portable Design industry, including WiMAX networks are a long way off. Everyone ence, like skiing moguls or riding a roller coaster. videos and podcasts, check out my would welcome better mobile Internet access, If there was any lingering question that portable new blog at: but MIDs aren’t the obvious answer. By the time consumer devices are driving the electronics in- www.portabledesign.blogspot.com. the infrastructure problems are solved, cell phone dustry, CES put it to rest. makers will no doubt be able to show much im- proved Internet-surfing capabilities, which will 6 PORTABLE DESIGN
  • 6. MicroTouch is Going Mobile Expanding the Possibilities 3M Touch Systems MicroTouch Flex Capacitive TM Touch Sensors for Mobile Applications • Nearly Invisible ITO Proprietary index matching technology to minimize ITO visibility • Ultrathin Substrate 0.05 mm PET substrate enables compact design • Creative Form Factors Allows designers the freedom to explore a myriad of shapes • High Volume Production Roll process is capable of producing millions of units per month Learn more about MicroTouch Going Mobile by calling 888-659-1080 or visit www.FlexCapTouch.com for details. 3M © 2007 MicroTouch is a trademark of the 3M Company.
  • 7. news ON Semiconductor to Acquire 74 percent and 26 percent, respectively, of the AMIS Holdings, Inc. combined company. ON Semiconductor Corporation and AMIS ON Semiconductor president and CEO Holdings, Inc., parent company of AMI Semi- Keith Jackson will serve as president and CEO conductor, have announced the signing of a of the combined company. Corporate head- definitive merger agreement providing for the quarters will remain in Phoenix, Arizona, with acquisition of AMIS by ON Semiconductor in a significant presence maintained in Pocatello, an all-stock transaction with an equity value of Idaho, Belgium and various other locations approximately $915 million. worldwide. ON Semiconductor non-executive “The acquisition of AMIS furthers the Chairman J. Daniel McCranie will continue as transformation of ON Semiconductor into an non-executive chairman of the Board of Direc- analog and power solutions leader with en- tors of the combined company, which will be hanced scale, higher value and higher margin expanded to eight members with the addition products, deep customer relationships and an of Christine King, CEO of AMIS. expanded addressable market,” said Keith Jackson, ON Semiconductor president and ON Semiconductor, Phoenix, AZ. CEO. “Combining ON Semiconductor’s lead- (602) 244 6600. [www.onsemi.com]. ing standard products and advanced manu- AMI Semiconductor, Pocatello, ID. (208) 233-4690. [www.amis.com]. TSMC Unveils New 65 Nanometer Mixed-Signal and RF Tool nd Qualification Program er exploration Taiwan Semiconductor Manufacturing Com- ether your goal pany, Ltd. (TSMC) has unveiled a comprehen- speak directly ical page, the sive Electromagnetic (EM) Tool Qualification ght resource. Program that drives its Design Service Ecosys- technology, tem partners to ensure greater accuracy of EM es and products simulators and extractors used in applications ed such as high-speed digital clock circuits and high-frequency mixed-signal RF designs. Targeting TSMC’s 90 and 65 nanometer facturing infrastructure with AMIS’s growing (nm) process technologies, the program im- standard products business and substantial proves device model accuracy, supports a wid- companies providing solutions now custom product portfolio will enable the com- er selection of qualified EM tools, significantly exploration into products, technologies and companies. Whether your goal is to research the latest datasheetto more comprehensively ad- bined company from a company, reduces customer EM tool evaluation efforts, dress our customers’ needs.” mp to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of lowers the risk and eases adoption of TSMC Under the terms of the agreement, which gy, Get Connected will help you connect with the companies and products you are searching for. advanced process technologies. onnected has been approved by both boards of direc- Typically, high-frequency circuit designers tors, AMIS shareholders will receive 1.150 select a set of devices, such as inductors, to be shares of ON Semiconductor common stock included in their design, and evaluate differ- for each share of AMIS common stock they ent EM simulators from different tool vendors, own. Based on the closing stock price of ON trying to match EM simulator data to silicon Semiconductor on December 12, 2007, this measurements provided by foundry. Most of represents a value to AMIS shareholders of the time the results are different due to the vari- End of Article approximately $10.14 per share. Upon com- ability of the process data and the wide variety pletion of the transaction, ON Semiconductor of different test devices. Through the EM Tool will issue approximately 104 million shares of Qualification Program, TSMC provides EM Get Connected common stock on a fully diluted basis to com- tool vendors a standardized set of devices and with companies mentioned in this article. plete the transaction. ON Semiconductor and silicon measurements, and a unified technology www.portabledesign.com/getconnected AMIS stockholders will own approximately file for extraction and modeling, thus eliminat-  PORTABLE DESIGN Get Connected with companies mentioned in this article.
  • 8. standard transaction-level modeling interfaces. lem P. Roelandts, 63, who remains chairman It also enables intra- and inter-company reuse of the board. Gavrielov becomes only the third through a common methodology and classes Xilinx CEO in its 24-year history, and brings for virtual sequences and block-to-system re- nearly 30 years of executive management and use, and full integration with other languages engineering experience with semiconductor commonly used in production flows. As a joint and software companies to Xilinx. Gavrielov’s development initiative between Mentor Graph- appointment is effective immediately. ics and Cadence Design Systems, the OVM is Most recently, Gavrielov served as executive supported on multiple verification platforms vice president and general manager of the fast- ideally suited to both novice and expert verifi- growing verification division at Cadence De- ing the data inconsistency, reducing tool evalu- cation engineers. ation time and improving design accuracy. This The OVM includes the foundation-level is especially significant in nanometer RF de- utilities necessary for building advanced ob- signs where obtaining accurate device models ject-oriented, coverage-driven verification en- at high frequency has created the bottleneck for vironments and reusable verification IP (VIP) first pass design success. in SystemVerilog. The OVM reduces the com- As part of the EM Tool Qualification Pro- plexity of adopting SystemVerilog by embed- gram, TSMC developed, and silicon-verified, a set of commonly used spiral inductors and pro- sign Systems, Inc. Before that, Gavrielov spent vides the devices and the process data to EM seven years as CEO of Verisity Ltd., where he tool vendors to verify the tool accuracy and grew the company from a $4M start-up, tak- ability to match silicon data. Once qualified, a ing it through its initial public offering (IPO) tool qualification report is generated and posted in 2001 to a $70M publicly traded company, on TSMC-Online, TSMC’s customer portal for and ultimately to its acquisition by electronic designers to download and review. Multiple design automation leader Cadence in 2005. EDA partners participate and are being quali- ding verification practices into its methodology Prior to joining Verisity, then Cadence, Gavr- fied in the program including Agilent, Ansoft, and library, and significantly shortens the time ielov spent nearly ten years at LSI Logic Corp., Cadence, Helic, Integrand, Lorentz, OEA, Sil- to create verification environments. It easily where he served in a variety of executive man- vaco and Zeland. integrates plug-and-play VIP and ensures code agement positions, including executive vice portability and reuse. president for the $1.3B products group, senior TSMC North America, San Jose, CA. A production version of OVM is avail- vice president of international markets, gen- (408) 382-8000. [www.tsmc.com]. able immediately with additional functional- eral manager for Europe, and general manager ity planned for release later in 2008. Cadence of the application-specific integrated circuit Interoperable SystemVerilog and Mentor have collaborated to ensure that (ASIC) division. Gavrielov began his career Methodology Ready for Download the OVM runs on their simulators and enables in engineering and engineering management Cadence Design Systems, Inc. and Mentor backward compatibility with their existing en- at National Semiconductor and Digital Equip- Graphics Corp. have announced immediate vironments, Advanced Verification Methodol- ment. Gavrielov earned a bachelor’s degree in availability of the Open Verification Method- ogy from Mentor Graphics and Incisive Plan- electrical engineering and a master’s degree ology (OVM). Distributed under the standard to-Closure Methodology (Universal Reuse in computer science from the Israel Institute open-source Apache 2.0 license, the OVM Methodology module) from Cadence. of Technology (Technion) in Haifa, Israel. He source code, documentation and use examples possesses five patents. may be downloaded free of charge from www. Cadence Design Systems Inc, San Jose, CA. In his new role, Gavrielov succeeds one of ovmworld.org. (408) 943-1234. [www.cadence.com]. the most highly respected CEOs in the industry. The OVM, based on IEEE Std. 1800-2005 Mentor Graphics Corporation, Wilsonville, OR. Roelandts was named president and CEO of SystemVerilog standard, is the first open, lan- (503) 685-7000. [www.mentor.com]. Xilinx in 1996 after a 30-year management ca- guage-interoperable SystemVerilog verifica- reer at Hewlett-Packard Co. Just before joining tion methodology in the industry. The OVM Xilinx Names New President & Xilinx, he served as senior vice president re- provides a methodology and accompanying CEO sponsible for all aspects of HP’s then $6 billion library that allow users to create modular, re- Xilinx, Inc. has announced that Moshe Gavr- worldwide computer systems business, includ- usable verification environments in which ielov, 53, has been appointed president and ing research and development, manufacturing, components communicate with each other via chief executive officer (CEO), succeeding Wil- marketing, professional services and sales. JANUARY 200 
  • 9. news Over more than a decade, Roelandts has led Xilinx through an intense period of change within the semiconductor industry, growing the company’s sales from $560 million to over $1.8 billion in fiscal year 2007. During his tenure, Roelandts significantly expanded the company’s global business and initiated its suc- cessful market diversification strategy to better address high-growth end markets, including consumer, automotive, industrial and defense. These markets have grown from 12 percent of total revenues in fiscal year 2002 to 45 percent toward the commercialization of its Micro of total revenues today. Hydrogen technology. The commercialization of Angstrom’s Xilinx, San Jose, CA. (408) 559-7778. technology reached another milestone on [www.xilinx.com]. November 16th, 2007, when the International Civil Aviation Organization (ICAO) created Hydrogen Fuel Cells for Portable new regulations that will permit Angstrom’s Devices devices to be transported globally in the pas- At CES, Canadian start-up Angstrom Power senger cabin of commercial aircraft. Final Inc. announced the completion of a six-month approval is expected before the regulations test of fully integrated hydrogen fuel-cell-pow- take effect in January 2009. With approval nd ered mobile devices. Offering twice the run- from Transport Canada, which preceded the er exploration time of batteries and with recharge times on ICAO regulations, Angstrom products have ether your goal the order of 10 minutes, Angstrom’s EverOn already made more than 60 commercial speak directly ical page, the capability proposes to supplant the lithium-ion flights to date. ght resource. batteries commonly used in today’s portable technology, electronic devices. Angstrom Power Incorporated, es and products Angstrom’s power platform was success- North Vancouver, BC. (604) 980-9936. [www.angstrompower.com]. ed fully integrated into MOTOSLVR L7 handsets for the trial, with no modification to the outside dimensions of the devices. The trial devices did not rely on the use of any battery—instead, they Neonode to Launch N2 Mobile drew power from Angstrom’s Micro Hydrogen Phone in U.S. companies providing solutions now platform, which is comprised of a novel fuel Swedish mobile technology company Neo- exploration into products, technologies and companies. Whether your goal is to research thearchitecture, from a company, cell latest datasheet innovative micro-fluidics and node will launch their latest mobile phone Neo- mp to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level tank. Angstrom a refillable hydrogen storage of node N2 in the United States in 2008. The cut- has demonstrated research results showing gy, Get Connected will help you connect with the companies and products you are searching for. ting-edge phone utilizes Neonode’s patented onnected twice the talk-time of the equivalent battery- neno user interface and zForce optical touch powered devices in side-by-side testing. screen technology, offering users an intuitive Angstrom’s fuel storage is designed for and easy to navigate experience. tight integration with the fuel cell and features metal hydrides. Metal hydrides bond hydrogen molecules directly to the surface of the mate- rial; hydrogen desorbs from metal hydrides in End of Article a self-regulating fashion at low pressures and ambient conditions. The company is currently collaborating Get Connected with world-leading battery manufacturers, with companies mentioned in this article. portable electronic device makers—includ- www.portabledesign.com/getconnected ing Motorola—and mobile service providers 10 PORTABLE DESIGN Get Connected with companies mentioned in this article.
  • 10. The most recent development in mobile Initiated by the Forum’s Public Safety Spe- phone technology is the emerging popularity cial Interest Group (SIG) and prepared by an of the touch screen. Neonode N2 uses the most ad hoc committee, the 21-page report (“Tech- advanced touch screen technology, the zForce nology Considerations and Recommendations optical touch screen. It doesn’t need any hard for Software Defined Radio Technologies for pressure or stylus but works quickly and ac- the 700 MHz Public/Private Partnership”) curately by reacting to sweeping and tapping cites the upcoming auction and licensing of signals on the screen. The intuitively organized ity to carry current over distances longer than the 700 MHz spectrum as a unique opportuni- user interface, neno, delivers quick and easy a couple of centimeters. Therefore, for large ty to fulfill the growing demand for spectrum access to applications and content. area OLEDs, the ITO layer must be topped resources for commercial and public safety Neonode N2 was launched in Europe (third with a thick metallic grid to prevent gradient broadband applications. quarter 2007) to critical acclaim. Neonode N2’s of light emission caused by the sheet resistance The report notes that the FCC has adopted the United States phone carrier and retail availabil- of ITO alone (typically 30 ohm/sq). The new strictest ever build-out rules for wireless servic- ity will be announced the second quarter 2008. anode Silverduct has a sheet resistance of less es and established rules to govern the partner- Neonode demonstrated its Neonode N2 mo- than 4 ohm/sq, thus enabling large area OLEDs ship between commercial carriers and the pub- bile phone as well as their technologies at this without additional metal grids. This is an im- lic safety community in sharing spectrum and month’s Consumer Electronics Show. portant step especially for transparent and bot- network resources. Though it acknowledges Neonode also announced that it has joined tom emission OLEDs in which the metal grid is that improving public safety communications with U.S. sales channel development and sup- visible. Additionally, by eliminating the metal ply chain company, Distribution Management grid Silverduct offers significant potential for Consolidators Worldwide LLC (DMC), to form reducing manufacturing costs. Neonode USA. The new entity will market OLEDs are semiconductors made of thin existing and new innovative products within organic material layers of only a few nanome- North America, Latin America and China, and ters thickness. They emit light in a diffuse way will commercially market the Neonode tech- to form an area light source. In a fast growing nology globally. display market OLEDs are key part of a revolu- tion: the dream of paper-thin, highly efficient Neonode USA, New York, NY. (917) 312-0694. displays with brilliant colors and great flexibil- through sharing resources with a commercial [www.neonode.com]. ity in design is becoming reality. OLEDs rep- system is an innovative concept for using the resent the future of a vast array of completely new 700 MHz spectrum, the report recognizes Breakthrough in Glass Substrates new lighting applications and at the same time the challenges that implementing the proposed for OLEDs offer the potential to become even more effi- network presents. Derived from the FCC re- Saint-Gobain and Novaled have demonstrat- cient than energy-saving bulbs. quirements, the challenges include meeting ed the feasibility of large area OLEDS, based the divergent needs of commercial and public on a new high-performance metallic anode, Novaled AG, Dresden, Germany. safety users; coverage; shared operational con- with Saint-Gobain Recherche technology and +49 351 796 5819. [www.novaled.com]. trol; robustness; adaptability; and spectrum use Novaled OLED proprietary developments. in the absence of network build-out. Researchers at Saint-Gobain Recherche The Forum report offers specific examples (SGR) have created a highly conductive trans- SDR Forum Report Makes of how these technologies can be used to ad- parent electrode “Silverduct,” bringing up to Technology Recommendations for dress critical implementation challenges of sys- 10 times better surface conductivity than tra- the 700 MHz Spectrum tems that meet the FCC’s defined service rules. ditional ITO (Indium Tin Oxide). Thanks to The Software Defined Radio (SDR) Fo- One such approach incorporates SDR, cogni- the Novaled PIN OLED technology for high- rum, a nonprofit international industry as- tive radio and dynamic spectrum access tech- efficiency OLEDs, samples were successfully sociation supporting the advancement of re- nologies—in both the system infrastructure and manufactured on large area surfaces. SGR configurable wireless technology, has issued subscriber units—to provide a highly flexible and Novaled now see the possibility to pro- a report identifying how SDR and cognitive network solution that can meet diverse require- duce OLED devices up to 100 cm², which radio technology can facilitate implement- ments and develop in concert with technology will ease the manufacturing of large OLED ing a nationwide interoperable broadband and operational evolution. lighting products. network in the 700 MHz spectrum that con- Traditional ITO coated glass impedes the forms to Federal Communications Commis- SDR Forum, Denver, CO. (303) 628-5461. race to large area OLED, due to its limited abil- sion (FCC) regulations. [www.sdrforum.org]. JANUARY 200 11
  • 11. analysts’ pages iSuppli Trims 200 global semiconductor revenue will rise to Semiconductor Forecast $291.4 billion in 2008, up 7.5 percent from Citing global economic woes, iSuppli Corp. an estimated $270.9 billion in 2007. This rep- has reduced its forecast for global semicon- resents a 1.8-percentage-point reduction from ductor revenue growth in 2008, but still fore- iSuppli’s previous prediction in September of sees a positive year for the market—particu- a 9.3 percent increase for the year. Figure 1 larly in the second half. iSuppli now predicts presents iSuppli’s forecast for global annual semiconductor revenue. figure 1 Global semiconductor sales in 2008 will be negatively impacted by rising energy costs. Worldwide Semiconductor Revenue Forecast Furthermore, the sub-prime mortgage crisis is (Revenue in Millions of U.S. Dollars) dimming the economic outlook for the United States next year. This will have global reper- 380,000 cussions, impacting demand in other nations. 360,000 361,379 These factors will contribute to underinvest- ment and nervous customers in 2008, restrain- Millions of U.S. Dollars 334,061 340,000 ing growth as they cut orders. 320,000 303,492 First-Half Struggles 300,000 291,360 Semiconductor market conditions will be ex- 280,000 270,930 tremely weak in the first half of 2008. Global 260,000 260,222 chip revenue during the first six months of the year will decline to $135.9 billion, down 4.5 240,000 percent from $142.3 billion in the second half 220,000 of 2007. Memory market conditions will be very poor 200,000 2006 2007 2008 2009 2010 2011 during the first half of 2008, with prices falling due to oversupplied conditions for DRAM and NAND-type flash memory early in the year. The DRAM market is expected to undergo a figure 2 pricing recovery in the second quarter of 2008, but NAND will not begin to rebound until the iSuppli Global Electronic Equipment Revenue Forecast third quarter. Because of this staggered recov- (Revenue in Millions of U.S. Dollars) ery, the impact of memory’s resurgence will not be felt by the overall semiconductor market 2000000 until the third quarter of 2008. 1865261.988 With memory devices expected to account 1776266.815 for 21.6 percent of global semiconductor rev- Millions of U.S. Dollars 1800000 1683117.977 enue in 2008, developments in this market will 1598466.449 have a major impact on the overall chip indus- 1600000 try. The normal, seasonal up tick in semicon- 1499163.574 ductor sales will drive the recovery in memory 1400000 1395579.454 in the second half. However, iSuppli cautions that the potential arrival of a much-feared re- cession in 2008 could put a damper on this ex- 1200000 pected growth and may scuttle the anticipated second-half recovery. 1000000 2006 2007 2008 2009 2010 2011 Equipment Outlook Reduced Along with the reduction in the semiconduc- tor outlook, iSuppli has reduced its 2008 growth 12 PORTABLE DESIGN
  • 12. forecast for all types of electronic equipment. RF Power Semiconductor Market study puts wireless infrastructure—which is Global electronic equipment revenue is expect- Will Near $1 Billion in 2012 well understood—into the context of the rest ed to rise to $1.6 trillion in 2008, up 6.6 percent A new report by ABI Research predicts of these markets.” from $1.5 trillion in 2007. This is down 0.4 that the market for RF power semiconduc- of a percentage point from iSuppli’s previous tors—those with outputs of 5W or more—will ABI Research. Oyster Bay, NY. (516) 624-2500. forecast of 7 percent growth. Figure 2 presents approach $1 billion by 2012, with markets out- [www.abiresearch.com]. iSuppli’s forecast for global annual electronic side of wireless infrastructure starting to take equipment revenue. up the slack. Notebook PCs and 3G mobile handsets at- But according to research director Lance WiMAX Will Be Successful, Study tained strong growth in shipments in 2007. Wilson, “The shape of the industry five years Says However, growth in these products is not ex- hence will depend on three critical questions. Forward Concepts has announced the pub- pected to reach the same levels in 2008. At the manufacturing level, will the introduc- lication of its newest in-depth study of the Equipment revenue in 2008 also will be im- tion of gallium nitride and silicon carbide RF global WiMAX market. The new 300-page pacted by economic concerns and reductions in power devices mean the demise of Si LD- study, “WiMAX ‘08: The 3G+ Broadband Al- capital spending. MOS? With mobile/3G infrastructure mar- ternative,” is an in-depth analysis of operators, kets in decline, will they continue to drive equipment, chips and broadband alternatives, iSuppli Corporation, El Segundo, CA. both wired and wireless. (310) 524-4000. [www.isuppli.com]. According to the principal author, Carter L. Horney, “3G cellular (HSPA and EV-DO) and Ultrawideband Beginning to Take mobile WiMAX are the technologies that will Off serve the majority of the 2012 mobile wireless The market for Ultrawideband (UWB) fi- broadband market, but HSOPA (High Speed nally started to take off in 2007, reports In- OFDM Packet Access), LTE (Long Term Evo- Stat. Though regulatory hurdles over UWB lution) and/or Ultra Mobile Broadband (UMB) still persist worldwide, the first UWB-enabled the RF power semiconductor industry as they will also be available then.” Key study findings notebook PCs have shipped last year from Dell, have in the past? Will the market segments include: Lenovo and Toshiba, the high-tech market re- outside of wireless infrastructure shore up • WIMAX, variously as fixed or mobile ser- search firm says. this market space?” vices, will bring broadband access services “The primary question for UWB now is: To answer these and other questions, ABI to rural and undeveloped regions of the Will other product segments follow where PCs Research undertook a market sizing study world. lead?” says Brian O’Rourke, In-Stat analyst. for all RF power semiconductors with power • WIMAX growth in India will be strong and “UWB is a very flexible technology in that it outputs above 5W, operating at frequencies of will precede 3G rollouts. supports multiple standards, including WUSB, 3.8 GHz and below. (A later study will target • WIMAX will become large in China, but Bluetooth 3.0, IP over UWB and Video over those operating at higher frequencies.) The on the heels of 3G TD-SCDMA. UWB. This should enable the technology to study sizes the RF power semiconductor mar- • If mobile WiMAX can supplement exist- gain design wins in a wide range of product ket into six usage-based segments and 24 sub- ing cellular networks as an overlay, it will segments, including PC peripherals, Consumer segments, providing a highly detailed, market- become a mainstream technology. Electronics (CE) and mobile phones.” driven analysis. Recent research by In-Stat found the follow- The six major segments are: wireless in- Will Strauss, Forward Concepts’ president ing: frastructure, military, ISM (Industrial/Scien- and editor/contributor of the report said “High • UWB-enabled notebook PCs hit the market tific/Medical), broadcast, commercial avion- profile cellular operators that have put their in mid-2007. PC peripherals will follow in ics and non-cellular communications. Each of weight behind Mobile WiMAX include Sprint 2008. these is subdivided into between two and six Nextel in the U.S., Rogers in Canada, KDDI • CE and communications applications with specialty segments. and Softbank in Japan, and Telefonica in both UWB won’t hit the market in volume until The need for such a study arose, accord- Spain and Latin America.” The study also notes 2010. ing to Wilson, because “This market has been that the supporting ecosystem is growing, for • In 2011, over 400 million UWB-enabled overshadowed for many years by the wireless example: devices will ship. infrastructure sector. Now that new 3G/cellu- • Over 200 Operators are deploying WiMAX, lar wireless infrastructure deployments are de- worldwide In-Stat, Scottsdale, AZ (480) 483-4440. clining, there is a paucity of information about • Over 30 companies are supplying WiMAX [www.in-stat.com]. how the rest of the industry is faring. This infrastructure equipment JANUARY 200 13
  • 13. analysts’ pages • Over 16 companies are providing WiMAX An iPhone Minus the Phone? To cut space usage, the iPod touch makes client equipment Functionally, the Apple iPod touch is an use of some advanced packaging for its com- • Over 19 companies offer 802.16e MAC/ iPhone minus several features, including cell- ponents not seen in the iPhone, including 0201 PHY baseband chip sets phone capability, Bluetooth and certain soft- diodes and passive components in 01005 en- • Over 15 companies are now offer WiMAX ware elements. Otherwise, the core features of closures on the touch’s WLAN module. radio transceiver chips the iPhone user experience are all present in the “This is the first time iSuppli has seen iPod touch, including orientation sensing, Web these components in a product we’ve torn Forward Concepts, Tempe, AZ. (480) 968-3759. surfing via Wi-Fi and the product’s signature down,” Rassweiler said. “Apple products [www.fwdconcepts.com]. feature: a 3.5-inch diagonal touch screen with always seem to push the envelope in terms multi-touch sensing. These advanced features of space savings, and therefore we often first Despite Progress, Uncertainty place the iPod touch right at the top of Apple’s see the newest, most-compact components in Remains for WiMAX iPod line. Apple products.” WiMAX continues to make gains, with “The iPod touch likely represents the future The iPod touch design also pushes the en- network trials becoming commercial deploy- of the high end of the iPod line,” said Andrew velope in terms of memory density. The high- ments, and well-known vendors adding the Rassweiler, teardown services manager and end version of the product includes 16 Gbytes technology to their product portfolios, reports principal analyst for iSuppli. “Click Wheel- of NAND flash memory, more than any In-Stat. Despite many positive events over the interface and Hard-Disk Drive (HDD)-based product in the Apple iPod line. In contrast, last 12 months, however, WiMAX still faces versions of the iPod are expected to wane the high-end iPhone offers only 8 Gbytes of much uncertainty, the high-tech market re- in favor of touch-screen and flash-memory- NAND flash. search firm says. equipped models like the iPod touch. But de- Another notable difference is in the Printed “Investor pressure could force Sprint to spite its functional and physical outward re- Circuit Board (PCB) design. The iPod touch pull back on its announced deployment,” semblance to the iPhone, and the fact that its employs a single PCB as opposed to the says Daryl Schoolar, In-Stat analyst. “As the internals borrow heavily from the iPhone, the iPhone’s modular two-PCB design. largest planned deployment, Sprint’s actions iPod touch is no iPhone clone, and has its own Other differences between the touch and the could impact what other carriers do with unique design.” iPhone include a new set of components to sup- WiMAX, and negatively impact the entire port the iPod touch’s Wireless LAN (WLAN) WiMAX community.” Family Resemblance functions and the location of the touch-screen Recent research by In-Stat found the follow- Rassweiler estimated the iPod touch and circuitry on the main PCB—rather than on the ing: iPhone designs have a 90 percent commonality touch-screen module. • Shipments of 802.16e-compliant infra- in terms of components. The arrival of the flash-memory-based touch structure overtook 802.16d in 2007. For example, the key Integrated Circuit (IC) will have major implications for the rest of Ap- • North America service revenues will ac- at the core of both the iPod touch and iPhone ple’s iPod line, iSuppli believes. count for 41% of all service revenues in is Samsung Electronics Co. Ltd.’s video/ap- “The touch, along with the nano, may drive 2012. plications processor, a chip based on an ARM Apple’s HDD-based iPods close to extinction • Vendors remain uncertain over the form microprocessor core and employing stacked in the near future,” said Chris Crotty, senior and business case for WiMAX femtocells. on-package memory. Costing $13.19 based analyst, consumer electronics, for iSuppli. on iSuppli’s October estimate, the Samsung “While not a dollar-for-byte match for HDDs, In-Stat, Scottsdale, AZ. (480) 483-4440. processor accounts for 8.5 percent of the iPod flash now offers sufficient capacity that many [www.in-stat.com]. touch’s total cost. consumers are willing to trade off storage for Another common part between the two advanced displays and features.” Teardown Reveals Apple’s iPod products is a power-management IC from touch is More Than an iPhone NXP Semiconductors Netherlands B.V., cost- iSuppli Corporation, El Segundo, CA. Without a Phone ing $2.61 and accounting for 1.7 percent of the (310) 524-4000. [www.isuppli.com]. On the outside, Apple Inc.’s iPod touch looks a iPod touch’s cost in October. lot like its iPhone. On the inside, there’s a strong resemblance too—but a dissection conducted Design Departure by iSuppli Corp.’s Teardown Analysis service However, the iPod touch’s design differs reveals the touch sports a distinct design and from the iPhone in that it is uniquely optimized unique advancements compared to the iPhone. to meet its form-factor and cost requirements. 14 PORTABLE DESIGN
  • 14. Keep your most precious stuff safe and secure Don’t put important applications in the hands of Other Key commodity compact flash card suppliers. White Features: Electronic Designs’ CompactFlash® is made for • Firmware critical industrial or medical applications with the control same reliability and attention to detail that our • World class military products receive. Commodity flash cards wear-leveling may have hidden component changes that affect to extend product life performance. We offer complete traceability and • Data loss protection provide customer notification for any part changes. • Densities from 128MB to 8GB • High Endurance — 4 x 106 Cycles • Obsolescence Management New Medical Series 1 and Revision Control CompactFlash cards from • Environmentally Resistant White Electronic Designs Conformal Coating Option offer unmatched reliability • Dedicated 32-bit RISC Flash Controller and stability even in • RoHS Compliant power-down interruptions. • Error Correction Control (ECC) • Brown Out Protection To learn more, visit www.whiteedc.com/compactflash www.whiteedc.com Tel: 602.437.1520 • Fax: 602.437.9120 Microelectronics • Display Systems • Interface Electronics • Electromechanical Products * Not authorized for use as critical components in life support devices or systems. CompactFlash® is a registered trademark of SanDisk Corporation.
  • 15. cover feature flash memory Dealing with the Limitations of Flash Memory Low-power non-volatile memory is critical for a wide range of portable devices. In many of them, flash is not an option. by Xerxes Wania, President and CEO, and E Steven Cliadakis, VP of Worldwide Sales and Marketing, Sidense Embedded non-volatile memory (NVM) is a mize the read range of these tags. The tags must critical component in a wide range of applica- also be field-configurable, which eliminates tions that require a cost-effective, secure and masked ROM as a storage medium. low-power means of storing critical data and Implantable Medical devices are not what code. Two diverse portable device examples— most people think of when they hear the term RFID tags and implantable medical devices— “portable devices.” However they are, indeed, demonstrate the need for this type of memory. part of this general category with some very RFID tags, which include both a silicon chip unique requirements. With each generation, and an antenna, provide a simple and inexpen- devices such as pacemakers/defibrillators and sive way to deliver accurate data on tagged cochlear implants become more complex, with items (Figure 1). Applications for these tags in- ever increasing data storage requirements. As clude tracking consumer retail goods, verifying an example of these “ultimate body comput- the authenticity of pharmaceuticals, tracking ers,” ICDs (Implantable Cardioverter Defibril- automobiles through tollbooths and tracing lost lators) have to not only hold large amounts of pets. Embedded NVM for these tags must be history data, they also need to store operational cost-effective, adding negligible cost to these information such as threshold voltages and very low priced components—some tags cost trigger heart rates, along with the processor less than 10 cents in large quantities. This re- code that tells the device what to do (Figure 2). quires NVM that adds no cost to the chip pro- The latter two needs require an extremely reli- cessing and has a small footprint. The memory able non-volatile memory, with retention rates must also dissipate very little power to maxi- greater than 10 years. Device failure is not an 16 PORTABLE DESIGN
  • 16. with standards. with Wind River. Mike Deliman Here’s a guy who appreciates the view from above. When he’s not trekking the high plains and mountain passes of Tibet, Mike Deliman is working on aerospace and defense projects for Wind River. He’s fond of Mars rovers, solar panels, and astronauts; and his real-life heroes are Albert Einstein and the Dalai Lama. He’s aiming high. Regional Developer Conference, Aerospace and Defense Edition Register now to join Wind River and our partners at one of three , full-day conferences dedicated to Wind River’s aerospace and defense solutions including: Wind River's new VxWorks 653 Platform 2.2, Wind River Real-Time Core for Linux (with FSMLabs technology), Wind River's VxWorks AMP/SMP multicore support, ARINC 653 and Integrated Modular Avionics (IMA) , and DO-178B safety certification http://www.windriver.com/announces/ad_conference/index.html March 12, 2008 March 27, 2008 April 2, 2008 Hilton Santa Clara Turf Valley Resort Four Seasons Resort & Club Dallas 4949 Great America Parkway 2700 Turf Valley Road at Las Colinas Santa Clara, CA 95054 Ellicott City, MD 21042 4150 North MacArthur Boulevard Tel.: 408-330-0001 Tel.: 410-423-0833 Irving, TX 75038 Tel.: 972-717-0700 ® 2008 Wind River Systems, Inc. The Wind RIver logo is a trademark, and Wind River is a registered trademark of Wind River Systems, Inc. Others marks are the property of their respective owners.
  • 17. cover feature Flash Memory – It isn’t for Everything Flash memory technology has made tremendous gains over the past few years. Driven primarily by the consumer market, flash has found its way into a wide range of consumer devices that need to store large amounts (Gigabytes) of digital audio, graphics and video content; it is being used to store boot-up and other code for processor cores; and is currently being touted as a more reliable, lower-power alternative for hard disk drives in low-end PCs. While a very useful non-volatile memory (NVM) technology for devices that do not require high levels of stored data security and minimal cost, flash technology does have some inherent shortcomings that preclude its use in certain ap- plications—mostly embedded—that require low cost, small memory footprint, a high level of security, and scalability to leading-edge process nodes and beyond (Table 1). Standard Read Scalable Scalable High Logic Field Prog. Low Cost Access Secure <0nm <3.3V Density CMOS <10ns NVM (antifuse Yes Yes Yes Yes Yes Yes Yes Yes based) Flash No - (floating No No No Yes Yes No No erasable, gate) readable Table 1 Flash memory has some weaknesses that eliminate it as a choice for certain embedded applications where other NVMs that are not based on floating-gate technology make more sense. Scalability is one area where flash memory has severe limitations. The technology works by storing charge on a float- ing insulated gate. Unlike DRAM, which is refreshed periodically, flash’s stored charge must remain intact for long peri- ods of time and should have a retention period of 10 years or more. As process nodes shrink to 90 nm and below, oxide thicknesses decrease, resulting in increasing levels of charge leakage and a decrease in flash data retention rates. As a result, flash technology runs one to two generations behind the leading-edge logic CMOS processes in which SoCs are fabricated to keep costs low and feature sets rich. NVM technologies that are not based on a floating gate, such as those that depend on gate oxide breakdown to pro- gram a memory bit, do not suffer from this charge leakage issue. To embed flash in a standard logic CMOS process requires additional masks and process steps. These extra steps add significant cost to the chip, around 30%-50%. For many consumer-driven applications, where profit margins are razor thin, embedded flash is just not a viable alternative. For applications that require only one-time or few-time programmable memory in large quantity, such as processor boot-code storage, embedded flash on the same chip as the processor(s) makes the chip too large and adds additional silicon cost to the end product. For embedded applications that are few-time programmable, such as boot code that may be updated infrequently, a small footprint OTP memory with an unallocated memory sector that can be programmed and swapped with a previously programmed sector is a smaller and less expensive alternative to flash. Finally, many applications require a very high degree of security to protect hardware and software chip resources, as well as user information and digital content. These uses range from low-bit-count security keys and IDs to multi-megabit code storage. This has become increasingly important over the past few years with the proliferation of mobile consumer devices that download and store huge amounts of copyrighted digital content, requiring a high level of protection against piracy through the use of encryption keys and other techniques. A chip developer who fails to protect third-party IP may be at serious legal and financial risk. Flash is just not a very secure storage medium. Since flash memory is pro- grammed through a charge-storage mechanism, it can be read (and pirated) using voltage contrast microscopy or altered (maliciously or accidentally) using SEM or FIB (focused ion beam) equipment. Charge on a floating gate in flash memory can be removed through exposure to high temperature, light or electron and ion beams. Since NVM solutions based on oxide breakdown technology do not store charge on a floating gate, they don’t have this charge removal problem and cannot have their contents read through voltage contrast techniques. So while flash has its uses, primarily for storing large amounts of frequently updated data, it doesn’t have the se- curity, cost and process scalability advantages of an embedded, dense OTP memory. Designers should consider using embedded OTP IP as an enabling storage technology in many of their designs. 1 PORTABLE DESIGN
  • 18. cover feature figure 1 Both RFID and implantable medical chips demonstrate the need for embedded NVM with the attributes of small size and cost, high reliability, long retention rate, very low power dissipation and field configurability. An RFID tag for tracking live or inanimate objects requires very low cost and small memory for storing IDs. (courtesy SanDisk) option—even if device failure is not life threat- ening, it requires replacement and an invasive surgical procedure, with the accompanying risk figure 2 factors associated with any surgery. Electronic devices that are implanted within the human body need to withstand severe ex- ternal conditions. The body constitutes a cor- rosive environment, which means that devices, in which their power sources are hermetically sealed, need to be replaced when their battery levels fall below certain threshold voltages—a period of several years. This means that the electronics package, including the non-volatile memory, must be ultra low power. Long bat- tery life also translates to a smaller battery size for a given medical application, resulting in the smallest possible device size for implantation. While widely diverse in function and us- age, both RFID and implantable medical chips An ICD not only has to monitor and control demonstrate the need for embedded NVM irregular heart rhythms, it has to do so reli- ably storing code and operational param- with the attributes of small size and cost, high eters in non-volatile memory for several reliability, long retention rate, very low power years. dissipation and field configurability. Flash (courtesy www.defibrillator-help.com) memory technology does not provide all of these capabilities and designers must look elsewhere for embedded NVM IP for many of their chips (see sidebar “Flash Memory – It isn’t for Everything”). Sidense Corp., Ottawa, Ontario Canada. (613) 287-0292. [www.sidense.com]. JANUARY 200 1
  • 19. wireless communications mobile WiMax Mobile WiMax: How to Make Mobile WiMax Consumer Devices a Reality Mobile WiMAX promises a true broadband Internet experience. But making it mobile isn’t easy. by Frank Ferro, Director of Business Development, Sonics, Inc. W With the completion of the IEEE 802.16e spec- Given this, OEMs are challenging semicon- ification, mobile broadband service is now be- ductor manufacturers to significantly reduce ginning around the world to bring fixed broad- price and power consumption since the under- band services to homes and businesses. There ling silicon makes up a large percent of the are now over 75 commercial networks in oper- overall system power. ation worldwide supporting 1.3M subscribers. The bulk of these subscribers are using fixed Road to Low Power WiMax service. To continue subscriber growth, Since WiMax is based on complex Orthogo- network service providers have realized that nal Frequency Division Multiplexing Multi- giving consumers the ability to “take the Inter- Access (OFDMA) technology, vendors have net wherever you go” has huge potential. To do been focused on functionality, interoperability this effectively, mobile devices are needed that and time-to-market. This evolution is similar will mimic the Internet experience at home re- to cellular, wireless LAN (WLAN) and Blue- gardless of location. tooth. All of these wireless technologies were Original equipment manufactures (OEMs) initially expensive and power hungry, and the have provided the first generation of mo- resulting devices were large with limited fea- bile WiMax products including PCs, smart tures. As standards and the market stabilized, phones, gaming devices and ultra-mobile PCs chip companies began to focus on cost and (UMPC). Unfortunately, these devices are ex- power reductions. pensive and do not meet the battery life re- The methodology employed to achieve these quirements consumers have come to expect. reductions varied depending on the company. 20 PORTABLE DESIGN
  • 20. The Newest Wireless Solutions New Products from: ZigBee ® RFID Connect® ME & Connect® Bluetooth ™ Wi-EM www.mouser.com/digi/a GPS WLAN GPS Receiver Module www.mouser.com/tyco/a Cellular ISM ZigBee RF Transceivers www.mouser.com/ aerocomm/a The ONLY New Catalog Every 90 Days Experience Mouser’s time-to-market advantage with no minimums and same-day shipping of the newest products from more than 335 leading suppliers. RF Monolithics Short Range Radios and RFICs mouser.com/rfmonolithics/a The Newest Products For Your Newest Designs www.mouser.com (800) 346-6873 Over 900,000 Products Online
  • 21. wireless communications Many would rely on the next generation semi- MAC has control of the system resources and conductor technology node along with better peripherals. Much care is typically taken in se- power management design techniques. Some lecting individual blocks to be power-efficient. would also look for processors and peripher- However, the final chip performance may not als that were more power-efficient. These meet the intended power consumption targets techniques have clearly achieved good results, due to the interaction between the processor since many of today’s mobile devices have ac- blocks and the memory. ceptable operating times. In current SoC designs the CPU(s) con- Even so, the demand for more complex trols the data flow and the interaction with wireless systems continues to push forward. memory and peripherals. Since the design For example, while common cell phones may is “CPU-centric” the processor is frequently have acceptable battery life, smart phone bat- in an active state, which utilizes the most figure 1 teries, under heavy use, are likely to last only power. In addition to the control issue, the one day. Or an MP3 player battery life may be system has multiple processing elements that fine, but add video and WLAN to it and battery are competing for resources including access CPU DSP CPU life becomes a problem again. Now consider to memory and peripherals. With traditional (MAC) (PHY) (MAC2) the effects of adding WiMax to these devices bus architectures, bandwidth is limited with for a true mobile broadband experience. This the potential for long latency. Given this, the new capability will continue to push all aspects processor(s) will often waste cycles due to BUS of the system to reduce power. bus conflicts and waiting for data that will again leave the processor in an active state SoC Design Methodology longer than necessary. nd Technology decisions for mobile WiMax er exploration chip designs often center on choosing a Maximize Processor Efficiency Memory I/O CTL ether your goal processor with the performance to meet the Building on many of the existing system- speak directly ical page, the speed requirements while also supporting level power-saving techniques, an alternative ght resource. low-power features. Other component deci- “interconnect-centric” SoC architecture en- technology, sions include a digital signal processor (DSP) ables a significant reduction in overall power. es and products Typical WiMax SoC with additional Wireless to support real-time algorithm processing, This methodology starts from the view of the ed Protocol. input and output (I/O) devices and the size interconnect and builds out. Using a “micro- and types of on-chip memory. Along with network” (Figure 2) allows the SoC designers choosing system components, architecture to model the interaction between all process- decisions need to be made about which func- ing elements in order to optimize data flow and tions will be implemented in software vs. processing efficiency while also applying pow- companies providing solutions now hardware. These choices significantly influ- er-saving techniques across the entire SoC. exploration into products, technologies and companies. Whether your goal is to research the latest power, performance and overall cost ence the datasheet from a company, In addition to other advantages, the creation of mp to a company's technical page, the goal of Get Connected is to put you in touch with thesystem. From a business and applica- of the right resource. Whichever level of a micro-network offers many system advantages gy, Get Connected will help you connect with the companies and products you are searching for.of view, decisions need to be made tion point from the perspective of power consumption. onnected to determine if the SoC will support other wireless protocols that could include WLAN, Advanced Interconnect GSM, CDMA, Bluetooth and/or GPS. Any Architecture combination of these wireless technologies A micronetwork provides an advanced is possible, but adds significant complexity to interconnect fabric along with data flow ser- the overall system design. vices. Efficiency is improved by adding new A typical embedded WiMax SoC block dia- flow control services to the SoC. For exam- End of Article gram is shown in Figure 1 (Note: the diagram ple, the micro-network can support functions has been simplified, focusing only on the is- that include quality of service (QoS) to set sues concerning power). In this configuration, data priorities, firewalls to protect regions in Get Connected the system memory is shared between the memory, error handling, data width conver- with companies mentioned in this article. processing elements [although many systems sions and power management. These new www.portabledesign.com/getconnected use tightly coupled memory (TCM)] and each data flow services allow the CPU(s) to be- 22 PORTABLE DESIGN Get Connected with companies mentioned in this article.
  • 22. wireless communications come a facilitator thus improving its overall based on the specific application require- efficiency, which will have the effect of al- ments. The gain of processing power in the lowing it to remain in a low-power state for MAC can allow the system software designer longer periods of time. the flexibility of adding new functions to the Many micro-networks support a non-block- MAC. These functions may have previously ing architecture along with multi-threading been done by the applications processor or capability. A non-blocking transaction model other hardware. Integrating as many func- offers the advantage of servicing requests from tions as possible into the MAC has the ad- multiple processors at the same time with mini- vantage of a “zero load” architecture for the mal latency in the response (versus a blocking applications processor. This will save overall transaction model that services one processor at system power since the applications proces- a time). Multi-threading offers the advantage of sor will be able to remain in low-power mode splitting processes into logic threads in order to during data processing and not have to share figure 2 improve the overall processing efficiency (e.g., the work load with the MAC. real-time functions in one thread and channel CPU CPU information in another). Power Control (MAC) Memory (MAC2) WiMax SoCs can take full advantage of this Designing with an interconnect-centric ar- architecture given that there are multiple pro- cessors, often with high bursts of data traffic. chitecture also can allow for decoupling of each processor and peripheral from the sys- Sonics Micronetwork { Data Flow Services Advanced Fabric Data flow Services This is especially true for SoCs that have mul- tem. With decoupling, the interconnect acts DSP tiple wireless protocol MACs on a single chip. as a buffer between the system components, (PHY) Peripherals In this situation, non-blocking capability sim- thus enabling independent clock control and plifies the data flow since each processor will voltage levels to each section of the chip. have predicable bandwidth that will minimize Clocks and power can be removed from sec- WiMax SoC with a Micro network. the number of cycles wasted waiting for sys- tions of the SoC for maximum power sav- tem resources. As in any wireless system the ing when that portion of the chip is not in goal is to process the data quickly and return use. The interconnect works in conjunction to low-power mode. This improvement in duty with an external power unit to enable fea- cycle will contribute to the reduction in aver- tures such as auto-wakeup, rapid power-on age power consumption of the SoC. and power-off. Fast wakeup and power-down These processor efficiency improvements times would be difficult to achieve if imple- become even more significant as the amount of mented by the CPU due to long instruction data to be processed increases. For typical CPU cycle delays. and cache configurations, reductions in instruc- tions cycles of fifteen percent have been shown Conclusion in simulations for processing large amounts of The need for mobile broadband services is data (i.e., time waiting for data after a cache pushing mobile devices to the limit in terms of miss with non-blocking versus blocking). Hav- processing power and battery life. Innovative ing a non-blocking architecture will be a key techniques and architectures that drive reduc- performance advantage for mobile WiMax de- tion in power consumption for mobile WiMax vices that have video processing capability. devices are now required as the market has reached a maturity level that warrants these ef- System Considerations ficiency gains. A design methodology that cen- The gain in processor bandwidth can have ters on the interconnect allows SoC designers other positive impacts on the system. It is cer- to look at the overall system from a data flow tainly possible to reduce the clock speed of perspective in order to maximize processor ef- the processor thus lowering the active power ficiency, minimize latency and improve overall consumption. As mentioned previously, it is system power control. typically better to process the data as quickly as possible and return to low-power mode. Sonics, Inc., Mountain View, CA. This is a trade-off that needs to be evaluated (650) 938-2500. [www.sonicsinc.com]. JANUARY 200 23
  • 23. consumer electronics mixed-signal design Applying an Integrated Approach to Mixed-Signal SoC Verification As mixed-signal design complexity is expanding, verification complexity is exploding. Implementing an integrated verification flow can save a lot of headaches. by Karen Chow, Technical Marketing Engineer, Design to Silicon Division, M Mentor Graphics Corp. Mixed-signal systems-on-chip (SoCs) increas- formats for the different blocks, with differ- ingly involve more and more digital process- ent levels of abstraction. The different for- ing functions isolated into multiple power do- mats are typically classified into either digital mains, hundreds or thousands of analog-digital or analog design. For purely digital designs, interconnections and operating frequencies al- many production-proven tools are available ways closer to pure RF. Clearly, genuine full- for standard cell creation, behavioral lan- chip verification of such complex chips calls guage simulation, synthesis and place and for careful planning and organization, as well route. For analog designs, traditional tools as flexible simulation technologies. Whether are used for schematic entry, accurate device- you are verifying a power-management circuit, level simulation, handcrafted layout and in- a single-chip multi-standard radio transceiver, teractive wiring. or a mobile communications processor, differ- So how do you integrate the design blocks ent strategies are required. Technologies that at the chip level and complete the testing and allow transparent and efficient combinations verification? Do the blocks really fit together of analog/RF descriptions, analog/mixed signal at the top level? Will the design function as (AMS) behavioral models and pure digital de- planned? To ensure a working design, an AMS scriptions—all interoperating under a common SoC chip-level design needs to be verified in its verification platform—can help maximize full- entirety. For this purpose, digital/analog (D/A) chip, mixed-signal verification. integration is mandatory. Shrinking manufac- Mixed-signal design starts are on the rise. turing processes require inclusion of parasitics An AMS SoC designer applies various design for analysis, and the integration of parasitic 24 PORTABLE DESIGN
  • 24. LatticeECP2M FPGAs More of the Best 4 to 16 SERDES (3.125Gbps) Only 100mW per channel Up to 5.3Mb of Block and Distributed RAM Supports PCI Express, Ethernet Up to 95K LUTs & other packet protocols DSP Blocks With multiply and accumulate PLLs and DLLs For optimized frequency synthesis & clock alignment Flexible I/O Up to 601 I/O Pre-Engineered Source Synchronous I/O Up to 840Mbps LVDS I/O Superior Configuration Options • Encrypted bitstream support • TransFR™ technology for easy field updates • Dual boot support LatticeECP2M: The First Low-Cost FPGA with 3Gbps SERDES Get more for less with Lattice’s new LatticeECP2M™ LatticeECP2M FPGAs give you “More of the Best” for less. family. No other low-cost FPGA offers up to 16 SERDES Visit our website at www.latticesemi.com. You’ll find channels with full-duplex serial data transfers at rates up information about Lattice’s complete line of FPGAs, includ- to 3.125Gbps. Best of all, each SERDES channel operates ing LatticeECP2M, LatticeECP2™, LatticeSCTM Extreme on a cool 100mW at maximum speed. Performance System Chip FPGAs, LatticeXPTM non-volatile FPGAs and many more. If you haven’t looked at Lattice The LatticeECP2M family offers even more, including FPGAs lately, look again – things have changed. up to 5.3Mb of RAM, high-speed DSP blocks, 533Mbps DDR2 memory interface and SPI4.2 support. Plus, 128-bit AES Encrypted Bitstream support and Transparent Field For design software and a Reconfiguration (TransFRTM) allow you to keep your FREE FPGA handbook go to designs secure and easily upgradeable even after your latticesemi.com/ecp2m product has shipped. ©2008 Lattice Semiconductor Corporation. All rights reserved. Lattice Semiconductor Corporation, L (& design), Lattice (& design), LatticeECP2M, LatticeECP2, LatticeSC, LatticeXP, TransFR, and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries, in the United States and/or other countries. Other marks are used for identification purposes only, and may be trademarks of other parties.
  • 25. consumer electronics data adds yet another level of complexity to of the circuit and to decide whether it meets this problem. However, a post-layout simula- the specifications or if revisions need to be tion netlist can be created that includes parasit- made to the architecture. Once the design has ics and handles various data formats and that been finalized, full-custom layout is complet- will effectively re-simulate the design while ed. The layout is then verified by completing accounting for layout parasitic effects to ensure design rule checking (DRC), layout versus signal integrity. schematic (LVS) and parasitic extraction. In Yield problems and multiple spins are caused doing post-layout simulation with the para- by missed deep submicron effects. Mixed-sig- sitic resistance, capacitance and inductance nal SoC designs require full-chip timing analy- in place, you can see if the design will still sis as well as full-chip signal integrity analysis. meet the specifications. Unfortunately, flat full-chip parasitic netlists A typical digital design starts with a hard- are huge and impossible to simulate with tradi- ware description language such as Verilog tional flat SPICE-type simulators. or VHDL to describe the functionality of the design. This is referred to as register transfer Addressing Integration Issues level (RTL) design. This RTL design is then As a designer, you require increased capac- simulated to test functionality. Synthesis con- ity in analysis tools, but the tools may not be verts the RTL design into a gate-level netlist able to meet this requirement, so selected net containing standard cells and the connections extraction is used to reduce the netlist size. between them. Static timing analysis then pre- nd Unfortunately, selected net analysis misses dicts the expected timing of the circuit. Other er exploration important full-chip effects, especially inter- types of analysis include power analysis and ether your goal actions between critical nets and non-critical signal integrity analysis. From here, the place- speak directly ical page, the nets. D/A partitions require different extrac- and-route tool creates the layout, and extrac- ght resource. tion modes and netlist formats, but having tion is run to verify the timing. Circuit de- technology, separate D/A extraction results in incorrect bugging can force a new place-and-route run, es and products interface net delays. As a result, post-layout synthesis job, or even change the HDL source ed simulation and debugging can be very chal- code. Analog/RF flows require manual sche- lenging. Extra resources and scripting are matic capture and layout, unlike digital de- needed to make the analysis flow work. The signs, which tend to have a highly automated netlist reassembly process is manual and er- data-creation flow. ror-prone. Often, the extracted netlist is not When designing mixed-signal chips, full companies providing solutions now compatible with the analysis tool, and the custom and digital components are combined block pin order requires manual netlist ed- exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, together on the same chip, and verifying timing, mp to a company's technical page, the goal of Get Connected is to put you in touch with the avoid these pitfalls, designers need a its. To right resource. Whichever level of functionality and power are critical for success. gy, Get Connected will help you connect with the companies and products you are searching for.that integrates the extraction tool tool flow Each block can have their I/O and performance onnected with the mixed-signal simulator, successfully specified such that individual designers can in- working out these issues and enabling design- dependently design each block. For interface ers to complete full-chip post-layout analysis. purposes, a small functional model of the inter- How does this flow work? face can be used; and as the design approaches completion, a mixed-mode simulator can be Mixed-Signal Verification Flow used to verify this interface. Mixed-mode sim- A standard RF SoC design includes the RF ulators allow you to run digital logic cells with End of Article front-end, analog baseband and digital signal a digital simulator, while still using a SPICE- processing (DSP) blocks. On the full-custom level simulator for analog and RF blocks. To do design side (analog and RF), the first step is this, mixed-signal verification needs to occur at Get Connected to capture the design using a schematic cap- several different parts of the flow. with companies mentioned in this article. ture tool (Figure 1). Using a simulation tool, First, during the design phase, once the full- www.portabledesign.com/getconnected it is possible to determine the characteristics custom analog and RF schematic capture and 26 PORTABLE DESIGN Get Connected with companies mentioned in this article.
  • 26. consumer electronics simulation has been completed, and the RTL interconnect delays overwhelm gate delays at simulation has been completed, a top-level smaller technology nodes. Physical effects are test bench can be put together that will test the now the leading factor in the failure to achieve functionality of the full chip, including all of acceptable yield. AMS SoC designers need a the analog-to-digital interface interactions. parasitic extraction tool that delivers accurate To enable full-chip simulation, some analog parasitic data for comprehensive and accurate blocks may be modeled using VHDL-AMS mixed-signal post-layout analysis and simula- or Verilog-AMS. Once full-chip mixed-signal tion. An extraction tool that is able to extract simulation has been completed, chip-level as- interconnect parasitics hierarchically, such sembly is done to tie all of the different analog, as Mentor’s Calibre xRC, can address these RF and digital layout blocks together. DRC and LVS are run at the full-chip level. Then parasitic extraction is run, with different types figure 1 of extraction happening depending on the de- sign style. Finally, mixed-signal post-layout Digital Design simulation tests whether the design still meets RTL the specifications. If it does, then it’s time to tape-out. If not, then some re-design will need Analog Design Chip-Level RTL Simulation to occur. Schematic Capture Top-Level Testbench Synthesis The Extraction-to-Simulation Flow Simulation Mixed-Signal Simulation Static Timing Analysis Let’s examine the chip-level extraction to post-layout simulation flow in more detail. Custom Layout Chip-Level Assembly Place and Route The interaction between RF blocks, analog DRC/LVS DRC/LVS baseband subsets and digital baseband subsets Extraction of modern RF systems is becoming tighter. Extraction Extraction Static Timing Analysis Often, the verification of these interactions is impossible, putting first silicon at risk of fail- Post-Layout Simulation Post-Layout Simulation ure. ADVance MS RF is an effective simula- tion solution for verification of such circuits. No Yes Yes No Yes No The technology provides 100x or 1000x speed- Design Meets Design Meets Design Meets Specs? Specs? Specs? up ratios over regular time-domain simulation Tapeout! and enables complete simulation of RF SoCs. It can simulate communication systems contain- Mixed-Signal Process Flow. ing tightly linked RF and baseband functions with complex digital signal processing (DSP) in VHDL or Verilog. For example, direct con- version receivers or amplifiers with high-speed issues. The tool delivers compact, hierarchi- digital automatic gain control can be simulated. cal, transistor-level parasitic data, which can Verifying such systems requires simultaneous, be back-annotated and simulated with full- transistor-level simulation of the RF part with chip mixed-signal simulation tools. In using the baseband part in acceptable CPU times, in- parasitic extraction, the effects of parasitic cluding all of their analog-digital connections. capacitance, resistance and inductance on The designer needs a language-neutral envi- neighboring lines (crosstalk) can be measured ronment including SPICE, VHDL, Verilog and and corrected. Static leakage in portable de- standard analog behavioral languages such as vices can account for a significant percentage VHDL-AMS and Verilog-AMS. of total power consumption, and being able to Post-layout analysis has become increas- measure and compensate for it can increase ingly important in sub-micron designs because battery life. JANUARY 200 27
  • 27. consumer electronics Importance of Extraction for device performance to change depending on Portable Designs the distance from the gate to the edge of the Doing extraction can enable more robust diffusion. Finally, designers need to be able to portable designs. In addition to coupling ca- check that the optimizations made by the lay- pacitance, a large spectrum of new capaci- out engineer during device construction have tance and resistance interactions become rel- not degraded circuit performance. For these evant in low-power designs implemented in reasons, performing mixed-signal parasitic advanced processes. For example, vias are extraction is important. now significant contributors to net parasitic When using a verification interface, such as Calibre Interactive, you can set up extraction figure 2 for each individual block and have it target either the analog, RF, or digital engine in the Delay Calculation simulator. There are several inputs that are Schematic Hierarchy Time-It Command supplied to the interface: the layout gds file, PrimeTime Digital PrimeTime SDF the source netlist, the LVS and extraction rule Command DSPF/ Analog File SPEF Time-It files, and a command file for the delay calcu- Calibre LVS lator (Figure 2). The schematic hierarchy is Digital Analog read into the GUI and provides a hierarchy Calibre Interactive tree that determines the extraction hierarchy Analog Analog PEX and modes. LVS and extraction are then run, nd Calibre and the output netlist for the various domains xRC er exploration Analog are produced. For the digital blocks, delay ADMS ether your goal Layout GDSII DSPF calculation is run using either PrimeTime speak directly ical page, the or Time-It, and an SDF file is produced. For .INCLUDE ght resource. Layout Hierarchy Index the analog and RF blocks, a DSPF file is pro- technology, Analog duced. The digital and analog/RF blocks are es and products Digital Analog .BIND Verilog Gate-Level automatically stitched together for simula- File ed tion. When using this extraction-to-simula- tion flow, there is a minimum of changes re- Analog Analog Extraction Netlist Assembly Extraction Input & Simulation quired to the pre-layout test bench to set up the post-layout simulation. An Example of an Integrated Mixed-Signal Extraction-to-Simulation Flow. In summary, using extraction-to-simulation companies providing solutions now integration enables full-chip post-layout analy- exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, sis for mixed-signal designs, speeding up de- mp to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of coupling is capacitance. Also, poly-contact sign closure. It detects critical effects caused by gy, Get Connected will help you connect with the companies and products you are searching for.increasingly important. The higher becoming layout parasitics and allows for effective cost onnected operating frequencies enabled by the smaller reduction by minimizing risk and rework. This geometries now make interconnect induc- kind of verification strategy enables designers tance relevant. to meet schedules and minimize time to work- The copper interconnects being used to re- ing silicon, requiring fewer resources to set up duce parasitic resistance are harder to control and maintain flows. dimensionally and cause interconnect resis- tance and capacitance variations across a die. End of Article They also require greater metal uniformity to Mentor Graphics Corporation, Wilsonville, OR. (503) 685-7000. [www.mentor.com]. control these variations, which means met- al-fill simulation must be included because Get Connected planarity variations also affect circuit per- with companies mentioned in this article. formance. Nanometer device isolation tech- www.portabledesign.com/getconnected niques, like shallow trench isolation, cause 2 PORTABLE DESIGN Get Connected with companies mentioned in this article.
  • 28. portable power designing for low power Extend Battery Life Using Programmable Clock Technology Few things will do more to improve the power profile of your next portable design than getting better control of the clock. by Greg Richmond, VP of Engineering and CTO, SpectraLinear, Inc. S System designers are continually looking for This equation clearly indicates that minimiz- ways to minimize power consumption in both ing the equivalent system switching capaci- line-powered systems and especially in bat- tance and voltage by using components manu- tery-powered systems. Line-powered systems factured in more advanced, smaller geometry benefit from lower power by reducing supply processes will reduce system power. The trade- components, cooling costs and becoming more off here is the higher cost of advanced com- “green,” while the benefits for portable systems ponents and the additional cost of generating include these as well as extended battery life. multiple voltages and signaling levels, such as This article reviews the methods for reducing input clocks, since these components often in- system power consumption through optimized troduce different supply voltages. Notice also clocking of system components and highlights that controlling the system clock frequency(s) the benefits of programmable clock technology can have a dramatic effect on power consump- in achieving this goal. tion. Let’s look first at controlling the system clock frequency as a primary method for power Time Is Power reduction, and follow that with an analysis of In digital systems, the classic equation for minimizing the power consumed by clock sig- power dissipation, P=I*V, is transformed to nal distribution and then minimizing the power include the clock frequency, F, by noting that consumed by the clock generator itself. the current is equal to the rate at which digital nodes with average switching capacitance C Controlling the System Clock are charged to voltage V and then discharged System clock signals are traditionally sup- to ground. The power dissipation equation then plied by discrete oscillators or by crystals becomes P=V*(C*V*F), or P=C*V2*F. that are connected to ASICs having integrated 30 PORTABLE DESIGN
  • 29. portable power crystal oscillators. Multiple oscillators and/or where one or more components have an inter- figure 1 crystals in a system are not cost-effective when nal clock multiplying PLL, abrupt frequency compared to a single crystal and a silicon clock transitions (like starting and stopping a clock) System High processing Low processing generator, which uses Phase-Lock-Loop, or can create system timing violations because the Inactive demand demand PLL, technology to replace them. In addition “downstream” multiplying PLL is not able to the silicon clock generator is much more reli- stop immediately or can become unstable when Clock Freq Fmax able than the mechanical crystal resonators it the frequency ramps below its safe operating replaces, and it can be designed to include ad- range. If it is not possible to put the system dF vanced EMI and power reduction capabilities. into an idle or no-op mode when the frequency dt As mentioned previously, the primary ad- moves outside of the safe range, then it may vantage of a silicon clock generator in reduc- still be possible to use “frequency slewing” in- Time ing system power is its ability to minimize the stead. As shown in Figure 1, frequency slew- average system frequency. This is traditionally ing is the ability of a clock generator to switch Dynamically adjusting clock rate to match demand. done by monitoring the system processing and smoothly between one or more frequencies in I/O demand and then either stopping or slow- real time while the system is operating. ing the clock through direct pin or I2C control For systems that operate directly at the sup- of the clock generator. The processing demand plied clock frequency, there is no limit to the monitor can be as simple as a wired OR keypad minimum frequency or frequency slew rate, activity detector or as complex as a firmware dF/dt. However, in systems where one or more algorithm to monitor CPU activity. Care must components have downstream frequency mul- be taken in the design of the clock generator tiplying PLLs, care must be taken to ensure to ensure that clocks stop and start “glitch” that the frequency slew rate can be “tracked.” free. This means that the generated clock sig- The limit for safe tracking is set by the clock nal should always have a pulse width high and generator frequency slew rate, dF/dt, the down- low time that does not fall below the minimum stream PLL bandwidth and the amount of PLL specification. phase error allocated in the component and Stopping the clock instantaneously may not system timing budgets. While these limits are always be an option, however. In many systems calculated theoretically, it is also recommended figure 2 Oscilloscope Capture Oscilloscope Capture 4 3.5 3.5 3 3 2.5 2.5 2 2 Voltage Voltage 1.5 1.5 1 1 0.5 0.5 0 0 -0.5 -0.5 0 1 2 3 4 5 6 7 -1 time (s) x10 -8 0 1 2 3 4 5 6 7 time (s) x10 -8 FFT (Oscilloscope Capture Buffer #1) FFT (Oscilloscope Capture Buffer #2) 10 10 0 0 -10 -10 -20 -20 Magnitude (DB) Magnitude (DB) -30 -30 -40 -40 -50 -50 -60 -60 -70 -70 -80 -80 -90 -90 107 108 109 1010 107 108 109 1010 Frequency (Hz) Frequency (Hz) 40% power savings and -20db EMI reduction from Programmable Clock Waveform Tuning. JANUARY 2008 31
  • 30. portable power that the safe limits be empirically verified by not having the ability to optimize the signal increasing the frequency range and slew rate would result in a 40% increase in power con- to the point of system failure and then limiting sumption (= (5V-3.5V)/3.5V). them by an acceptable safety margin. Because these variables are different for every system Reducing Clock Generator Power and component, the ideal clock generator The final knob to be tweaked in our quest to figure 3 300K XIN/ 3 PLL with 6 SSCLK1/REFCLK1 CLKIN Modulation Control Output PCin Buffers, 7 SSCLK2/REFCLK2 XOUT 2 Dividers SSCLK3/REFCLK3 and 8 SSON#/FS PCout Switch To I/O Programmable Matrix 4 SSCLK4/REFCLK4 VDD 1 Configuration Register PD#/OE V-Reg To nd Core VSS 5 er exploration ether your goal speak directly ical page, the SpectraLinear’s SL15101 Programmable Clock. ght resource. technology, es and products should have programmable upper and lower minimize system power is to reduce the power ed frequency limits, programmable slew rates and consumption of the clock generator itself. This permit access directly to the PLL dividers that is especially important if the clock generator set the output clock frequency. remains active to supply the system heartbeat while the rest of the system is idle. As before, it Optimizing Clock Distribution is important that the clock generator be manu- companies providing solutions now A secondary consideration for reducing sys- factured in an advanced technology to mini- exploration into products, technologies and companies. Whether your goal is to research the power consumption is optimized distribu- tem latest datasheet from a company, mize internal switching currents. In many cases mp to a company's technical page, the goal of Get Connected is to put you in touch withof system clocks. Matching the impedance tion the right resource. Whichever level of the operating voltage of advanced processes gy, Get Connected will help you connect with the companies and products you are searching for. trace and end load will ensure that of the board does not support the higher voltage that may onnected the signal is free from ringing, which minimiz- be the single system supply or that is needed es the peak-to-peak voltage of the clock signal for the external clock signals. In this case the and hence the power consumption as well as clock generator should have internal regula- the radiated Electro-Magnetic Interference or tors, which not only allow low power operation EMI. Ideally the clock generator would have at higher supply voltages, but also provide im- programmable impedance to ensure a good proved immunity to system noise and maintain match to various line impedances, lengths and a stable clock. End of Article loads, and also a programmable rise/fall time to But there are other trade-offs as well with re- slow the edges, which reduces high frequency gard to lowering the internal operating voltage. harmonic content and minimizes EMI. An ex- As the operating voltage goes lower, the maxi- Get Connected ample of a poorly matched and well matched mum operating frequency of the internal PLL with companies mentioned in this article. clock signal and the resulting spectral content is reduced. This in turn limits the output fre- www.portabledesign.com/getconnected is shown in Figure 2. Note that in this example, quency and increases the long-term jitter of the 32 PORTABLE DESIGN Get Connected with companies mentioned in this article.
  • 31. portable power output clock. Long-term jitter is the measure tile memory or configured in real time through of edge uncertainty for edges spaced “n” clock the 2-pin I2C port. periods apart. A typical value for “n” is 1000, A block diagram of the SL15101 is shown in and a typical failure mode for excessive long- Figure 3. Using the methods described in this term jitter is closure of serial communication article, the product can be programmed to pro- eye diagrams (increased bit error rates) and jit- vide optimum system performance with mini- tery pixels in high-resolution graphics displays. mum power dissipation. Ideally then, the clock generator would have In summary, this article has focused on the programmable internal voltage levels so that advantages of a programmable clock genera- the voltage can be reduced to just that required tor for reducing system power by a variety of for the maximum frequency and long-term jit- methods. To control system power, use clock ter performance required by the system. start/stop in direct clock systems and frequen- And just as various portions of a system are cy skewing in clock multiplying systems. To powered down when not required, the clock control clock distribution power, use voltage generator should be capable of powering down matching to minimize signal swing and im- its unused sections independently. In fact, in pedance matching to minimize line ringing. To the lowest power operating mode, when just control clock generator power, you can trade the crystal oscillator is running, it would be off PLL frequency vs. jitter and power; inde- advantageous to control the amplitude of the pendently minimize core operating voltages; crystal oscillation waveform. Whenever crystal and control the amplitude of crystal oscillator oscillator waveform amplitude control is pro- waveforms. All of these are made substantially vided, it is important that the clock generator easier—or even possible—through the use of still provide maximum gain during power-up programmable clock generators. to ensure reliable crystal startup. Most crys- tal manufacturers recommend a “negative re- Spectra Linear, Inc. sistance” at startup of at least 5x the crystal’s Santa Clara, CA (408) 855-0555. maximum rated Equivalent Series Resistance, [www.spectralinear.com] or ESR. Programmable Clock Generators Programmable clock generators are avail- able from a variety of suppliers such as Texas Instruments, Cypress Semiconductor and Spec- traLinear. One example of a programmable clock generator that provides programmable optimization in all of the areas discussed so far is the EPro clock family from SpectraLinear. The company offers various Electrically Pro- grammable, or EPro, clock products incorpo- rating from 1 to 4 low-power PLLs with up to 2048 nonvolatile control bits. The PLLs can be programmed to consume less than 2 mA each. This product provides programmable min/max frequency, frequency slew rate, output imped- ance, rise/fall times, output drive levels, oscil- lation amplitude and internal voltage regulators as well as power-down of various sub-blocks. The program can be stored in internal nonvola- JANUARY 2008 33
  • 32. portable power designing for low power Lower Supply Voltages Enable Low-Power Portable Electronic Devices Few power management methods will help your energy budget more than dropping the supply voltage. But doing so while maintaining clock frequency and signal integrity is no easy trick. by Aditya Rao, Product Marketing Engineer, T Memory Products Division, Microchip Technology Inc. The tremendous growth in the semiconduc- An electronic device’s overall power con- tor industry over the last two decades has large- sumption can be represented by: ly been a result of the scaling of CMOS devices which, over the years, has yielded lower costs PTOT=αCTOTVDD2f +VDDIOFF; with more die per wafer, smaller feature sizes where IOFF=Ioe(-qVTH/nkT) and increased performance. However, device scaling has reached a point of threshold today, Equation 1: An Electronic Device’s Overall wherein its benefits are realized only if a de- Power Consumption vice’s power consumption can be reduced by a few orders of magnitude. Power minimiza- The first term in Equation 1 represents dy- tion is of paramount importance for design- namic or “switching” power, while the second ers today, especially in the portable electronic term represents static power—primarily due device market, where devices have become to leakage currents. (The short-circuit power, increasingly feature rich and power hungry. which forms less than 5% of the total power, Low supply voltages play a significant role in is not included.) As a result of scaling over the determining the power consumption in portable years, the dynamic power has remained almost electronic device circuits. constant (Figure 1), so increases in switching This article will examine the benefits of low frequency (α), clock frequency (f) and total ca- voltage within portable electronic designs, pacitance (CTOT) have been largely offset by the showing how the advantages of low power can supply voltage (VDD). be achieved. The paradox faced by designers is that a 34 PORTABLE DESIGN
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  • 35. portable power reduction in supply voltage helps to reduce gating (Figure 2a), which uses high threshold- power but, on the flipside, it limits the clock voltage transistors or sleep transistors in circuit frequency. Additionally, a reduction in supply blocks that switch infrequently. This results in voltage reduces the saturation current through zero standby currents during the inactive state. the MOSFET, thereby cutting speed and per- Dynamic supply-voltage scaling is another formance. Hence, the supply voltage plays an method employed that is often used in low- important role in the speed vs. power trade- power designs to efficiently tackle the power/ off. performance trade-off. The underlying prin- figure 1 To counter this reduction in saturation cur- ciple is to scale the supply voltage down along rent, threshold voltage (VTH) has also scaled non-critical timing paths, thereby lowering the Dynamic and Static Power Consumption with Technology Scaling down. This has led to a tremendous surge in overall dynamic power consumption. Howev- 100 1990 1995 2000 2005 2010 2015 2020 sub-threshold leakage current (IOFF) and static er, along timing-critical paths, the supply volt- power, especially in the deep submicron pro- age is kept at its nominal value to ensure timing 1 Dynamic Power cess technologies (Figure 1). Minimizing this closure. It must also be noted that the addition- Normalized Power is expected to be a significant challenge for fu- al voltage levels and their integration into the 0.01 ture low-power designs. Table 1 shows the ef- design increase the overall cost of the design. fect of scaling on various parameters. Modifications involve adaptive supply-voltage Today’s consumer-electronics market is scaling, based upon the sub-circuit workload. 0.0001 driven by battery-operated, wireless applica- Next, dynamic threshold-voltage scaling can Static Power tions and portable devices that are becoming be used, where the threshold voltage of cells 0.0000001 500 350 250 180 130 90 65 45 22 increasingly sophisticated. All of this has cre- is increased by controlling the substrate bias- Gate Length (nm) ated a huge demand for longer battery life. As ing. A larger threshold voltage implies reduced a result, design practices today are increasingly passive leakage, thus shrinking the static power Dynamic and Static Power Consumption with focusing on the demands and requirements of consumption. Therefore, choosing supply-volt- Technology Scaling. the end application and target markets, rather age or threshold-voltage scaling depends upon than just overall system optimization, for better whether dynamic or static power dominates the performance. In fact, to achieve this, foundries power equation. nowadays offer multiple options on threshold Architectural optimizations implemented voltage, supply voltage and oxide thickness for during the RTL and synthesis phases of the the same process, providing designers with the flexibility to choose the best device for help- figure 2 ing them overcome some of the limitations of CLK power-performance trade-offs, enabling them to tailor designs to the needs of the end appli- Latches cation. For example, portable applications that place a higher premium on power consumption are often designed using higher VTH transistors, Sleep Input L1 Logic High VTH L1 Circuit L2 Output L2 trading off performance for lower power. On Virtual VDD the other hand, fast switching circuits will use Pull-Up Network low VTH cells. (PUN) Low VTH EN There are many methods that designers can employ to reduce power consumption in por- Input Output Modifying Circuit to Enable Clock Gating table electronic devices. One is known as clock gating (Figure 2b). Clock power is an impor- Pull-Down Network CLK tant component of overall dynamic power. One (PDN) Low VTH way to reduce clock power is to use clock gat- EN Logic Circuit ing, which dynamically disables the clock in Virtual GND Clock Gating by ANDing CLK Gating Clock unused parts of the circuit. This avoids the un- Sleep High VTH Signal (Enable) and Enable Signals Logic necessary power dissipation caused by charg- Input L1 Circuit L2 Output L1 L2 ing and discharging the clock signal at these unused gates. Gating is generally achieved by Sleep = 0 => Normal Operation, Logic ON Sleep = 1 => Power Gated, Logic Turned OFF ANDing the clock signal with a clock-gate sig- nal, which rises whenever the part of the circuit that needs to be gated is active and remains low (a) Power-Gating Circuit (b) Clock Gating Reduces Static Power Reduces Dynamic Power otherwise. Many synthesis tools offer clock- gating insertions at the RTL level. (a) Power Gating using Sleep Transistors and (b) Clock Gating. Another commonly used technique is power JANUARY 2008 37
  • 36. portable power design flow are critical as key design trade- ration and allows for higher threshold voltages offs are made in this phase. Mapping and siz- for the same “on” current. This reduces static ing techniques are often used on the netlist to power. Table 2 shows the list of proposed new find the high switching inputs. These are then materials and their respective advantages. mapped to low-capacitance inputs. If possible, Signal Integrity (SI) has become a major pipelining techniques should be implemented concern today, especially in deep sub-micron to further save power. processes. Lower noise margins with supply- Scaling to the deep sub-micron level has voltage scaling have meant more stringent re- opened the door to a number of second-order strictions on the signal output and quality. This is particularly demanding with faster rise times and increased slew. SI issues creep in not only table 1 when data that is latched is incorrect, but also when data that needs to be latched doesn’t ar- Parameter Relation Full Scaling General Scaling rive at the right time. Substrate coupling, cross- W, L, tOX - 1/S 1/S talk and circuit interconnects are the primary VDD, VTH - 1/S 1/U culprits for SI problems. Some tips and tricks for overcoming these SI Area WL 1/S 2 1/S2 problems include: COX 1/tOX S S • Use differential signals at high fanout nodes. CL COXWL 1/S 1/S • Use ECL signals for clocking. IDSAT COX(W/L)V2 1/S S/U2 • Use parasitic extraction tools that model 3D parasitics and inductance, especially in Intrinsic Delay (tP) CLV2/IDSAT 1/S U/S2 high-frequency designs. This increases the Avg. Power (PAV) CLV /tP 2 1/S 2 S/U3 accuracy of the slew-rate prediction. Power Delay Product CLV2 1/S3 1/SU2 • Model capacitors as nodal capacitors, as opposed to capacitors to ground. Full Scaling = Dimension and voltage scales by a factor “S” (S>0) • Match impedance at the package boundary. General Scaling = Dimension and voltage scales with different factors. • Use decoupling capacitors between the supply voltage and ground at the external The Impact of Scaling on Device Parameters. pins. • Limiting di/dt helps reduce crosstalk and effects, such as tunneling, channel-length modu- ground bounce. lation, punch through, drain-induced barrier low- • Optimize layout for fewer metal layers and ering and velocity saturation. All of these effects minimum wire length. further impact both power consumption and • Give greater margins during design to al- performance, making designs increasingly com- low for costly post-silicon SI defects. plicated and causing a growing need for newer, more innovative materials and processes. For Non-Volatile Memory Technologies example, the use of High-K dielectrics helps The non-volatile memory market, consist- mitigate the effects of tunneling with thicker ing primarily of flash and serial EEPROM, is gate oxides. Strained-Si helps improve mobil- one of the fastest growing in the semiconduc- ity, which mitigates the effects of velocity satu- tor industry. EEPROM devices are particularly useful in portable and consumer-electronic ap- table 2 plications, providing system programmability and data storage. They also find applications in Device Material power-down storage, error diagnostics, secure Effect From í To data storage, maintenance logs and configura- AI í CU Reduces Interconnect Delay Time tion storage, and often as look-up tables and analog controls in consumer-electronic appli- SiO2 í Low-K Reduces Interconnect Delay Time cations. What makes serial EEPROM attractive Si í Silicon On Insulator (SOI) Lower Capacitance, no latch up is its high endurance, low cost, byte-level pro- Si í Strained Si Higher Mobility grammability and low power. These attributes make it ideal for portable consumer-electronic Poly-Si í Metal Gate Higher Effective Oxide Capacitance applications, such as MP3 players, camcorders SiO2 í High-K Reduced Oxide Leakage Currents and wireless Bluetooth applications (Table 3). Serial EEPROM devices are becoming in- New device materials and their advantages. creasingly power savvy. Leading providers of 38 PORTABLE DESIGN
  • 37. portable power EEPROM devices today specify EEPROM de- tremely low, making current sensing challeng- vices with typical standby currents of around ing and slow. Boosting the voltage on the word 0.01 micro Amperes (μA). In fact, newer serial line to obtain higher on currents is one way to EEPROM parts effectively tackle the speed- work around this problem. power trade-offs as well. For example, the 1 On the other side of the spectrum, scaling Mbit 25AA1024 or 25LC1024 (25XX1024) has helped reduce the cost per bit, with reduced serial EEPROM devices from Microchip Tech- die sizes and cost. It has also helped reduce nology are not only the fastest (20 MHz) 1 power consumption, and has made these devic- Mbit SPI serial EEPROMs available, but they es significantly faster with every generation of also have a deep power-down mode feature that scaling. Today, low supply-voltage operation helps to reduce power consumption. These ad- is inevitable. The conundrum facing designers ditional low-power features make these devices with serial EEPROMs is that having low power well suited for low-power designs up to around is useful in applications such as smart cards the 1 Mbit density level. (Serial flash memory and DRAM modules. However, higher per- devices typically have standby currents around formance and faster access times are required 15 μA at this high-end density.) when used with embedded applications and microcontrollers. Going forward, supply-volt- Floating-Gate Design Challenges age limitations with smaller gate lengths are Portable applications, with their scaling of expected to lead to smaller EEPROM supply- other onboard chip components, have forced voltage ranges. serial EEPROM devices to operate over a wide Using lower supply voltages to help reduce voltage range, typically 1.8V to 5.5V. The real dynamic power is inevitable with scaling. How- challenge is to ensure fast access and erase ever, the resulting increased static power is ex- table 3 times, along with reduced write times at low pected to pose the biggest challenge for low- supply voltages, while reducing power con- power portable designs in the future. To offset Application Software, Data Memory, Program Storage, sumption at higher supply voltages. An addi- the slowdown in scaling, newer, more innova- 1 Mbits Printers, Scanners, Smart Configuration Storage, Maintenance Logs tional critical design consideration is to ensure tive materials like Silicon-on-Insulator (SOI) 512 Kbits Cards, GPS, Remote Control, Energy Meters, that standby current is as low as possible, espe- are being used to make devices more robust. 256 Kbits Hearing Aid, Wireless, VoIP Last Number Call, Data cially in battery-operated devices. Additionally, advanced packing technology is 128 Kbits Setting, Log Data, Secure Data Storage, Error One great advantage of non-volatile memory is quickly integrating into designs, with flip-chip 64 Kbits Cell Phones, Cordless Phones, Digital TV, HDCP, Diagnostics, System Settings that a flash or serial EEPROM device’s power technology becoming increasingly popular. 32 Kbits Facsimile, Set Top Box, Digital Camera, PDAs, supply can be shut down to ensure zero mem- More sophisticated testing methodologies and 16 Kbits Bluetooth Headsets User Setting, Initial Channel 8 Kbits ory leakage when not in use. When operating EDA tools are helping designers to model sys- Setting, Fine-tuning, Usage DVD, MP3, VCR, CD, Record, Initial Data Settings, 4 Kbits at lower supply voltages, write times in these tems better, thereby reducing turnaround times Home Appliances, Configuration Settings 2 Kbits Car Alarm Systems, devices increase dramatically. Hence, charge- and costs. 1 Kbits DDR DIMM Modules, LCD Monitors pump designs are critical in obtaining write- Thus, while scaling may not keep the same time optimizations. The big challenge here is pace going forward, better systems, improved Application and usage of Serial EEPROM devices, by density. to obtain the highest internally generated write tools, increased use of software and architectur- voltage at the lowest possible supply voltage, al optimizations, newer materials and improved to ensure faster write times. processes can bring the benefits of lower cost, Another significant challenge associated increased performance and lower power. with technology scaling in floating-gate de- signs has to do with thinner oxides, resulting Microchip Technology, Inc. in poor write quality. This causes lower endur- Chandler, AZ. (480) 792-7200. ance and severely affects data retention. Also, [www.microcip.com writes are generally performed at high voltages (greater than ± 10V) making the thinner gate oxides more vulnerable to permanent oxide damage and charge loss. This severely affects reliability. Using materials with high dielectric con- stants for the oxide is one way to reduce the impact of dielectric scaling. To optimize the time taken to read from floating-gate non-vola- tile memories, the address decoding times must be optimized. The real challenge here is that at low supply voltages, the on currents are ex- JANUARY 2008 39
  • 38. product feature power consumption in a single device. The term Altera Zeros Out Power, Zeros “zero power” originated with Phillips back when in on Portable Designs static power was in the mA range; zero power came to mean anything in the μA region. Altera MAX IIZ CPLD combines 29 μA static claims the MAX IIZ is zero powe’ based on the power, instant-on performance in a EPM240Z’s 29 μA static power while running at 50 MHz; dynamic power in that case is 8.9 5x5 mm package. mA. With a density about half way between the CoolRunner-II XC2C128 (128 macrocells) figure 1 by John Donovan – Editor-in-Chief and XC2C256, at 50 MHz the IIZ’s dynamic current (Icc) is about half (8.9 vs. 18 mA), while The money play in consumer electronics is the static current (0 MHz, 25°C) is somewhat cell phones, and few chip vendors can make higher (29 vs. 20 μA). The flash-based FPGA a stronger pitch for sockets than the program- camp will protest that this isn’t zero power, but mable logic camp—quick time-to-market, lower it’s a close enough approximation for all but the BOM cost, the ultimate in flexibility to accommo- most demanding medical applications. As for date evolving protocols, different regional stan- which chip makes the most sense in a given ap- dards and even over-the-air software updates of plication, all things being equal it will vary with hardware. What’s not to like? the usage model, but in this comparison the The problem, of course, is that traditionally MAX IIZ would most often have the edge. FPGAs—SRAM-based FPGAs in particular—have In terms of density, Denny Steele, Altera’s been too power hungry for handsets, and senior marketing manager for Low Cost Prod- the low density of CPLDs has limited them ucts, claims that the MAX IIZ offers 6x the den- to glue logic chores. As CPLD densities have sity and 3x the I/Os in the same package size risen, some of these chores have gotten quite as traditional macrocell-based CPLDs. This de- sophisticated, with CPLDs handling system-level rives from the use of MBGA packaging instead power management as well as communication of the micro-leadframe QFN favored by Xilinx between the main processor and peripherals. and Lattice. In a 5x5 QFN you can expect to get Altera designed its new MAX IIZ family specifi- 20-21 I/Os and 32 macrocells, whereas the cally to address the power, package and price EPM240Z provides 80 I/Os and 192 macrocells constraints of the portable applications market. in the same size package. More horsepower They made some major modifications to the and more functionality while using less power in MAX II’s look-up table (LUT) architecture with the same piece of board real estate is a pretty an eye to low-power embedded applications, compelling argument. combining low power and instant-on capability MAX IIZ devices are supported by free in a 5mm x 5mm micro-BGA (MBGA) package. Quartus II Web Edition software version 7.2, The MAX IIZ initially comes in two densities: SP1, which integrates with all leading third-party synthesis and simulation tools. Production-qualified MAX IIZ EPM240Z M68 figure 2 devices will begin shipping in the first quarter of 2008 at $1.25 in high volumes. All MAX IIZ devices will be shipping in production by the second quarter of 2008. Additionally, over 20 MAX IIZ design examples, enabling designers to quickly and cost-effectively create and custom- ize their designs, are available at www.altera. com/max2example. The MAX IIZ demo board will be available by the second quarter of 2008. Xilinx’ highly successful CoolRunner line has long been the obvious choice for handling com- munication between cell phone processors and their peripherals. Actel, Lattice and QuickLogic have all designed products to capture those sockets, but so far with limited success. With the advent of the MAX IIZ, Altera has picked up—or perhaps thrown down—the gauntlet. The MAX IIZ is a worthy competitor and well deserving of being Portable Design’s product of the EPM240Z has 240 logic elements, 192 the month. macrocells, 80 I/O pins and 8K of user flash Altera Corporation, memory; the EPM570Z has 570 logic elements, San Jose, CA. 440 macrocells, 160 I/O pins and the same 8K (408) 544-7000. of flash. Both include an internal oscillator. [www.altera.com]. The real story here is power consumption and density. The devices utilize a 0.18-micron process, 1.8V core voltage and 6-metal-layer flash to provide both high functionality and zero 40 PORTABLE DESIGN
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  • 40. design idea Flexible Over/Undervoltage Detector Monitors Negative and Positive Voltage figure 3 by Franco Contadini and Bich Pham, Maxim Integrated Products Inc. Multi-voltage supply supervisors (such as the MAX6887) provide several voltage-detector inputs for positive voltages, each with factory-set thresholds for undervoltage and overvoltage. The /RESET output asserts when any input drops below its undervoltage threshold, or when you assert the manual reset (MR). The /OV output asserts when any input exceeds its overvoltage threshold. These capabilities are useful, but tele- com applications often require that you monitor a negative supply voltage for the RF circuitry as well. figure 1 figure 2 -6V By combining the circuits of Figures 1 and 2, one pair of terminals R1 REF warns of under or overvoltage for multiple positive voltages and IN_ one negative voltage. MAXIM R1 MAX6764 R2 UVH + UV figure 4 + REF *VREFUV - UV UV1H MONITOR GND R2 Internal VCC Reference CH1-0V 0.5V CH1=VM OV1H + OV OVH - OV REF1=UVIN + MONITOR *VREFOV R3 REF1/CH2-0V CH2=UV VH *VREFOV and VREFUV are referenced to 0.6V according to the device’s tolerance. CH3=OVIN This IC (in SOT23 package) is a CH4=OV simple window comparator that CH3/CH4 - 0V MAX6887 adjustable input option. monitors a supply voltage with separate under/overvoltage outputs. These waveforms illustrate operation of the Figure 3 circuit. To monitor negative voltage you can make use of the MAX6887 adjust- able-input option (Figure 1), in which a level-shifting circuit connects one side of the resistive divider to a positive level and the other side to the Operation of the Figure 3 circuit is illustrated in the scope shot of Fig- negative voltage. This approach, however, produces inverted output logic. ure 4, in which the yellow trace (CH1) represents the monitored negative If, for example, you monitor -6V with thresholds at -6.5V and -5.5V, the voltage VM as it ranges from 0V to -7V. Other traces are: circuit asserts /UV when VIN = -6.5V and /OV when VIN = -5.5V. R1 (black) = UVIN The circuit of Figure 2 overcomes this limitation by adding a simple win- CH2 (blue) = MAX6764 /UV dow-detector IC (Figure 3) to monitor the negative supply. The detector’s CH3 (green) = OVIN /UV output connects to the multi-voltage supervisor’s /OV output, and CH4 (pink) = MAX6764 /OV. the detector’s /OV output connects to the supervisor’s /RESET output. The nominal value for the monitored negative voltage is -6V. Both /OV Thus, the /RESET output goes low when the negative voltage decreases and /UV outputs have a 10 kΩ pullup to 5V, and the VCC terminals of to -5.5V, and the /OV output asserts low when the negative voltage in- both ICs connect to a 5V supply. The MAX6764 Output /UV (MAX6887 creases to -6.5V. Three resistors (R1-R3) set the under- and over-voltage /OV Output) goes low at VM = -6.55V (and goes high at VM = -6.52V). thresholds UV and OV. R1 connects to a positive reference voltage, and The MAX6764 output /OV (MAX6887 /RESET Output) goes low at VM = R3 connects to the monitored negative voltage. -5.53V (and goes high at VM = -5.55V). If your system doesn’t include a positive reference voltage, you can use the supervisor’s 2.55V BP output. To maximize DC accuracy, the sum of R1+R2+R3 should draw only a few microamps from the BP output. Us- ing the principle of superposition, you can then calculate the voltages at UVIN and OVIN for any given set of resistor values as follows: VUVIN = V × BP ( R 2 + R3 R1 + R 2 + R3 ) − VM × ( R1 R1 + R 2 + R3 ) , VOVIN = V × BP ( R3 R1 + R 2 + R3 ) − VM × ( R1 + R 2 R1 + R 2 + R3 ) , where VM is the monitored negative supply voltage. 42 PORTABLE DESIGN
  • 42. products for designers Direct Digital Synthesis IC for Low-Power, Portable Designs Analog Devices, Inc. is expanding the applicability of its industry-leading direct digital synthesis technology into battery-powered industrial, communications and defense electronics applications with the introduction of a complete low-power, low-cost Direct Digital Synthesizer (DDS) specifically designed for wireless, handheld equipment. Unlike competing approaches used to synthesize a digitally controlled frequency, the AD9913 is the first DDS device to deliver a 250 MHz clock rate while consuming as little as 50 mW of power. At less than $5 in volume quantities and available in a compact chip-scale package, the new IC is ideally suited for portable barcode scanners, radar detectors, remote radio controls and other products that require a cost-effective combination of performance and low-power operation. Unlike phase-locked loop (PLL) devices, which suffer from settling times measured in microseconds and fine-tuning limitations, the AD9913 settles in nanoseconds with granularity well below 10 mHz. Other approaches, including field-programmable gate arrays (FPGAs) with embedded DDS functions, have difficulty matching the AD9913’s greater than 80 dB spurious-free dynamic range (SFDR) performance on a 100 MHz output signal while requiring higher operating power and the addition of a discrete digital-to-analog converter (DAC) to synthesize the sine wave. The AD9913 includes an on-chip 10-bit high-speed DAC with no price premium compared to a stand-alone DAC. The fine-tuning granularity and higher SFDR of the AD9913 allow it to more quickly and accurately generate a stable signal in the band of interest. In a remote radio-controlled application, for example, such as an unmanned aircraft, this means the operator is less likely to lose contact with the airplane due to frequency interference that can result in a dropped signal. The AD9913 is available in full production quantities. The AD9913 costs $4.65 per unit in 100,000-unit quantities and is available in a 32-lead LFCSP (lead-frame chip-scale package). Analog Devices, Norwood, MA. (781) 329-4700. [www.analog.com]. Li-Ion/Li-Polymer Chargers with Auto USB or AC Ultra-Low-Power Power-Source Selection Microcontroller Microchip Technology Inc. Texas Instruments has an- has announced sampling of the nounced the availability of five MCP73837 and MCP73838 new families of MSP430F2xx (MCP73837/8) dual-input, high-performance microcon- high-current Li-Ion/Polymer trollers, the industry’s lowest- charge-management control- power 16-bit general-purpose lers with automatic USB or AC microcontrollers (MCUs). The adapter power-source selec- new microcontrollers provide a tion. The single-cell, fully inte- direct upgrade path for corre- grated chargers enable charge sponding devices in TI’s popular currents of up to 1A from an MSP430F1xx generation of ultra-low-power MCUs, easing development and AC power source, plus charging offering complete software and pin compatibility while delivering twice the currents of up to 100 mA or performance, twice the battery life and increased memory. MSP430F2xx 500 mA from a USB port. They have several on-chip safety features, and MCUs enable developers of meters, sensors, industrial control systems, are available in 10-pin MSOP and 3 mm x 3 mm DFN packages, to enable handheld instruments and a host of other embedded systems to extend the smaller, faster and safer battery-charger designs. performance and lifetime of their products with minimal redesign (see www. Auto power-source selection from either a USB port or AC adapter ti.com/msp430f2xx-pr for more information). means that MCP73837/8-based charger designs can automatically With a high level of analog integration, TI’s MSP430F2xx MCU architecture charge from a PC’s USB port when no AC power is available. When is designed for the requirements of a new generation of control systems. powered from a USB port, the devices ensure compliance with USB power The devices integrate on-chip memories of up to 120 Kbytes, and a 20-bit specifications and adjust outputs accordingly. The result is that one char- address word increases total addressable memory to 1 Mbyte without pag- ger design can support multiple power sources. Additionally, with high ing, supporting the development of more complex programs. A wide range charge currents up to 1A from an AC power source, the MCP73837/8 of analog and digital peripheral options enable enhanced features in end devices enable faster charging cycles and less recharging down time. products while reducing system costs and power consumption. For example, On-chip safety features, such as thermal regulation, cell-temperature almost no battery drain occurs with standby power consumption as low as monitoring and charge-timers minimize charger-related system damage, 0.5 μA, and fast wake up from standby mode further reduces battery load. resulting in safer and more efficient charger designs. The MCUs have a wide operating voltage range of 1.8 to 3.6 volts and a flex- Microchip also announced the MCP73837/8 evaluation board, (Part ible clocking architecture that allows the designer to implement their select # MCP7383XEV-DIBC), to help designers evaluate the MCP73837/8 processing speed versus operating voltage. Battery life and system cost are chargers in their designs. The board can be ordered now at www.micro- further optimized by achieving the full processor speed of 16 MHz, at 3.3V, chipdirect.com, and is expected to ship in late December. It is priced at giving margin for the power supply design requirements. $40 each. With up to 120 Kbytes of flash and 8 Kbytes of RAM, the MSP430F241x Samples of the MCP73837/8 chargers are immediately available and MSP430F261x are targeted for systems needing extensive processing in 10-pin MSOP and 3 mm x 3 mm DFN packages, for $0.89 each in capability, while the MSP430F24x and MSP430F23x are more general-pur- 10,000-unit quantities. pose devices. Among the devices, the MSP430F2418 and MSP430F2618 are optimized for operation in low-power ZigBee networks, while the Microchip Technology Inc., Chandler, AZ. MSP430F2410 targets applications such as IEEE 802.15.4 wireless net- (480) 792-7200. [www.microchip.com]. works and automatic meter reading. All five families are available now in volume quantities. Evaluation tools are also available now for all devices. Texas Instruments Inc., Dallas, TX. (800) 336-5236. [www.ti.com]. 44 PORTABLE DESIGN
  • 43. products for designers Firewall Technology for M2M Applications High-Performance Clock Connect One Generators has developed ON Semiconductor has an- SecureGAP, a cost- nounced the expansion of its effective, firewall- PureEdge high-performance clock on-a-chip solution generation portfolio with the intro- that allows M2M duction of two best-in-class devices, devices to be safely the NB3N3002 and NB3N5573. connected directly The NB3N3002 and NB3N5573 to the public Inter- are 3.3 volt clock generators that net. SecureGAP create selectable Host Clock Signal safeguards vital Levels (HCSL) and sub-picosecond proprietary informa- (ps) jitter quality clocks at 25 MHz, tion for application 100 MHz, 125 MHz and 200 MHz. owners through These devices are ideal for PCI Express, Gigabit Ethernet and FBDIMM ap- security and data segregation, which serves as a gatekeeper and natural plications. The PureEdge architecture provides increased design flexibility firewall between the host processor and the Internet as well as signifi- and reduces system cost compared to standard crystal oscillators and cantly cutting connectivity costs and simplifying deployment. This technol- competitive silicon-based clock generation devices. ogy has been introduced in the CO2128, Connect One’s newest and The NB3N3002 generates one differential HCSL output clock, while lowest cost IP controller that provides Internet connectivity, encryption the NB3N5573 delivers dual output. Employing advanced 0.25 micron and superior security for a host processor or device. The CO2128 powers (um) CMOS technology, the devices significantly outperform competitive Connect One’s entire range of modules and device servers. devices with phase noise comparable to expensive Surface Acoustic The CO2128 works as a coprocessor, offloading all security and com- Wave (SAW) crystal oscillators. These devices generate high-quality clocks munication aspects from the main processor. As a firewall between the from a low-cost 25 MHz crystal with four selectable output frequencies host processor and the Internet, SecureGAP prevents intruders from and integrated 1:2 fanout buffer (NB3N5573). The device provides phase tapping directly into the host processor’s data. By maintaining a physical noise of -130 decibels relative to the carrier per hertz (dBc/Hz) at 100 barrier between the public Internet and the application as well as encrypt- KHz offset from the carrier frequency. ing data using SSL3, the CO2128 makes it completely safe to transfer Like all of ON Semiconductor’s PureEdge devices, these new clock data to and from any host processor over the Internet via 802.11b/g Wi- generators free up more of the system designer’s precious timing budget Fi, 10/100 BasedT LAN, GPRS, or dial-up connection. Architecturally de- and offer true design flexibility. Silicon-based clock generation ICs, such signed into the CO2128 as an offload engine, SecureGAP serves as the as the NB3N3002 and NB3N5573, are inherently simpler to manufacture most trustworthy and reliable option for secure and efficient connectivity, than expensive crystal oscillators. This results in lower overall system and is technically superior to software firewalls installed on the host CPU. costs and vastly shorter lead times. The NB3N5573 is a pin-compatible CO2128 supports LAN, Wi-Fi and all types of dial-up/wireless modems drop in replacement for the competitive function device ICS557-3. The (AMPS, CDMA, CDMA2000, CDPD, GPRS, GSM, IDEN and TDMA cel- NB3N5573 provides much better jitter performance and was implement- lular protocols). It includes a full secure TCP/IP stack, plus upper layer ed without the Spread Spectrum feature making it a better value where protocols like SMTP, POP3, MIME, HTTP, WAP, FTP ,TELNET and SerialNet SSM is not required. mode for serial-to-IP bridging. It also includes a Web server with two web- Offered in a 5.0 mm x 4.4 mm lead-free (Pb-free) TSSOP-16 package, sites: one for the application and one for configuring iChipSec CO2128. the NB3N3002 and NB3N5573 are budgetary priced at $1.80 per unit in The CO2128 operates at an industrial temperature range of -40° to 2,500 unit quantities. 85°C (-40° to 185°F) and is RoHS compliant. ON Semiconductor, Phoenix, AZ. Connect One Semiconductors, San Jose, CA. (602) 244 6600. [www.onsemi.com]. (408) 572-5675. [www.connectone.com]. Peripheral Controller with MLC NAND Flash Support Cypress Semiconductor Corp. has introduced a new West Bridge peripheral controller with Multi-Level Cell (MLC) NAND Flash support that enables designers to use lowest-cost, highest-density flash storage. The West Bridge Astoria controller supports up to 16 MLC NAND Flash devices, which cost approximately three times less than Single-Level Cell (SLC) NAND Flash devices for the same storage density. By fully offloading management of USB and storage from an embedded processor, the West Bridge Astoria peripheral controller saves critical processor resources and maximizes data-transfer performance. The controller marks the debut of Cypress’s fast-interleaving N-Xpress MLC NAND Flash control technol- ogy, with static wear-leveling, bad block management and 4-bit ECC (Error Correction Coding) to support up to 16 SLC/MLC NAND devices. The storage port can be configured so designers can select up to two SDIO devices such as Bluetooth, Wi-Fi, GPS and SD cards, making Astoria ideal for applications such as data cards and dongles. Astoria also supports other types of storage from a list that includes Secure Digital High Capacity (SDHC) v. 2.0, MultiMedia Card+ (MMC+) v. 4.2 cards, CE-ATA for HDD, as well as various types of controlled NAND. The flexible processor interface enables connection to most embedded processors adding a selection of Asynchronous SRAM, ADMUX (Address Data Multiplexing), SPI (Serial Peripheral Interface) and NAND interfaces to the Pseudo-CRAM interface of Antioch. The West Bridge Astoria controller features up to 27 programmable GPIOs and 16 USB endpoints. It comes in a small 100-ball VFBGA (Very Fine Ball Grid Array) package that measures only 6 mm x 6 mm and 0.5-mm pitch. Additionally, Astoria supports standard handset frequencies such as 19.2 MHz and 26 MHz for clock input, removing the need for an additional crystal. Cypress Semiconductor, San Jose, CA. (408) 943-2600. [www.cypress.com]. JANUARY 2008 45
  • 44. products for designers Eval Board Demonstrates Extended Battery Life for Portable Designs Actel Corporation has announced the new Icicle Kit evaluation board for the company’s 5 μW IGLOO FPGA. The kit showcases the ultra-low-power attributes, flexible implementation options and battery-saving advantages of IGLOO for portable applications. The $99 kit allows designers to easily and rapidly program, evaluate and modify their low-power IGLOO-based portable designs. Powered by a rechargeable lithium-ion battery, the 1.4” x 3.6” Icicle evaluation board consumes less than one-seventh the power of competitive FPGA development solutions in a design the size of a small cell phone. The Icicle board is an environmentally friendly, RoHS-compliant solution that integrates a nonvolatile, 125,000-gate AGL125 IGLOO FPGA. The board includes the built-in, rechargeable lithium-ion battery, USB-to-UART interfaces and power management circuits. In addition to the Icicle evaluation board, the kit includes a sophisticated programming stick for extended programming functionality. Also offered is a free, unlimited-use license for the Actel Libero Integrated Design Environment (IDE) Gold edition. This enables designers using the Icicle Kit to take advantage of the advanced power analysis tools recently intro- duced with Actel’s Libero IDE v8.1 to identify key sources of power in their designs. Other kit elements include user’s guide and tutorial, printed circuit board (PCB) schematics, layout and sample design. The Icicle Kit is available immediately from Actel for $99. Actel Corporation, Mountain View, CA. (650) 318-4200. [www.actel.com]. MicroPower Hall-Effect Switch with Complementary Ultra-Small Solid-State Drive for Handheld Devices Push-Pull Outputs Intel Corporation announced its latest entry into the solid-state drive Allegro Microsystems has introduced a new ultra-sensitive, Hall-effect market with the Intel Z-P140 PATA Solid-State Drive (SSD), one of the switch with latched digital outputs and either unipolar or omnipolar actua- tiniest in the industry aimed at handheld mobile devices. Smaller than a tion. It features operation at low supply currents and voltages, making it penny and weighing less than a drop of water, these 2 Gbyte and 4 Gbyte ideal for battery-operated ultra-small devices are fast, low power and rugged, with the right size, electronics. Key features capacity and performance for mobile Internet devices, digital entertain- such as: lower minimum ment and embedded products. Vcc, a small, low-profile SSDs use flash memory to store operating systems and computing package and push-pull data, emulating hard drives. The Intel Z-P140 PATA SSD has an industry complementary outputs, standard parallel ATA (PATA) interface and is optimized to enhance Intel- all serve to satisfy pres- based computers, and will be an optional part of Intel’s Menlow platform ent and future trends for mobile Internet devices debuting in 2008. in battery-operated The Intel Z-P140 is the small- consumer products. This est SSD in its class, making new device is targeted it attractive to designers and at the consumer and manufacturers of mobile and industrial markets. ultra-mobile devices. Compara- The low operating tively, the Intel Z-P140 is 400 supply voltage, 1.65V to times smaller in volume than a 3.5V, and unique clock- 1.8-inch hard disk drive (HDD), ing algorithm assist in reducing the average operating power consump- and at .6 grams is 75 times lighter. It is also a much more durable alter- tion. For example, the power requirements are less than 15 μW with native to HDDs. The 2 Gbyte and 4 Gbyte capacities are large enough to a 2.75V supply. Unlike some traditional Hall-effect switches, Allegro’s store mobile operating systems, applications and data such as music or A1171 allows the user to configure how the device is magnetically actu- photos. It is extendable to 16 Gbytes for added storage capacity. ated. Under default conditions the device will activate output switching The Intel Z-P140 PATA SSD offers read speeds of 40 Mbytes/s and with either a north or south polarity magnetic field of sufficient strength. write speeds of 30 Mbytes/s. Critical to mobile applications, its active In the EW, 6-pin, microleaded package, the polarity specific actua- power usage is 300 mW and only 1.1 mW in sleep mode, which helps to tion can be set by the user via an external selection pin to operate in a extend a device’s battery life. unipolar mode, switching only on a north or south polarity field. Lastly, the With a 2.5 million hour mean time between failures (MTBF) rate, this A1171 has two push-pull output structures, which source and sink cur- PATA-based chip scale package delivers reliable solid-state performance rent to eliminate the need for external pull-up resistors. This polarity-inde- in an extremely tiny footprint. The Intel Z-P140 is currently sampling with pendence, as well as the minimal power requirements, allows the A1171 mass production scheduled in the first quarter of 2008. The 4 Gbyte ver- to easily replace reed switches, providing superior reliability and ease of sion will follow the 2 Gbyte product. manufacturing while eliminating the requirement for signal conditioning. Intel Corporation, Santa Clara, CA. Allegro’s A1171 is currently available in the EW (2 mm x 1.5 mm x 0.4 (408) 765-8080. [www.intel.com]. mm DFN) package. The A1171 is priced at $0.38 in quantities of 1,000 and has a 10-12 week typical lead time to market. Allegro MicroSystems, Inc., Worcester, MA. (508) 853-5000. [www.allegromicro.com]. 46 PORTABLE DESIGN
  • 45. products for designers Integrated Real-Time Trace Support for Xtensa and Smallest Color SVGA Display Diamond Cores Kopin Corporation has announced the Tensilica has smallest color SVGA display (800 x 600 res- added an optional olution) in the LCD industry. The CyberDis- full-speed, non-in- play SVGA LVS microdisplay has the same trusive instruction size (0.44” diagonal) as Kopin’s current trace capability to CyberDisplay VGA display (640 x 480 resolu- all of its Diamond tion), allowing it to utilize the same optics Standard and and housing developed for the VGA display. Xtensa configu- This new display is the culmination of Kopin’s development program to rable processor shrink the full-color pixel size to 11.25 μm square. The CyberDisplay cores. Tensilica’s SVGA LVS display exhibits remarkably sharp color images. TRAX-PC proces- Kopin combined smaller pixel transistors and the planar multi-metal sor trace capture layer process offered by 8-inch Si IC processing with an enhanced nano- macrocell is Nexus technology process for its liquid crystal alignment and a precision cell-gap 5001 compatible liquid crystal assembly process. and ideal for de- Kopin’s CyberDisplays are transmissive LCD displays with the same bugging complex, architecture as LCD flat-panel TVs, but with ultra-high pixel densities. The challenging real-time applications such as engine and motor control. new 0.44” CyberDisplay SVGA LVS display is targeted for PC and HD- Software control and use of the on-chip TRAX hardware is fully integrated related video eyewear applications. CyberDisplay SVGA LVS samples are into Tensilica’s Xplorer integrated design environment (IDE) so software available to select customers for evaluation and design-in. engineers can easily develop and debug programs while using the TRAX- Kopin Corporation, Taunton, MA. PC trace macrocell. (508) 824-6696. [www.kopin.com]. Tensilica’s TRAX-PC processor trace capture block is an optional item for use with all Tensilica Diamond Standard and Xtensa processors. It provides tracing information through an SoC’s JTAG debug port without requiring added device pins. It helps designers trace all changes in program flow (“PC” means “program counter”) including exceptions and interrupts. The trace block uses a circular on-chip trace buffer with user- defined sizing to capture the trace stream and accepts PC-based triggers and external trigger inputs. Tensilica’s associated software tools convert the compressed trace into an annotated program disassembly for easy debugging. These tools are fully integrated into Tensilica’s world-class Eclipse-based, Xtensa Xplorer integrated design environment (IDE). The Xplorer IDE provides a powerful visualization and debugging environment to both develop and debug programs using the TRAX-PC trace macrocell. The TRAX-PC processor trade capture macrocell is available now for use with all current Tensilica processor products. Tensilica Inc., Santa Clara, .CA (408) 986-8000. [www.tensilica.com]. Ultra-Low-Noise, High-PSRR, LDO Linear Regulators Maxim Integrated Products has introduced the MAX8902A/MAX8902B, the industry’s smallest 500 mA, low-noise, low-dropout (LDO) linear regulators. Packaged in a tiny, 2 mm x 2 mm TDFN, these devices provide up to 92 dB PSRR (at 5 kHz), 16 microVrms output noise, and a low, 100 mV (max) dropout volt- age at full load (500 mA). The MAX8902A/MAX8902B are ideal for noise-sensitive and space-constrained applications, such as smartphones, PDAs, PMP/MP3 players, GPS devices and ultra-mobile/notebook PCs. The MAX8902A/MAX8902B offer ±1.5% output-voltage accuracy and a wide, 1.7V to 5.5V input-voltage range. The MAX8902A features preset pin-selectable output voltages between 1.5V and 4.7V, and the MAX8902B allows users to adjust the output voltage between 0.6V and 5.3V using two external resistors. To maximize battery life, these devices consume a low, 80 microamp operating current and less than 1 microamp shutdown current. Other features include a programmable soft-start circuit to prevent high inrush currents, short-circuit protection, reverse-current protection and thermal shutdown. Available in a thermally enhanced, 2 mm x 2 mm, 8-pin TDFN package, the MAX8902A/MAX8902B are fully specified over the -40° to +125°C automotive temperature range. Prices start at $1.25 (1000-up, FOB USA). Maxim Integrated Products, Inc., Sunnyvale, CA. (408) 737-7600. [www.maxim-ic.com]. JANUARY 2008 47
  • 46. ceo interview analog CMOS. So Maxim has worked more on Ray Zinn the portable side, since CMOS tends to favor low- power operation. At Micrel we have both CMOS and bipolar, so we cover the gamut. Micrel A lot of the power management products we’ve developed are aimed at the handset market. We got involved early on with Qualcomm, and as a result we started developing cell phone products. january 2008 Samsung and LG turned out to be good customers for us because they were also CDMA. We wound up becoming the king of LDOs (low drop-out regulators); at the time they wouldn’t even allow a switcher in a cell phone because they made too much noise. We still produce more varieties and types of LDOs than anyone in the world. Now we’re getting more into switchers because we have to increase efficiency. Last year we introduced a family of “SuperLNRs” (Low Noise Regulators) that feature the advantages and ease of use of LDOs with low noise, high PSRR (power supply rejection ratio) and ultra-fast transient performance. They have the efficiency of a switcher but the simplicity and ease of use of an LDO. We’re also trying to produce an LDO with the world’s lowest output voltage; we’re currently at around With over 5000 catalog products, Micrel offers a broad range of 1.3V, trying to get down to 1V. high-performance analog, mixed signal and digital ICs that address Then we came out with another product called Hyper Light Load, high-growth markets including cellular telephones, portable electronics, which is a portable product. The problem you have with normal sleep set-top boxes, desktop and notebook computers, networking and commu- mode is the time required to wake the product up. With Hyper Light nications. The majority of the company’s revenue is derived from power Load we can wake a switcher up quickly from sleep mode and still have management standard products that largely target portable designs. good transient response. Ray Zinn is a cofounder of Micrel and has been its President, Chief Without technology that can operate below 0.7V—and as low as Executive Officer and Chairman of its Board of Directors since the com- 0.2V—we can’t be in 65 nm designs. The challenge we face in portable pany’s inception in 1978. Like many of Silicon Valley’s founders, Ray power management is to be able to work efficiently from high input volt- began his career at Fairchild Semiconductor. In those days you couldn’t ages and still deliver very low output voltages. As you lower the output just call up Applied Materials if you needed tools, you had to make them voltage the accuracy becomes critical; at 0.7V, 5% accuracy is only a few yourself. Ray invented the wafer stepper in 1974, a basic technology that millivolts. Also, switchers become rather noisy at 0.7V; a typical switch- has been in use ever since. That process orientation and drive to invent er running at minimal capacity can easily generate over 10 mV of ripple. new technologies has been a constant at Micrel ever since. Now you’ve already used up a third of your noise margin for the entire system. This is the advantage of having our own fab—we can look ahead Portable Design: Micrel produces a wide range of power to see where we need to go and develop the processes to get there. management ICs. This is a hot market with a number of large players. How do you position your products vs. Portable Design: Micrel is spending money on wafer those of your competitors? fabrication facilities in San Jose at a time when a lot of Zinn: Micrel is differentiating itself in parametric performance and companies are going “fab lite” or even fabless, relying process technology. Our products offer small solution sizes, high effi- on Asian foundries for their silicon. What is your thinking ciency, low noise and excellent transient performance. behind this investment? In terms of technologies, we’re kind of a marriage between LTC and Zinn: We feel that having our own fab gives us a competitive advan- Maxim. LTC uses a low-cost process and then puts a lot of effort into tage in terms of process technology differentiation, design and manufac- design and application support. A lot of what LTC does is still bipolar turing cycle time, and even cost. We have always thought it was impor- analog, which tends to be higher power and higher voltage. Maxim, on tant to have a fab to control our own destiny, to be able to differentiate the other hand, was an offshoot of Intersil. What Intersil did well was our products. There are now fabs in China that will allow customers to go 48 PORTABLE DESIGN
  • 47. in and create their own processes, and that’s a new twist that’s happened portable device use state. Some examples are dynamic voltage scaling in the last 10 years. for applications processors; Hyper Light Load Mode for state retention I started the company in 1978, and three years later we had our own and light load conditions; and high-efficiency RF subsystem power man- fab. We were the first true foundry. My brother actually started it in 1971; agement. Smart power management has enabled dramatic improvements it was called Advanced LSI, and they were strictly a foundry. I ended up in battery life, and there’s every reason to believe this will continue to be buying it in 1981 from Siemens. But it wasn’t until 1985 that we started true going forward. to create our own products. We got into analog then because I didn’t think that in the digital world Portable Design: How do you see the portable market— I could get the margins that I needed. Since Maxim and LTC were doing consumer electronics in particular—evolving over the quite well, we decided to build design teams along the same lines. next 3-5 years? Today we own our own fabs, the building and equipment, we have an Zinn: Service providers and cell phone makers are going to con- excellent cost structure and we’re virtually debt-free. We still do some tinue to try to differentiate themselves in terms of design, features and foundry work—for example, we make solar cells for our largest cus- form-factors. I expect to see them add digital TV; GPS with extensive tomer. But mostly we make our own chips. map and up-to-the-minute local point-of-interest information; improved PDA/computing functions; more multi media and gaming features; and Portable Design: Micrel derives a substantial portion of of course more video content and capabilities. its net revenues from standard products. But in handsets The basic phone will improve a lot, too. Video phones will appear, in particular, more and more support chips—or at least along with improved digital picture quality due to larger, high-resolution their functions—are getting pulled into SoCs. What is screens. This will require higher data rate transfers. Pentaband phones Micrel doing in response to this trend? will be common, with Wi-fi, WiBro and WiMAX support. Flash memory Zinn: It’s true that more support functions are becoming standard- will be able to handle huge files. ized and then getting integrated. However, handset OEMs constantly try to differentiate mid- to high-end handsets by going beyond what’s con- Portable Design: How do you see Micrel changing over sidered “standard,” and that creates continuous opportunity for “add-on the same timeframe? functions” that big analog baseband chips can’t integrate or anticipate Zinn: Micrel will continue to offer the building blocks enabling in- early enough to integrate. Recent examples are the expanding use of ap- novation in cell phones. We’ll continue to focus on ease of use for cus- plication processors for high-end graphics and multimedia; GPS chipsets tomers. We’ll continue to push into smaller packages. We’ll continue to in non-CDMA handsets; larger LCD screens; and >3M pixel cameras develop high-PSRR LDOs in higher frequency ranges, including more requiring zoom, autofocus and high-current flash drivers. internal-inductor ICs; moving to higher integration PMICs (power man- agement ICs); more focus on partnering for reference designs; and pos- Portable Design: In portable electronics, batteries are sibly digital power management if and when the value/price point in the improving orders of magnitude more slowly than the market is reached. products that rely on them. To what extent can smart power management address this issue beyond what’s Micrel, Inc., San Jose, CA already being done? (408) 944-8088. [www.micrel.com]. Zinn: Just a few years ago, cell phones were primarily voice-cen- tric devices. However with the increased competition, service providers and cell phone makers are aiming to differentiate themselves in terms of design, features and form-factors. Some of these new features include multi-mega pixel cameras with high-power flashes, GPS navigation sys- tems, high-efficiency multi-band power amplifiers, digital TV function- ality, and much more. The cell phone battery chemistry has remained the same during this period of time, with battery capacities trending up only slowly. Battery technology will continue to improve incrementally, with the advent of 2.3V Li+ batteries and eventually fuel cells. The surest way to get added functionality is by improving the effi- ciency of the overall power management. Smart power management will continue to increase battery life through advanced state management, where the most efficient power delivery mode is selected for any given JANUARY 2008 49
  • 48. The RTC Group is a media services company specializing in bring- ing companies and their products to a focused group of electronic and computer manufacturers. RTC is proud of its track record of blazing new trails in search of advertiser index marketing value for our clients. Portable Design magazine is the newest addition to RTC Group’s collection of publications. 3M Touch Systems 7 www.3m.com/touch Altera Corporation 2 www.altera.com event calendar 02/05-07/08 AVIONICS EXPO 36 www.avionics05.com AFCEA West 2008 San Diego, CA Cirrus Logic 29 www.cirrus.com www.afcea.org Delkin Devices 51 www.delkin.com 02/08-10/08 So. California Linux Expo Los Angeles, CA EmbeddedCommunity.com 4 www.embeddedcommunity.com www.socallinuxexpo.org Lattice Semiconductor Corporation 25 www.latticesemi.com 02/12/08 Real-Time & Embedded Linx Technologies, Inc 4 www.linxtechnologies.com Computing Conference Atlanta, GA www.rtecc.com/atlanta2008 Mouser Electronic 21 www.mouser.com 02/19/08 MVACEC 41 www.mvacec.com Real-Time & Embedded www.mountainviewalliance.org Computing Conference Huntsville, AL www.rtecc.com/huntsville2008 National Semiconductor 52 www.national.com 02/21/08 Real-Time & Embedded 43 www.rtecc.com Real-Time & Embedded Computing Conference Computing Conference Melbourne, FL www.rtecc.com/melbourne2008 VadaTech 35 www.vadatech.com 03/03-07/08 White Electronic Designs 15 www.wedc.com SD West 2008-01-14 Santa Clara, CA Wind River Systems, Inc. 17 www.windriver.com www.sdexpo.com 03/11-12/08 Mountain View Alliance Communications Ecosystem Conference San Francisco, CA www.mvacec.com 03/17-18/08 VoiceCon Orlando 2008 Orlando, FL www.voicecon.com If you wish to have your industry event listed, contact Sally Bixby with The RTC Group at sallyb@rtcgroup.com
  • 49. PowerWise® LED and OLED Drivers for Energy-Efficient Handheld Lighting Designs national.com/LED LM4510 Synchronous Step-Up DC-DC Converter Enables OLED Displays LM45 DC-DC converter LM4510: LM2755: Charge pump LED controller with programmable LM27 with wide adjustable patte pattern generators that facilitate multi-zone backlighting outpu voltage output in by independently controlling RGB indicator LEDs LM2757: Smallest inductorless LM2 LM2756: White LED driver with digital LM27 boo boost regulator for keypad lighting brigh brightness control and flexible LED and peripheral features including configurations for multiple display or USB On-The-Go (OTG) keyp keypad lighting systems Applications Handheld and portable lighting including handset, GPS navigation, and portable medical devices To learn more about LED drivers visit: national.com/LED © National Semiconductor Corporation, 2007. National Semiconductor, , and PowerWise are registered trademarks of National Semiconductor Corporation. All rights reserved.