ET4508_review 2005.ppt

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ET4508_review 2005.ppt

  1. 1. Exam <ul><li>General Comments: </li></ul><ul><ul><li>Provisional date/time/venue: 16/05/2005, 9am, C1058-1060 (make sure to re-check at http://www.timetable.ul.ie/ !) </li></ul></ul><ul><ul><li>Duration: 2½ h </li></ul></ul>
  2. 2. ED5532 Instructions
  3. 3. ET4508 Instructions
  4. 4. General recommendations <ul><li>Recommendations for exam preparation </li></ul><ul><ul><li>Go through slides (on the web) </li></ul></ul><ul><ul><li>Use lecture notes as the reference material </li></ul></ul><ul><ul><li>Look at past exam papers (in particular: 2003-2004) </li></ul></ul><ul><ul><li>Selected exercises taken from tutorial sheets 1-3 </li></ul></ul>
  5. 5. Focus Part A <ul><li>Focus of Part A – Multiple choice </li></ul><ul><ul><li>MPU fundamentals </li></ul></ul><ul><ul><ul><li>Buses, address decoding, read and write cycles, memory-mapped I/O vs separate I/O mapping, stacks, interrupts, DMA, etc… </li></ul></ul></ul><ul><ul><li>Processors 8086 (main features, register set, functional units, bus interface, minimum system…) </li></ul></ul><ul><ul><li>Processor evolution (86, 286, 386, 486, Pentium, MMX, P6, P7), main features, register sets, bus widths, bus interface, burst mode… </li></ul></ul><ul><ul><li>Modes of operation (real mode vs protected mode) – main differences… </li></ul></ul><ul><ul><li>Instruction queues, instruction pipelines, super-scalar architecture, RISC vs CISC </li></ul></ul><ul><ul><li>Memory devices (static/dynamic RAM, ROM, EPROM, Flash), width of data bus and address bus, </li></ul></ul><ul><ul><li>ISA, EISA, VESA, main features </li></ul></ul><ul><ul><li>PCI bus, main features </li></ul></ul><ul><ul><li>AGP bus, main features </li></ul></ul>
  6. 6. Focus Part B <ul><li>Processors: RISC vs CISC </li></ul><ul><li>Cache memories </li></ul><ul><li>Pipelines </li></ul><ul><li>Memory management (segmentation and paging) </li></ul><ul><ul><li>look at exercises </li></ul></ul><ul><li>PC Architectures and Expansion Buses </li></ul><ul><li>Legacy ports </li></ul><ul><li>USB </li></ul><ul><li>Excluded topics: </li></ul><ul><ul><li>Sections/details skipped during classes </li></ul></ul><ul><ul><li>PC-Card Interface (L13-x) </li></ul></ul>
  7. 7. Tutorial <ul><li>Selected questions from ET4508 / ED5532 Tutorial Sheets 1-3 ( http://www.ul.ie/~rinne/et4508. htm ) </li></ul>
  8. 8. Tutorial #1 – Q4 <ul><li>Superscalar processors use more than one pipeline </li></ul><ul><li>Under best case conditions the Pentium can complete two instructions in every clock </li></ul><ul><li>IA-32 instructions have to be ‘paired’ according to Intel rules </li></ul><ul><ul><li>Pipeline u can execute any IA-32 instruction </li></ul></ul><ul><ul><li>Pipeline v can execute ‘simple’ instructions </li></ul></ul><ul><ul><li>Pipeline u gets filled first </li></ul></ul><ul><ul><li>If the second instruction is NOT part of a pair – it waits for the next slot </li></ul></ul><ul><li>All pairing & decoding decisions are done in hardware –software support not required – but helps performance </li></ul>
  9. 9. Tutorial #1 – Q4 FP Pipeline has 8 stage Shares first 4 stages with u integer pipeline WB of U is first execution stage of FP pipline
  10. 10. <ul><li>CISC = Complex Instruction Set Computer </li></ul><ul><li>Complex instructions. Code-size efficient </li></ul><ul><li>Micro-encoding of the machine instructions </li></ul><ul><li>Extensive addressing capabilities for memory operations </li></ul><ul><li>Few, but very useful CPU registers … </li></ul><ul><li>CISC drawback: Most instructions are so complicated, they have to be broken into a sequence of micro-steps </li></ul><ul><li>These steps are called Micro-Code </li></ul><ul><li>Stored in a ROM in the processor core </li></ul><ul><li>Micro-code ROM: Access-time and size... </li></ul><ul><li>They require extra ROM and decode logic </li></ul>Tutorial #1 – Q5
  11. 11. <ul><li>RISC = Reduced Instruction Set Computer </li></ul><ul><li>Sometimes executing a sequence of simple instructions runs quicker than a single complex machine instruction that has the same effect </li></ul><ul><li>Reduce the instruction set to simplify the decoding </li></ul><ul><li>Smaller Instruction Set -> Simpler Logic -> Smaller Logic -> Faster Execution </li></ul><ul><li>Eliminate microcode – hardwire all instruction execution </li></ul><ul><li>Pipeline instruction decoding and executing – do more operations in parallel </li></ul>Tutorial #1 – Q5
  12. 12. <ul><li>Load/Store Architecture – only the load and store instructions can access memory </li></ul><ul><ul><li>All other instructions work with the processor internal registers </li></ul></ul><ul><ul><li>This is necessary for single-cycle execution – the execution unit can’t wait for data to be read/written </li></ul></ul>Tutorial #1 – Q5
  13. 13. <ul><li>Increase number of internal register due to Load/Store Architecture </li></ul><ul><li>Also registers are more general purpose and less associated with specific functions </li></ul><ul><li>Compiler designed along with the RISC processor design. Compiler has to be aware of the processor architecture to produce code that can be executed efficiently </li></ul>Tutorial #1 – Q5
  14. 14. <ul><li>Problem of given code sequence: </li></ul><ul><ul><li>Register dependency </li></ul></ul><ul><li>Resulting in </li></ul><ul><ul><li>pipeline flush, temporary loss of performance </li></ul></ul><ul><li>Problem avoided by smart compilers </li></ul>Tutorial #1 – Q5
  15. 15. Tutorial #2 – Q1 <ul><li>Unified cache for code and data – e.g. i486: More efficient use of resources </li></ul><ul><li>Separate (Harvard) code and data caches – e.g. Pentium </li></ul><ul><ul><li>Faster because you can access code and data in the same clock cycle </li></ul></ul>
  16. 16. Tutorial #2 – Q1 <ul><li>Cache Hit: if data required by the CPU is in the cache we have a cache hit , otherwise a cache miss </li></ul><ul><li>Cache Hit Rate: Proportion of memory accesses satisfied by cache, Miss Rate more commonly referred to </li></ul><ul><li>To prevent memory bottlenecks cache miss rate needs to be no more than a few percent </li></ul><ul><li>Cache Line: A block of data held in the cache. It’s the smallest unit of storage that can be allocated in a cache. Processor always reads or writes entire cache lines. Popular cache line size: 16-32 bytes </li></ul><ul><li>Cache Line Fill: occurs when a block of data is read from main memory into a cache line </li></ul>
  17. 17. Tutorial #2 – Q1 <ul><li>Direct-mapped cache </li></ul><ul><ul><li>two different memory locations sharing the same set address cannot be held in the cache at the same time. They will contend… </li></ul></ul>
  18. 18. Tutorial #2 – Q1 <ul><li>Two-way Set-associative cache </li></ul><ul><ul><li>two different memory locations sharing the same set address can be held in the cache at the same time </li></ul></ul>
  19. 19. Tutorial #2 – Q1
  20. 20. Tutorial #2 – Q1 <ul><li>MESI Protocol </li></ul><ul><ul><li>Formal Mechanism for controlling cache consistency using snooping </li></ul></ul><ul><ul><li>Every cache line is in 1 of 4 MESI states (encoded in 2 bits) </li></ul></ul><ul><li>M odified An M-state line is available in only one cache and it is also MODIFIED (different from main memory). An M-state line can be accessed (read/written to) without sending a cycle out on the bus </li></ul><ul><li>E xclusive An E-state line is also available in only one cache in the system, but the line is not MODIFIED (i.e., it is the same as main memory). An E-state line can be accessed (read/written to) without generating a bus cycle. A write to an E-state line causes the line to become MODIFIED </li></ul><ul><li>S hared This state indicates that the line is potentially shared with other caches (i.e., the same line may exist in more than one cache). A read to an S-state line does not generate bus activity, but a write to a SHARED line generates a write-through cycle on the bus. The write-through cycle may invalidate this line in other caches. A write to an S-state line updates the cache </li></ul><ul><li>I nvalid This state indicates that the line is not available in the cache. A read to this line will be a MISS and may cause the processor to execute a LINE FILL (fetch the whole line into the cache from main memory). A write to an INVALID line causes the processor to execute a write-through cycle on the bus </li></ul>
  21. 21. Tutorial #2 – Q1 <ul><li>Data cache: 2 bits required for encoding of 4 possible states (MESI) </li></ul><ul><li>Code cache: inherently write protected. only 1 bit required for 2 possible states (SI) </li></ul>

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