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Enhancement of Program Speed in Dopant-Segregated Schottky ... Enhancement of Program Speed in Dopant-Segregated Schottky ... Document Transcript

  • 78 IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 1, JANUARY 2009 Enhancement of Program Speed in Dopant-Segregated Schottky-Barrier (DSSB) FinFET SONOS for NAND-Type Flash Memory Sung-Jin Choi, Jin-Woo Han, Sungho Kim, Moon-Gyu Jang, Jin Soo Kim, Kwang Hee Kim, Gi Sung Lee, Jae Sub Oh, Myeong Ho Song, Yun Chang Park, Jeoung Woo Kim, and Yang-Kyu Choi Abstract—A dopant-segregated (DS) Schottky-barrier (DSSB) FinFET SONOS for NAND Flash memory with a proposed archi- tecture is demonstrated for the first time. A DSSB technique with a nickel-silicided source/drain (S/D) is integrated in the FinFET with a 30–50-nm range of fin width. Compared with the conventional FinFET SONOS, the DSSB FinFET SONOS boasts very fast programming time with low voltage. For a programming state, hot electrons triggered by sharp band bending at the DS S/D region are used. As a result, a threshold voltage (Vth ) shift of 4.5 V is achieved in a fast programming time of 100 ns. Index Terms—Dopant segregated (DS), FinFET, Flash memory, hot electrons, NAND Flash, nonvolatile memory, Schottky-barrier MOSFET, silicon–oxide–nitride–oxide–silicon (SONOS), SONOS memory. I. I NTRODUCTION Fig. 1. (a) TEM image along the channel direction. Recessed S/D is formed by the etch-back technique. It is feasible to make uniform S/D in the vertical A SILICON–OXIDE–nitride–oxide–silicon (SONOS)-type device was suggested as a candidate for NAND Flash beyond the 45-nm node [1]. One of the advantages of SONOS- direction of fin depth. (b) TEM image perpendicular to the channel direction. Fabricated fin widths are in the range of 30–100 nm, and the fin height is 75 nm. The thickness of O/N/O is 3/6/4 nm. type Flash memory devices is natural immunity to floating- On the one hand, dopant-segregated Schottky-barrier gate coupling issues, thereby allowing downscaling to the (DSSB) MOSFETs have attracted much attention as candidates nanoregime. The SONOS-type device can operate with very for high-performance devices in future ULSIs because of the few electrons without displaying erratic behavior [2]. How- enhancement of the injection velocity from a source side and ever, its programming time is in the range of 10−6 –10−3 s, low parasitic resistance at the S/D [3]. Moreover, doped silicon which is too long, due to the Fowler–Nordheim (FN) tunneling S/Ds are replaced by metallic materials, which leads to high mechanism in conventional NAND Flash memory. This makes immunity of the short-channel effect due to the shallow and it difficult for certain applications which require high-speed abrupt junction profile [3], [4]. Because of hot-carrier injection application. In addition, the conventional diffused source/drain from the source side generated by the intrinsic band structure, (S/D) with deep junctions obstructs further aggressive scaling specifically, DSSB MOSFETs are particularly expected to be- in the SONOS-type memory devices. come outstanding high-speed devices [5], [6]. In this letter, we have demonstrated a novel NAND Flash architecture with SONOS structure implemented in DSSB Manuscript received September 28, 2008; revised October 23, 2008. First FinFETs. Fast programming is achieved because of hot elec- published December 9, 2008; current version published December 24, 2008. trons on the DS S/D side. These hot electrons require neither This work was supported by the National Research Program for the 0.1-Terabit Nonvolatile Memory Development Initiative, sponsored by the Korea Ministry high programming voltage nor long programming time. With of Commerce, Industry and Energy. The review of this letter was arranged by the same ground voltage on the S/D junction, hot electrons trig- Editor T. Wang. gered by sharp energy-band bending were naturally generated. S.-J. Choi, J.-W. Han, S. Kim, and Y.-K. Choi are with the Division of Elec- trical Engineering, School of Electrical Engineering and Computer Science, Moreover, a divided-bit-line NAND array structure, which was Korea Advanced Institute of Science and Technology, Daejeon 305-701, Korea feasible by the commonly grounded S/D, is proposed for high- (e-mail: ykchoi@ee.kaist.ac.kr). speed programming. M.-G. Jang is with the Electronics and Telecommunication Research Insti- tute, Daejeon 305-350, Korea. J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, and J. W. Kim are with the National Nanofab Center, Daejeon 205-806, Korea. II. D EVICE D ESIGN AND F ABRICATION Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. The process flow of DSSB FinFET SONOS is the same Digital Object Identifier 10.1109/LED.2008.2008667 as that of our previous work [7], except for gate spacers and 0741-3106/$25.00 © 2008 IEEE Authorized licensed use limited to: Korea Advanced Institute of Science and Technology. Downloaded on January 1, 2009 at 23:54 from IEEE Xplore. Restrictions apply.
  • CHOI et al.: ENHANCEMENT OF PROGRAM SPEED IN DSSB FinFET SONOS FOR NAND-TYPE FLASH MEMORY 79 Fig. 2. (a) Simulated data of the electric field along the channel direction in DS Schottky-barrier FinFET SONOS. Because of the segregated layer as well as its intrinsic band structure, the electric field is intensified. It can make thermally injected or tunneled electrons at the S/D to hot electrons. (b) Divided-bit-line NAND Flash array. The ground state of the bit line is applied for programming in the proposed devices. silicided S/D formation. For DS Schottky junctions, arsenic was implanted at a dose of 1 × 1015 /cm3 at 5 keV. After that, the DS S/D junction was formed by nickel silicidation with two-step RTP. In the case of recessed S/D, it assures uniform silicided S/D in the vertical direction of fin depth, which is hard to accomplish with only S/D implantation. Conventional FinFET SONOS devices with standard p-n junction S/D were prepared as a control group. Fig. 1 shows TEM images of the fabricated DSSB SONOS FinFET. III. R ESULTS AND D ISCUSSION Fig. 2(a) shows the simulated results of a lateral electric field at S/D junction sides in a programming state [8]. Fast program- ming is achievable by applying the same ground voltage on both S/D junctions simultaneously. In this case, a high lateral electric field is generated by a sharpened band structure at the DS region. Thus, hot electrons energized by this high electric field at the S/D region are used to program the NAND Flash device. Due to hot electrons, fast programming with low voltage is feasible. In Fig. 2(b), a NAND-cell array structure to include a divided bit line is designed to achieve the aforementioned novel programming method. The selected cell is programmed by applying the ground bias from both the top bit line and the bottom bit line at the same time. On the other hand, the unselected cell is not programmed by applying positive voltage at the S/D so that it reduces the electric field between the S/D and the channel. Fig. 3 shows the novel programming/erasing transient char- acteristics and the Vth change according to read voltage (Vds ). Fig. 3. (a) Program and erase transient characteristics by various program As a reference, a conventional FinFET SONOS with a diffused voltages. Excellent program efficiency compared with that of a control group p-n junction is compared. Fig. 3(a) shows the excellent program is achieved due to hot electrons energized by sharp band bending at the S/D. efficiency of DSSB FinFET SONOS by the new programming However, the erase efficiency is not much different from that of a control group. (b) Vth characteristics according to various drain voltages. The injection of hot method. The program condition VPGM = 12 V with tPGM = electrons at the S/D can cause a relatively small DIBL value in DSSB FinFET 100 ns exhibits the Vth shift of 4.5 V in the DSSB FinFET SONOS. SONOS. It should be noted that a significant Vth shift for pro- gramming was achieved within a few tens of nanoseconds. The to hot-carrier injection energized by sharp band bending at the difference of the Vth shift between a DSSB FinFET SONOS DS S/D junction edge. These outstanding results are among the and a conventional FinFET SONOS for programming is ap- best results in terms of Vth window and programming/erasing proximately 3 V at 100-ns programming time. This is attributed speed among FinFET structure Flash memory devices [9]–[11]. Authorized licensed use limited to: Korea Advanced Institute of Science and Technology. Downloaded on January 1, 2009 at 23:54 from IEEE Xplore. Restrictions apply.
  • 80 IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 1, JANUARY 2009 However, there is no significant difference of erase character- istics between a DSSB FinFET SONOS and a conventional one because band bending is not as much sharp as that at the programming state. However, slow erase characteristics can be circumvented by BE-SONOS technology [9]. Fig. 3(b) shows characteristics of drain-induced barrier low- ering (DIBL) with various program conditions for the DSSB FinFET SONOS and a conventional one. Even though the characteristics of DIBL at an initial state are almost the same, they are clearly different in a programming state. The difference arises from locally trapped electrons in the DSSB FinFET SONOS. Because of hot-carrier injection for the programming state at the source side as well as the drain side, the charac- teristic of DIBL in the programmed DSSB FinFET SONOS is smaller than those in the conventional one. In the case of typical FN programming for a conventional FinFET SONOS, globally distributed electrons along the channel can cause a larger DIBL value than locally confined electrons at S/D sides of the DSSB FinFET SONOS due to the unwanted nonuniform charge trapping. For comparison, the Vth shift is also compared in Fig. 3(b) with the channel-hot-electron-injection (CHEI) programming (Vgs,PGM = 9 V and Vds,PGM = 4 V) condition for a conventional FinFET SONOS. In the case of the forward read state in CHEI programming, the surface potential in a conventional FinFET SONOS is more sensitive to the drain bias than in the reverse read state due to locally trapped electrons on the drain side. In the case of the reverse read state, however, the surface potential is less sensitive to the drain bias than in the forward read state. Consequently, the DIBL characteristics of the reverse read state for a conventional FinFET SONOS and the new programming method for the DSSB one are very Fig. 4. (a) Postcycling retention comparison of the DSSB FinFET SONOS and a conventional one. Due to damages of hot electrons, the charge loss of the similar due to locally trapped electrons, as shown in Fig. 3(b). DSSB FinFET SONOS is larger than that of a conventional one. (b) Measured The retention characteristics after 1k cycling and the P/E endurance characteristics of the DSSB FinFET SONOS and a conventional one. cycling endurance of the DSSB FinFET SONOS compared The negligible Vth shift is observed in P/E states. with that of the control group, a conventional FinFET SONOS, segregated Schottky-barrier FinFET SONOS is a promising are shown in Fig. 4(a) and (b), respectively. These character- candidate for Flash memory beyond the 30-nm node, particu- istics are measured at room temperature. Fig. 4(a) shows that a larly in terms of high-speed programming. rapid degradation of the retention characteristics was monitored during a longer programming time, which is a worse condition for the stored charges to be lost by more damage by hot carriers R EFERENCES degrading the tunneling oxide quality. Nevertheless, the Vth [1] K. Kim, “Technology for sub-50 nm DRAM and NAND Flash manufac- turing,” in IEDM Tech. Dig., 2005, pp. 323–326. margin of the DSSB FinFET SONOS after ten years is larger [2] M. Janai, “Data retention, endurance and acceleration factors of NROM than that of a conventional one because of the high efficiency devices,” in Proc. IRPS, 2003, pp. 502–505. of programming originating from the sharpened energy-band [3] A. Kaneko, A. Yagishita, K. Yahashi, T. Kubota, M. Omura, K. Matsuo, I. Mizushima, K. Okano, H. Kawasaki, T. Izumida, T. Kanemura, bending by the DSSB structure. P/E endurance characteristics N. Aoki, A. Kinoshita, J. Koga, S. Inaba, K. Ishimara, Y. Toyoshima, are also shown in Fig. 4(b). After 105 P/E cycles, only the H. Ishiuchi, K. Suguro, K. Eguchi, and Y. Tsunashima, “High- negligible Vth shift is seen, which can assure that reliability performance FinFET with dopant-segregated Schottky source/drain,” in IEDM Tech. Dig., 2006, pp. 893–896. characteristics are satisfactory. [4] A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, and J. Koga, “Solution for high-performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique,” in VLSI Symp. IV. S UMMARY Tech. Dig., 2004, pp. 168–169. [5] K. Uchida, K. Matsuzawa, J. Koga, S. Takagi, and A. Toriumi, A novel dopant-segregated Schottky-barrier FinFET SONOS “Enhancement of hot-electron generation rate in Schottky source with a conceptual NAND Flash architecture is proposed. metal–oxide–semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 76, no. 26, pp. 3992–3994, Jun. 2000. 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