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Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
Dual-Gate TFT for 3-D Flash Memory
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Dual-Gate TFT for 3-D Flash Memory

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  • 1. Dual-Gate TFT for 3-D Flash Memory Andrew Walker Schiltron Corporation December 4th 2009
  • 2. Contents • The Gathering Storm • The Inevitability of 3-D Flash • The Contenders for the Crown • Charge Trap Flash in 3-D • The Schiltron Solution Explained • Prototype Process Flow • Physical Results • Electrical Results • Conclusions • Acknowledgements
  • 3. The Gathering Storm Worldwide NAND Flash Memory Consumption by Major End Use Application Source: In-Stat Report “Flash Applications Drive Strong Revenues Worldwide” Dec. 2008
  • 4. The Gathering Storm • NAND Flash market > $50B by 2014 • BUT….. • Classic NAND Flash within 2 years of brick wall – 1 final technology node at sub-30nm half-pitch – Multi-bit per cell exhausted • 3-D inevitable • IEDM Dec. 2009: – First time with dedicated 3-D nonvolatile memory session – 3-D Charge-Trap-Flash-based in 4 out of 6 papers (ST, Toshiba, Macronix, Kaist) – One 3-D PCM (Intel/Numonyx) – One NEMS mechanical memory (Kaist)
  • 5. The Gathering Storm • NAND Floating Gate Challenges – ONO does not scale – Tunnel oxide does not scale – Inter-cell interference • Coupling Ratio collapses Required floating gate height to suppress inter-poly parasitic coupling and the effect on the coupling ratio Source: Y. Shin, Samsung, Symp. VLSI Circuits 2005
  • 6. The Inevitability of 3-D Flash • Lateral scaling: – A method that complicates a semiconductor process but increases the number of good die per wafer – Cost increase due to process complexity more than offset by cost decrease due to increased good die per wafer • Monolithic 3-D Stacking: – Logical alternative to lateral scaling – Also increases process complexity but increases the number of die per wafer • What is the Real Cost Advantage of 3-D Stacking ? – Process complexity and cost increase – Yield may decrease – Number of die per wafer increases
  • 7. The Inevitability of 3-D Flash ⎞ ⎛ C o + C crit _ mask .N crit _ mask ⎞ 2 ⎛ Y2 D ⎞⎛ 1 ⎞ ⎛ F3 D ⎞ ⎛ MLC 2 D 3D 3D 3D C =⎜ die ⎟.⎜ ⎜ ⎟.⎜ ⎟⎜ F ⎟ ⎟ ⎜ .⎜ ⎟.⎜ ⎟ C die ⎜ Y3 D 2D ⎝ ⎟ N ⎠⎝ L ⎠ ⎝ 2D ⎠ ⎝ MLC 3 D ⎟ ⎜ C + Z n .C 3 D ⎠⎝ o crit _ mask 2D .N crit _ mask ⎟ ⎠ • Equation for cost of good 3-D die divided by cost of good 2-D die • Y – yields • NL – number of memory device layers • F – minimum half pitch • MLC – number of electrical bits per cell • Co – base wafer cost without memory processing • Ccrit_mask – cost of each critical memory masking layer and process • Ncrit_mask – number of critical masking layers • Z – rate of increase in wafer cost between generations • n – number of generations between 3-D and 2-D processes Source: A.J. Walker, IEEE Trans. Semi. Manuf. May 2009
  • 8. The Inevitability of 3-D Flash Source: A.J. Walker, IEEE Trans. Semi. Manuf. May 2009
  • 9. The Inevitability of 3-D Flash
  • 10. The Contenders for the Crown • Resistance Change Approaches – Phase Change Memory (PCM) – Intel/Numonyx – Simple Metal Oxide – SanDisk/Toshiba ? – Perovskite - Unity ? – Solid-State Electrolytes - Axon • At least 2 masking steps per device layer • Probably 3
  • 11. The Contenders for the Crown • Charge Trap Flash in Vertical Plane – Vertical Recess Array Transistor (VRAT) - Samsung – Bit Cost Scalable (BiCS) - Toshiba Source: Symp. VLSI Technology 2009
  • 12. The Contenders for the Crown • Charge Trap Flash in Horizontal Plane – TANOS - Samsung – TFT (BE)-SONOS - Macronix – Dual-Gate TFT SONOS - Schiltron Source: Jung et al., IEDM 2006
  • 13. Charge Trap Flash in 3-D Vread-pass Vread-pass Vread ONO Source To Bit Line N+ N+ N+ N+ Inversion channel • Vread-pass > Vtprog(max) + margin Pass disturbs on • Vprog-pass > Vtprog(max) + margin selected string • Applies to both lateral and vertical NAND CTF
  • 14. Charge Trap Flash in 3-D FG scaling Nitride Need good worst-case problems at string current Read Pass Disturb Storage < 30nm Thicken up Thicken up tunnel oxide tunnel oxide Optimization Circle Need high Program/pass disturb erase voltage Thicken up blocking oxide Need high (Al2O3) program voltage Use high Work Function gate (TaN) • Serious read pass and program pass disturbs remain • High program/erase voltages • MLC extremely challenging • Classic NAND blocks the advantages of classic SONOS
  • 15. Charge Trap Flash in 3-D Vread_pass (V) Lifetime = time to shift erased Vt by 3V Source: C.-H. Lee at al., Symp. VLSI Technology 2006
  • 16. The Schiltron Solution Explained Inversion channel and DG structure with close electrostatic depletion region providing interaction between top and bottom good shielding of memory devices providing good short channel charge from pass voltages control Vread Second Gate ONO Source To Bit Line N+ N+ N+ N+ First Gate Vread_pass OFF Vread_pass • Vread-pass decoupled from Vtprog(max) • Vprog-pass decoupled from Vtprog(max)
  • 17. Prototype Process Flow • Test chip developed and laid out • Process architecture and recipes developed • Processed in Silicon Valley Technology Center (SVTC), San Jose • First silicon functional • Smallest feature size < 50 nm
  • 18. Prototype Process Flow HDP Oxide Nitride etch stop on oxide Silicon wafer
  • 19. Prototype Process Flow Oxide trench etch and poly dep
  • 20. Prototype Process Flow PolySilicon CMP1 (forms GATE1)
  • 21. Prototype Process Flow After polysilicon CMP1 (forms GATE1)
  • 22. Prototype Process Flow X HDP oxide dep and channel trench etch Y
  • 23. Prototype Process Flow 32 cell string after channel trench etch
  • 24. Prototype Process Flow X Gate1 oxide formation and channel a-Si dep Y
  • 25. Prototype Process Flow X a-Si CMP2 (forms active channels) Y
  • 26. Prototype Process Flow After CMP2 Over 13 wafers: 16nm average oxide loss with 3sigma of 6nm
  • 27. Prototype Process Flow X ONO formation Y
  • 28. Prototype Process Flow X GATE2 deposition Y
  • 29. Prototype Process Flow X GATE2 litho & etch Y
  • 30. Prototype Process Flow 64 cell string after 2nd gate formation
  • 31. Prototype Process Flow X Source/drain implant and low-temp anneal Y
  • 32. Prototype Process Flow CMP1 CMP2 XTEM perpendicular to wordline gate direction
  • 33. Prototype Process Flow CMP2 CMP1 XTEM perpendicular to channel direction
  • 34. Physical Results 48nm gatelength 45nm channel width 350 A channel “nanowire” thickness
  • 35. Physical Results 1020 Antimony Concentration (/cm3) 1019 1018 1017 1016 1015 0 50 100 150 200 Depth (nm)
  • 36. Electrical Results Sheet Resistance (Ohm/sq) 2000 1800 1600 1400 Anneal time = 1 min 1200 1000 500 550 600 650 700 750 800 850 Anneal Temperature (C)
  • 37. Electrical Results 10-6 4 Source-Drain Current (A) 10-7 3 2 10-8 W/L = 50nm/65nm 2nd dch ~ 35nm 10-9 1 Vds = 0.5V -4 1st 10-10 -3 0 Second Gate Voltage (V) 10-11 -2 -1 10-12 -2 -1 0 1 2 3 4 5 First Gate Voltage (V)
  • 38. Electrical Results Second Gate Threshold Voltage (V) Programmed memory cell 4 3 2 N+ N+ 1 Vpass=9V 0 1 10 100 1000 Duration of 9V Application to First Gate (s)
  • 39. Electrical Results 64 cell cell string (W/L=45nm/48nm Devices) Midcell OFF Gate voltage OFF Bit Line Source ON with read pass voltage ON with read pass voltage OFF
  • 40. Electrical Results 10-7 8 7 6 Worst-Case String Current (A) 64 cell string 5 W/L = 45nm/47nm 4 dch ~ 35nm Vds = 1V 3 10-8 Mid-cell first gate at -3V 2 10-9 Read-Pass Voltages (V) All memory devices off except mid-cell 10-10 -1 0 1 2 3 4 5 Second Gate Voltage on Mid-Cell (V)
  • 41. Electrical Results Read-Pass Voltage (V) 200 8 Worst-Case String Current (nA) 64 cell string 180 W/L = 45nm/47nm dch ~ 35nm 7 160 Mid-cell first gate at -3V 140 All memory devices 6 off except mid-cell 120 Mid-cell second gate at 3V 100 5 80 60 4 40 3 20 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 String Source-Drain Voltage (V)
  • 42. Electrical Results 800 Worst-Case String Current (nA) W/L = 45nm/47nm 8 cell 700 dch ~ 35nm Vds=1.1V 600 Mid-cell first gate at -3V All memory devices 500 off except mid-cell Mid-cell second gate at 3V 16 cell 400 300 32 cell 200 100 64 cell 0 2 3 4 5 6 7 8 Read-Pass Voltage (V)
  • 43. Electrical Results 4 Threshold Voltage (V) 32 cell string 3 W/L = 45nm/47nm dch ~ 35nm Vprog/Verase = 17.5V 100us / -13V 400ms Read-pass voltage = 7V Program-pass voltage = 7V 2 Erase-pass voltage = 6V 1 10 102 103 104 105 Number of Cycles
  • 44. Electrical Results 4 After 105 cycles Threshold Voltage (V) 10 years 3 2 1 0 10 102 104 106 108 Time at 85C (s)
  • 45. Conclusions • 3-D stackable and inherently scalable • Existing materials and methods – No new materials or material breakthroughs required – Program/erase close to existing approaches • Ideal for both stand-alone (NAND replacement) and embedded • No pass disturbs – Shielding gets rid of the bane of all Charge Trap Flash NAND • Concept shown on silicon at W and L < 50nm with 64 bit strings – IEDM Dec. 2008 – IEEE Trans. Semicon. Manufacturing May 2009 – 3D cost model – IEEE Trans. Electron Devices Nov. 2009
  • 46. Acknowledgements • Professors Endoh and Nishi for the invitation to speak at this Workshop • TJ Rodgers at Cypress Semiconductor and CJ Koomen for initial investment • R. Rhoades at Entrepix for CMP expertise • L. Liang at Precision TEM • A. Chatila at MEMC for constant support • L. Marques for constant support

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