Our agenda today is to first give you an overview of the COP8 Feature family architecture, then examine advanced features of COP8FLASH in more detail. Emphasis will be on the FLASH memory and In-System-Programming. Various integrated peripheral modules are explained. There is a major thrust at National to integrate analog functions on current and future generation devices. All new devices are targeted toward low power applications with a focus on small outline packaging. We will take a look at currently available COP8FLASH family members and their supporting development tools. A new In-System-Emulator is introduced which takes advantage of COP8FLASH’s integrated, hardware assisted, background debugging mode to give the designer unique benefits in emulating on-chip analog functions. We will conclude this session with the discussion of the COP8FLASH product roadmap.
All COP8 microcontrollers share a common block of logic, known as the COP8 core. The core includes the COP8 Central Processing Unit (CPU), the MICROWIRE/PLUS serial interface and the 16-bit Multi-Function Timer T1. The core registers are contained within this block. The CPU registers include a 15-bit program counter (PC), a processor status word (PSW), an 8-bit accumulator (ACC), and two core control registers (CNTRL, ICNTRL). The COP8 is able to access program memory and data memory concurrently, thus reducing execution time. This is achieved by using a modified “Harvard” architecture whereby the program memory is distinct from the data memory. Each type of memory has its own physical memory space and internal address bus. By comparison, in the “Von Neumann” architecture, where program and data memory share the same address space, concurrent access cannot occur. The COP8 architecture contains an improvement over the conventional Harvard architecture. The Load Accumulator Indirect ( LAID ) instruction allows access to data tables stored in program memory. The COP8 micro. is an accumulator based design. Apart from the Accumulator (A) and the Program Counter (PC), all registers, I/O ports and RAM are memory mapped into the data memory address space. Timer T1 is a 16-bit Multi-Function timer with two 16-bit auto-reload/capture registers. It can be configured to operate in any of three modes: Pulse Width Modulation (PWM), external event counter or input capture mode. The interrupt controller module supports up to 15 sources of interrupts. The priority scheme it uses is fixed, with two non-maskable interrupts, NMI and software trap, having the highest ranking. A non-maskable interrupt can not be interrupted by a maskable, Non-maskable can interrupt a maskable. Interrupts not serviced are latched and their Interrupt pending flags are set. The pending interrupts are serviced based on their priority level, following the return of the CPU from current ISR. The Microwire/Plus serial interface controller is also built into the core. The controller supports both Microwire and SPI synchronous serial communication protocols. The instruction set on COP8FLASH is very efficient with 77% single byte single cycle. The execution unit traps illegal instructions and interrupts the CPU. The COP8 is a fully static uC, the contents of the RAM and the registers are retained even without a clock. COP8FLASH features several power saving modes; Halt, Idle, and Dual Clock. We will later examine these features in more detail.
Some of the functions presented here are unique to COP8FLASH. In the timer block there is the Idle timer, which is a free running real time clock. It is used for waking-up the controller from the Idle power save mode, and in conjunction with the Watchdog to determine the watchdog service window. The other two timers T2 and T3 are 16-bit Multi-Function, similar to T1, however, they can be clocked as fast as 50ns with a 10MHz system oscillator. For nonvolatile program/data storage there are up to 32K bytes of FLASH memory available. A 1K byte SRAM provides plenty of storage space for on chip buffers and variables. The device packs up to six bi-directional 8-bit I/O, one 4-bit I/O and one 8-bit output port into a 68-pin PLCC package. That’s 52 individually programmable I/O and 8 output only pins, all with high sink/source capability. Another powerful feature is an integrated supply voltage monitoring circuit, the Brownout reset. For power sensitive applications we have introduced the dual clock mode, which allows the user to switch between a fast and a slow clock for optimal power consumption. The core clock speed has also been doubled compared to previous architecture. The on-chip clock doubler multiplies the selected system clock by a factor of two. No COP8FLASH microcontroller can go without a “Watchdog” and clock monitor onboard, providing your designs with two additional levels of fail safety There are 8 Multi-Input-Wake-Up inputs, which can be used to get the device out of the Halt or Idle mode. They can also be used as individually configurable external interrupts.
FLASH memory retains its content when the power is removed. It is also electrically erasable and programmable. The COP8FLASH devices are available in various sizes of FLASH memory. The memory array is sectored in blocks of 128 bytes on 32KB devices, and 64 bytes on others. One can erase the entire memory, using mass erase feature, in less than 8ms. After the device is erased, it can be updated. The write timing is cumulative when sector write feature is used. Individual pages can be erased in 1ms, irrespective of the operating frequency. National’s FLASH technology has 100 years data retention and endurance of 100,000. The endurance is defined as the number of erase and write cycles before any failures occur due to inability to alter state of a memory cell. Content of the FLASH memory can be changed without removing the COP8FLASH from the circuit. Using an internal secondary program memory during FLASH memory programming, allows the microcontroller to continue code execution from where it left off prior to start of FLASH programming. More on this topic later. COPFLASH operates from a singles power supply. It has on-chip chargers which are used to internally provide the high voltages required to erase and program the FLASH memory array. There are protection circuits placed internally which prevents these high voltages to feed through to external pins. All the timing and interface control signal requirements when writing to the FLASH memory is built into the COP8FLASH. The non-volatile option register resides in FLASH memory array and it is used to configure various operating modes on the microcontroller. Programming this register is similar to FLASH memory programming.
It takes about 140 s to write a single byte to the FLASH memory. During this time period the FLASH memory bus tri-states and it’s inaccessible to the microcontroller. The COP8FLASH uses a secondary program store device to feed instructions to the controller while writing to the FLASH memory. National uses 1KB of boot ROM for this purpose. Solutions from competitors use either RAM or EEPROM, which can be fatal If content is inadvertently erased. Any amount of the FLASH memory can be used for nonvolatile data backup. It can be used for storing configuration information (i.e. Serial numbers, passwords, etc.) and setup parameters. The boot ROM contains many useful routines which facilitate interfacing to the FLASH memory. The content are divided into three dedicated categories. One segment is used for FLASH memory updates through a unique protocol over the microwire interface bus. Segment two is allocated to ISP support of user written procedures. The third section provides link for National and Metalink’s new In-System-Emulator. Use these ROM based routines to perform page/mass erase, byte read/write, block read/write, sector recall into RAM buffer, etc. Benefits: Traditionally EEPROM or battery backed SRAM are used for non-volatile data store. With the integrated FLASH on the COP8 there is no need for additional store devices, eliminating extra expense and saving the precious PCB real estate. Due to small size of the FLASH memory sector, content can be updated rapidly. And the size of the virtual EEPROM can grow as your needs increase.
In data storage applications portion of the on-chip RAM is allocated for shadowing the FLASH memory sector being modified. When updating an existing parameter byte within a memory block, content of that sector is recalled into the RAM. Then the FLASH memory sector must be erased. New value of the parameter is written to the RAM leaving other bytes in the buffer unaltered. Next the FLASH memory content can be updated by transferring the RAM buffer. The user may be given the option to either retain the data in the RAM buffer or save to the FLASH memory. User might decide to discard the recent changes and keep the previously saved values and settings. Other options may be implemented that enables an auto-store feature, where the system detects a power-down condition and issues a FLASH write back command to the memory manager. These techniques can substantially reduce the number of intermediate writes to the FLASH memory, and ultimately boost overall system life cycle.
When updating FLASH memory the following steps are used in general. Similar data patterns can be skipped over. When a new pattern is found content of the page where the byte resides is recalled and stored in the RAM buffer. Use the ROM resident routines to erase the FLASH page. Update the SRAM buffer to reflect the recent data. The RAM can now be transferred to the FLASH using a ROM based routine. Repeat this loop if there are additional data.
Here is a code sample showing the instructions used to write a single byte to FLASH memory. Assume that this is the first write after performing a background erase on the page. The COP8FLASH has five dedicated registers to facilitate the FLASH memory interface. The code initially loads the physical address of byte into ISPADHI and ISPADLO registers. The data pattern is loaded in the ISPWR register. You always have set this key bit before executing any of the ROM codes. This is done by writing the KEY pattern 0x98 into ISPKEY register. The operation should immediately be followed by a JSRB instruction to the specific routine in the ROM. After the transfer to the FLASH memory is completed, the CPU returns and continues executing the code following the JSRB instruction.
During consecutive byte write operations, some of the overhead associated with single byte write is eliminated, following the first byte write. This improves the write timing for subsequent bytes, by reducing it from 140Us to 120Us. Another important feature of the COP8FLASH is latching of any interrupts which occur during FLASH write operation. Since the controller is prohibited from access the program memory during the FLASH internal write cycle, the ISR can NOT be executed in response to an Interrupt event. These interrupts are flagged by setting their corresponding Interrupt pending flag and they are recognized by the controller and processed following the FLASH write operation.
The COP8FLASH offers system designers a variety of low-power consumption features that enable them to meet the demanding requirements of today's increasing range of low-power applications. These features include low voltage operation, low current drain, and power saving features such as Dual Clock, HALT, IDLE, and Multi-Input wakeup (MIWU). In the HALT mode all microcontroller activities are stopped and power consumption is reduced to a very low level. Either a valid reset signal or transitions on MIWU inputs can terminate this mode. Content of the internal RAM and port states are preserved while in HATL mode. In the IDLE mode all microcontroller activities are stopped except on-chip oscillator, Idle timer, watchdog, and clock monitor. The IDLE mode is terminated by a Reset or any other sources of interrupts, including IDLE timer underflow. The part without the Brownout Reset feature can operate down to 2.7V.
The COP8FLASH supports three operating modes, each of which have two power save modes of operation. The three operating modes are: High Speed, Dual Clock, and Low Speed. Within each operating mode, the two power save modes are: HALT and IDLE. Coming out of Reset the device is operating in high speed clock mode. In high speed mode, the Idle timer is clocked by the instruction clock. When in dual clock mode the Idle timer clock is the same as the low speed oscillator clock.
The COP8FLASH consumes less than 15mA when operating at high speed at 10MHz. The power consumption is reduced to 50 A in slow speed mode. The internal high speed oscillator circuitry remains active when the Idle mode is entered from high-speed clock operation. In dual clock fast mode the Idle mode activation disables the on-chip high speed oscillator. In Dual clock fast and slow speed modes, the 32kHz oscillator keeps running even in HALT mode. This was done to avoid long delays with oscillator start-up times. That explains the higher Halt mode current consumption in dual clock modes when compared to the high speed clock mode.
Features The Multi-Input-Wake-Up inputs are used to wakeup the device from the HALT or IDLE mode by means of a transition on one or more pins of the Port L, caused by external events (e.g., keypress). Alternatively, they maybe used as 8 programmable edge triggered external interrupts. The Port L pins may be individually included/excluded from the wakeup logic. The port L pins are equipped with schmitt trigger inputs.
As mentioned earlier, except the Accumulator and the PC all core registers, I/O ports, and RAM are memory mapped into the data memory address space. The address range assigned for these special function registers is 80-FF. The remaining data memory addresses are available for variable data storage. Available Timers are: T0 - Also referred to as IDLE timer. T1 - Core timer, free running multi-function timer. T2, T3 – Aux. general purpose timers
The Idle timer is used to manage and control many on-chip functional blocks: 1- As an Idle timer, it provides duration of Idle mode time interval 2- In watchdog timer, it times the service window 3- Halt mode exit, it controls startup delay when exiting HALT 4- Brownout- it is used to generate timeout delay T1 is clocked by the instruction clock, the T2 and T3 timers can be either clocked by the instruction clocked or the internal high speed core clock. The general purpose timers can operate in the following modes: PWM- Pulse Width Modulation Applications of the PWM mode are: DC motor control Tone generation Internal timer for processor events Rudimentary D to A converter AC motor control (dimmer switch) In Counter mode external events on TxA pin are counted. Underflow causes reloads of timer register alternately from TxRA and TxRB. The Capture mode is predominately used for Precise measurement of external frequencies or the duration of external events
In pulse width modulation mode, the timer generates pulses, independent of the processor, with specific width and duty cycle. Pulses are placed on TxA pin. Timer tick is CLK/CPU CLK. Underflow causes reloads of timer register alternately from TxRA and TxRB. In Counter mode external events on TxA pin are counted. Underflow causes reloads of timer register alternately from TxRA and TxRB. In input capture mode, the timer can precisely measure external frequencies or time external events. In this mode, the reload registers; RXA and RXB, serve as independent capture registers, capturing the contents of the timer when an external event occurs on their corresponding input pins TxA and TxB. The trigger events can be specified either as a positive or a negative edge. Valid external transitions or timer underflow can generate interrupts.
There are several communications controllers integrated on the COP8FLASH. The Microwire Plus, is a serial synchronous communications interface. It is compatible with the legacy Microwire and SPI protocols. The communications is over 3-wires. The CLK pin is used as either output clock in master mode or as input clock in slave mode. The SO is the serial data output and SI is the serial data input . There is no CPU intervention required for data transfers on the Mirowire bus. The built-in full-duplex, double buffered USART supports both synchronous and asynchronous data transfers. It has a baud rate generator which can be clocked internally or externally. All the standard baud rates are supported using the system clock and the internal divisor. Receive and transmit baud rates can be different, allowing split baud rates. The USART is fully programmable, the data bits, stop bit, parity bit generation and detection are all software selectable. The module is also capable of generating and detecting break signals.
The on-board Brown Out protection circuit resets the device when the operating voltage (Vcc) goes below the Brown Out Voltage. The device is held in reset when Vcc stays below the Brown Out Voltage.
The Windowed Watchdog is an integral part of most COP8 devices. This feature is used to guarantee proper system operation by keeping the software execution in check. The watchdog has a fixed lower window, set at 2K Idle timer tick. The upper window interval is programmable. A data pattern written to WDSVR register must contain the fixed key sequence to reset the watchdog timer. The clock monitor detects either stopped or slow clock conditions. When the CKI input clock speed falls below a pre-set limit (COP8FLASH = 25KHz) similar trigger mechanism as the watchdog is generated. This feature can be enabled/disabled once after reset by writing WDSVR register.
If the Watchdog Service register is not continuously updated in a timely manner, the watchdog triggers an output pulse, on G1 port pin, which can be used to either reset or, using MIWU pins, interrupt the device. Don’t put watchdog service into an interrupts service routine, this would partly defeat the purpose of the watchdog (stuck in endless loop). Recommend polling the Idle timer pending flag within the main software program.
All the I/O port pins on COP8FLASH are high sink and source enabled. They can directly drive For testability and safety purposes the status of I/O pins can be read. A useful feature to be used for detecting any stuck at faults and bus contentions. The output structure of the I/O pins can be individually configured to Hi-Z, Open Drain or Push-Pull types.
The COP8CBR has an analog block which contains a 16 channel multiplexor and 10 bit ADC. The ADC uses successive approximation technique and its accuracy is +/- 1 LSB. The ADC can operate in either single ended or differential mode. Output of the Mux is normally internally tied to the ADC input, in MUX-Out mode its brought out on a port pin. In mux out mode an input port serves as ADC input, the signals from MUX output can be further conditioned by external filter before being processed using ADC. The conversion rate can be slowed down to support slow (high impedance) input signals.
COP8 microcontrollers offer the largest I/O count per mm^2 of board area.No other competitor comes even close. Pictures show 28CSP and 44 CSP in comparison to a 44 PLCC package and a standard SOT package. The 28-pin Chip Scale Package from National is smallest 28-pin microcontroller. Ideal for applications requiring compact design where the PCB real estate is in short supply. Full support tools compatibility have also been put into place. Soon the COP8FLASH will be available in 44-pin CSP.
Starting 1st quarter of 2001, new derivatives of the COP8FLASH will be made available. The main differentiating features are memory size, package type, number of I/O port pins, etc. The available packages are 44-lead PLCC and CSP. 48 and 56 lead TSSOP. 68 lead PLCC. These devices will meet both Industrial and extended temperature ratings.
These are the features which are common among all COP8FLASH members: The Idle timer (T0) The MIWU inputs The Watchdog and clock monitor blocks Clock Doubler Virtual EEPROM In-System-Programmable (ISP) The optional features are: The 10 -bit ADC with 16-channel Multiplexor Dual OpAmp with Temp Sensor - will be available Q2 Y2001 USART Extra I/O Ports Dual Clock Brown-Out Reset
COP8FLASH has been successfully utilized in Whitegood and Appliance applications. Manufacturers have the desire to store large amount of history data in non-volatile memory to assist in failure diagnostics and field service. FLASH solutions from other microcontroller manufacturers offer only a fixed EEPROM size, eg. 64 or 128 bytes. COP8FLASH’s Virtual EEPROM feature gives you the flexibility to allocate any amount of FLASH memory for non-volatile data storage. Our true ISP feature, that requires no external components or additional control signals, allows for easy remote firmware updates, even via the Internet. Other FLASH microcontrollers that store their ISP code in SRAM while updating the FLASH program memory are not suitable for such remote updates. If a power failure occurs during update, the FLASH is already erased and the ISP code in SRAM is lost. Our COP8FLASH implementation uses ISP code in a dedicated ROM, so in case of a power failure during program update, you simply restart the update. A single hardware platform can serve multiple product lines with differentiation in the system firmware. Once orders are received, at the factory floor, a blank system is pulled off the shelf and configured by loading system software for that model prior to shipping. Another application example might be smart sensor where the system can learn about its environment and adapt parameters for the current installation. Calibration factors can be saved in Virtual EEPROM and can later be adjusted and customized as the environment changes. The 16 channel multiplexor output can be tied to an I/O pin, signals from the mux. Can then be passed through external filters and amplified before re-entering the COP8FLASH to be passed through the ADC. This allows sharing of the external signal conditioning circuit among multiple channels. The power save features make COP8FLASH an ideal solution for battery powered handheld devices. The MIWU inputs are ideal for low power key scan with minimal CPU overhead. In this application the CPU can be brought out of Idle mode when a keypress is detected. The 10-bit ADC provides a single chip application for touch screen applications by eliminating many external components. Those systems requiring manufacturing diagnostics can easily be designed to self test and then be reloaded with production firmware before shipment. External components or test sockets are not needed to contain dedicated test programs.
The COP8FLASH microcontroller has a complete set of development support tools. You can setup an integrated development environment using the free IDE. The COP8 assembler and ISP software program, FLASHWIN, are free of charge. The C-Compiler from IAR and Byte Craft also support COP8 products. There is also a reference design board which is available at a nominal fee. You can obtain additional information by visiting our website.
The ISE interfaces the COP8FLASH through alternate functions of port G pins G0-G3 and the Reset pin. The physical connection between the ISE and the COP8FLASH is implemented using a 2x7 ( 10 mil centered) male header. During development phase, the PCB is assembled with the header mounted on the board. Using a mating connector, the ISE is connected to the target system. The dual row header carries both debug signals and application state of the port pins. The ISE recreates signal portion of the port G pins and the RESET on the header row connected to the application circuit. When the system is not in debug mode, the two rows of the header can be shorted using jumper blocks. For production purpose the header is omitted and copper traces are used to permanently short circuit the footprints of the dual row header.
There are many powerful features on the ISE which allow full speed, real time emulation of your code and analog signals. Because the emulator does not need a dedicated port, all the ports and signals are completely available during emulation.
The entry level ISE model sells for $235, and allows you limited debugging ability. The mid-level model sells for $800. It gives you trace and software break capability. The High end model packs a lot of features. It has hardware breakpoints, real-time trace buffer, and real-time data trace. Visit our website to purchase or get more information on the model of your choice.
For $99 you can order the COP8FLASH reference design board. You can place the order from national’s COP8 website. It includes the board, lots of host software and the on-board firmware. Integrated on the board are many useful functions which demonstrate the capabilities of the COP8FLASH. These functions include a multimeter, several communications interface ports, a matrix LC display, temperature and light sensors. There are expansion connectors and hook for future expansions. Visit the web site to place your orders: www.national.com/cop8flash.
You can obtain more information on COP8FLASH by visiting our website. The information available include the Roadmap, documentation, application notes, the design contest. There are free downloads and design tools . Place your orders online for parts, tools or samples.
This is a snap shot of the FLASHWIN program’s main Menu. It is a Windows based program which supports ISP over PC parallel port by emulating the MICROWIRE interface. Wiring diagram of the interface cable is also shown here. The program allows downloading and reprogramming COP8FLASH from a PC using the 4-wire MICROWIRE interface cable. Free copies can be downloaded from the National’s COP8FLASH Website.
National can send you a CD containing all the available free software tools(including latest assembler, simulator and IDE), documentation and demo versions of the C-compilers. You can order the CD for $3 plus shipping fee from National’s website. Metalink has a CD containing fully functional copy of their Windows Debugger. The same CD ships will all development tools orders. The cost for this CD is $199 and is available from Metalink.
Precise Analog Emulation and True In-System-Programmability Introduction to COP8FLASH Microcontrollers Fall 2000/ Updated 11/01
COP8 CORE 8 BIT CORE Modified HARVARD Architecture CLOCK HALT IDLE WAKE UP RESET INTERRUPT CONTROLLER ALU CPU Registers MICROWIRE + SPI INSTR DECODE LOGIC ILLEGAL CONDITION DETECT ADDR REG PC PSW ICNTRL CNTRL S A B X SP 16 BIT TIMER T1
COP8Flash PERIPHERALS IDLE Timer (T0) 1KB RAM WATCHDOG Clock Monitor Full Duplex USART Brown Out Oscillator Dual Clock Clock Doubler 32KB FLASH 16 Bit Timers T3 (50ns) T2 (50ns) BOOT ROM 1KB UP 8 10 Bit A/D I/O Ports D F C G L B E A MULTI INPUT WAKE
Idle Mode, timer T0 and selected oscillator active
Multi-Input Wakeup, to exit power save modes based on external events
Operating Voltages down to 2.7V
COP8FLASH Oscillator modes High Speed Mode Dual Clock Fast Dual Clock Slow Reset 2MHz All frequency values assume 10MHz/32kHz external oscillators 20MHz CPU clock 20MHz CPU clock 32kHz 64kHz CPU clock 32kHz Halt Halt Halt Idle Idle Idle
T1 16-bit multifunction timer, clocked by instruction clock (500ns@10MHz oscillator)
T2, T3 16-bit high-speed multifunction timers, clocked at instruction clock or CPU clock (500ns/50ns)
T1,T2,T3 Operating Modes:
Processor Independent PWM
Multifunction Timer Block Diagram TxA Underflow SEL Internal Data Bus 16 Bit Autoreload/Capture Register RA 16 Bit Timer/Counter 16 Bit Autoreload/Capture Register RB TxPNDB TxPNDA TxC0 TxB Edge Selector Logic Edge Selector Logic Instruction clock CPU clock